1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
35 #include <linux/of.h>
36 #include <linux/of_device.h>
37 #include <linux/of_mtd.h>
38
39 #include <asm/mach/flash.h>
40 #include <linux/platform_data/mtd-mxc_nand.h>
41
42 #define DRIVER_NAME "mxc_nand"
43
44 /* Addresses for NFC registers */
45 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
46 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
47 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
48 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
49 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
50 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
51 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
52 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
53 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
54 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
55 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
56 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
57 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
58 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
59 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
60 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
61 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
62 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
63 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
64 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
65 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
66 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
67
68 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
69 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
70 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
71 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
72 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
73 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
74 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
75 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
76 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
77 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
78
79 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
80
81 /*
82 * Operation modes for the NFC. Valid for v1, v2 and v3
83 * type controllers.
84 */
85 #define NFC_CMD (1 << 0)
86 #define NFC_ADDR (1 << 1)
87 #define NFC_INPUT (1 << 2)
88 #define NFC_OUTPUT (1 << 3)
89 #define NFC_ID (1 << 4)
90 #define NFC_STATUS (1 << 5)
91
92 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
93 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
94
95 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
96 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
97 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
98
99 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
100
101 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
102
103 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
104 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
105 #define NFC_V3_WRPROT_LOCK (1 << 1)
106 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
107 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
108
109 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
110
111 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
112 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
113 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
114 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
115 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
116 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
117 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
118 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
119 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
120 #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
121 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
122 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
123 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
124 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
125
126 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
127 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
128 #define NFC_V3_CONFIG3_FW8 (1 << 3)
129 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
130 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
131 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
132 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
133
134 #define NFC_V3_IPC (host->regs_ip + 0x2C)
135 #define NFC_V3_IPC_CREQ (1 << 0)
136 #define NFC_V3_IPC_INT (1 << 31)
137
138 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
139
140 struct mxc_nand_host;
141
142 struct mxc_nand_devtype_data {
143 void (*preset)(struct mtd_info *);
144 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
145 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
146 void (*send_page)(struct mtd_info *, unsigned int);
147 void (*send_read_id)(struct mxc_nand_host *);
148 uint16_t (*get_dev_status)(struct mxc_nand_host *);
149 int (*check_int)(struct mxc_nand_host *);
150 void (*irq_control)(struct mxc_nand_host *, int);
151 u32 (*get_ecc_status)(struct mxc_nand_host *);
152 struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
153 void (*select_chip)(struct mtd_info *mtd, int chip);
154 int (*correct_data)(struct mtd_info *mtd, u_char *dat,
155 u_char *read_ecc, u_char *calc_ecc);
156
157 /*
158 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
159 * (CONFIG1:INT_MSK is set). To handle this the driver uses
160 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
161 */
162 int irqpending_quirk;
163 int needs_ip;
164
165 size_t regs_offset;
166 size_t spare0_offset;
167 size_t axi_offset;
168
169 int spare_len;
170 int eccbytes;
171 int eccsize;
172 int ppb_shift;
173 };
174
175 struct mxc_nand_host {
176 struct mtd_info mtd;
177 struct nand_chip nand;
178 struct device *dev;
179
180 void __iomem *spare0;
181 void __iomem *main_area0;
182
183 void __iomem *base;
184 void __iomem *regs;
185 void __iomem *regs_axi;
186 void __iomem *regs_ip;
187 int status_request;
188 struct clk *clk;
189 int clk_act;
190 int irq;
191 int eccsize;
192 int used_oobsize;
193 int active_cs;
194
195 struct completion op_completion;
196
197 uint8_t *data_buf;
198 unsigned int buf_start;
199
200 const struct mxc_nand_devtype_data *devtype_data;
201 struct mxc_nand_platform_data pdata;
202 };
203
204 /* OOB placement block for use with hardware ecc generation */
205 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
206 .eccbytes = 5,
207 .eccpos = {6, 7, 8, 9, 10},
208 .oobfree = {{0, 5}, {12, 4}, }
209 };
210
211 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
212 .eccbytes = 20,
213 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
214 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
215 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
216 };
217
218 /* OOB description for 512 byte pages with 16 byte OOB */
219 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
220 .eccbytes = 1 * 9,
221 .eccpos = {
222 7, 8, 9, 10, 11, 12, 13, 14, 15
223 },
224 .oobfree = {
225 {.offset = 0, .length = 5}
226 }
227 };
228
229 /* OOB description for 2048 byte pages with 64 byte OOB */
230 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
231 .eccbytes = 4 * 9,
232 .eccpos = {
233 7, 8, 9, 10, 11, 12, 13, 14, 15,
234 23, 24, 25, 26, 27, 28, 29, 30, 31,
235 39, 40, 41, 42, 43, 44, 45, 46, 47,
236 55, 56, 57, 58, 59, 60, 61, 62, 63
237 },
238 .oobfree = {
239 {.offset = 2, .length = 4},
240 {.offset = 16, .length = 7},
241 {.offset = 32, .length = 7},
242 {.offset = 48, .length = 7}
243 }
244 };
245
246 /* OOB description for 4096 byte pages with 128 byte OOB */
247 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
248 .eccbytes = 8 * 9,
249 .eccpos = {
250 7, 8, 9, 10, 11, 12, 13, 14, 15,
251 23, 24, 25, 26, 27, 28, 29, 30, 31,
252 39, 40, 41, 42, 43, 44, 45, 46, 47,
253 55, 56, 57, 58, 59, 60, 61, 62, 63,
254 71, 72, 73, 74, 75, 76, 77, 78, 79,
255 87, 88, 89, 90, 91, 92, 93, 94, 95,
256 103, 104, 105, 106, 107, 108, 109, 110, 111,
257 119, 120, 121, 122, 123, 124, 125, 126, 127,
258 },
259 .oobfree = {
260 {.offset = 2, .length = 4},
261 {.offset = 16, .length = 7},
262 {.offset = 32, .length = 7},
263 {.offset = 48, .length = 7},
264 {.offset = 64, .length = 7},
265 {.offset = 80, .length = 7},
266 {.offset = 96, .length = 7},
267 {.offset = 112, .length = 7},
268 }
269 };
270
271 static const char * const part_probes[] = {
272 "cmdlinepart", "RedBoot", "ofpart", NULL };
273
memcpy32_fromio(void * trg,const void __iomem * src,size_t size)274 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
275 {
276 int i;
277 u32 *t = trg;
278 const __iomem u32 *s = src;
279
280 for (i = 0; i < (size >> 2); i++)
281 *t++ = __raw_readl(s++);
282 }
283
memcpy16_fromio(void * trg,const void __iomem * src,size_t size)284 static void memcpy16_fromio(void *trg, const void __iomem *src, size_t size)
285 {
286 int i;
287 u16 *t = trg;
288 const __iomem u16 *s = src;
289
290 /* We assume that src (IO) is always 32bit aligned */
291 if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) {
292 memcpy32_fromio(trg, src, size);
293 return;
294 }
295
296 for (i = 0; i < (size >> 1); i++)
297 *t++ = __raw_readw(s++);
298 }
299
memcpy32_toio(void __iomem * trg,const void * src,int size)300 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
301 {
302 /* __iowrite32_copy use 32bit size values so divide by 4 */
303 __iowrite32_copy(trg, src, size / 4);
304 }
305
memcpy16_toio(void __iomem * trg,const void * src,int size)306 static void memcpy16_toio(void __iomem *trg, const void *src, int size)
307 {
308 int i;
309 __iomem u16 *t = trg;
310 const u16 *s = src;
311
312 /* We assume that trg (IO) is always 32bit aligned */
313 if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) {
314 memcpy32_toio(trg, src, size);
315 return;
316 }
317
318 for (i = 0; i < (size >> 1); i++)
319 __raw_writew(*s++, t++);
320 }
321
check_int_v3(struct mxc_nand_host * host)322 static int check_int_v3(struct mxc_nand_host *host)
323 {
324 uint32_t tmp;
325
326 tmp = readl(NFC_V3_IPC);
327 if (!(tmp & NFC_V3_IPC_INT))
328 return 0;
329
330 tmp &= ~NFC_V3_IPC_INT;
331 writel(tmp, NFC_V3_IPC);
332
333 return 1;
334 }
335
check_int_v1_v2(struct mxc_nand_host * host)336 static int check_int_v1_v2(struct mxc_nand_host *host)
337 {
338 uint32_t tmp;
339
340 tmp = readw(NFC_V1_V2_CONFIG2);
341 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
342 return 0;
343
344 if (!host->devtype_data->irqpending_quirk)
345 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
346
347 return 1;
348 }
349
irq_control_v1_v2(struct mxc_nand_host * host,int activate)350 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
351 {
352 uint16_t tmp;
353
354 tmp = readw(NFC_V1_V2_CONFIG1);
355
356 if (activate)
357 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
358 else
359 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
360
361 writew(tmp, NFC_V1_V2_CONFIG1);
362 }
363
irq_control_v3(struct mxc_nand_host * host,int activate)364 static void irq_control_v3(struct mxc_nand_host *host, int activate)
365 {
366 uint32_t tmp;
367
368 tmp = readl(NFC_V3_CONFIG2);
369
370 if (activate)
371 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
372 else
373 tmp |= NFC_V3_CONFIG2_INT_MSK;
374
375 writel(tmp, NFC_V3_CONFIG2);
376 }
377
irq_control(struct mxc_nand_host * host,int activate)378 static void irq_control(struct mxc_nand_host *host, int activate)
379 {
380 if (host->devtype_data->irqpending_quirk) {
381 if (activate)
382 enable_irq(host->irq);
383 else
384 disable_irq_nosync(host->irq);
385 } else {
386 host->devtype_data->irq_control(host, activate);
387 }
388 }
389
get_ecc_status_v1(struct mxc_nand_host * host)390 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
391 {
392 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
393 }
394
get_ecc_status_v2(struct mxc_nand_host * host)395 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
396 {
397 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
398 }
399
get_ecc_status_v3(struct mxc_nand_host * host)400 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
401 {
402 return readl(NFC_V3_ECC_STATUS_RESULT);
403 }
404
mxc_nfc_irq(int irq,void * dev_id)405 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
406 {
407 struct mxc_nand_host *host = dev_id;
408
409 if (!host->devtype_data->check_int(host))
410 return IRQ_NONE;
411
412 irq_control(host, 0);
413
414 complete(&host->op_completion);
415
416 return IRQ_HANDLED;
417 }
418
419 /* This function polls the NANDFC to wait for the basic operation to
420 * complete by checking the INT bit of config2 register.
421 */
wait_op_done(struct mxc_nand_host * host,int useirq)422 static int wait_op_done(struct mxc_nand_host *host, int useirq)
423 {
424 int ret = 0;
425
426 /*
427 * If operation is already complete, don't bother to setup an irq or a
428 * loop.
429 */
430 if (host->devtype_data->check_int(host))
431 return 0;
432
433 if (useirq) {
434 unsigned long timeout;
435
436 reinit_completion(&host->op_completion);
437
438 irq_control(host, 1);
439
440 timeout = wait_for_completion_timeout(&host->op_completion, HZ);
441 if (!timeout && !host->devtype_data->check_int(host)) {
442 dev_dbg(host->dev, "timeout waiting for irq\n");
443 ret = -ETIMEDOUT;
444 }
445 } else {
446 int max_retries = 8000;
447 int done;
448
449 do {
450 udelay(1);
451
452 done = host->devtype_data->check_int(host);
453 if (done)
454 break;
455
456 } while (--max_retries);
457
458 if (!done) {
459 dev_dbg(host->dev, "timeout polling for completion\n");
460 ret = -ETIMEDOUT;
461 }
462 }
463
464 WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
465
466 return ret;
467 }
468
send_cmd_v3(struct mxc_nand_host * host,uint16_t cmd,int useirq)469 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
470 {
471 /* fill command */
472 writel(cmd, NFC_V3_FLASH_CMD);
473
474 /* send out command */
475 writel(NFC_CMD, NFC_V3_LAUNCH);
476
477 /* Wait for operation to complete */
478 wait_op_done(host, useirq);
479 }
480
481 /* This function issues the specified command to the NAND device and
482 * waits for completion. */
send_cmd_v1_v2(struct mxc_nand_host * host,uint16_t cmd,int useirq)483 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
484 {
485 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
486
487 writew(cmd, NFC_V1_V2_FLASH_CMD);
488 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
489
490 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
491 int max_retries = 100;
492 /* Reset completion is indicated by NFC_CONFIG2 */
493 /* being set to 0 */
494 while (max_retries-- > 0) {
495 if (readw(NFC_V1_V2_CONFIG2) == 0) {
496 break;
497 }
498 udelay(1);
499 }
500 if (max_retries < 0)
501 pr_debug("%s: RESET failed\n", __func__);
502 } else {
503 /* Wait for operation to complete */
504 wait_op_done(host, useirq);
505 }
506 }
507
send_addr_v3(struct mxc_nand_host * host,uint16_t addr,int islast)508 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
509 {
510 /* fill address */
511 writel(addr, NFC_V3_FLASH_ADDR0);
512
513 /* send out address */
514 writel(NFC_ADDR, NFC_V3_LAUNCH);
515
516 wait_op_done(host, 0);
517 }
518
519 /* This function sends an address (or partial address) to the
520 * NAND device. The address is used to select the source/destination for
521 * a NAND command. */
send_addr_v1_v2(struct mxc_nand_host * host,uint16_t addr,int islast)522 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
523 {
524 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
525
526 writew(addr, NFC_V1_V2_FLASH_ADDR);
527 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
528
529 /* Wait for operation to complete */
530 wait_op_done(host, islast);
531 }
532
send_page_v3(struct mtd_info * mtd,unsigned int ops)533 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
534 {
535 struct nand_chip *nand_chip = mtd->priv;
536 struct mxc_nand_host *host = nand_chip->priv;
537 uint32_t tmp;
538
539 tmp = readl(NFC_V3_CONFIG1);
540 tmp &= ~(7 << 4);
541 writel(tmp, NFC_V3_CONFIG1);
542
543 /* transfer data from NFC ram to nand */
544 writel(ops, NFC_V3_LAUNCH);
545
546 wait_op_done(host, false);
547 }
548
send_page_v2(struct mtd_info * mtd,unsigned int ops)549 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
550 {
551 struct nand_chip *nand_chip = mtd->priv;
552 struct mxc_nand_host *host = nand_chip->priv;
553
554 /* NANDFC buffer 0 is used for page read/write */
555 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
556
557 writew(ops, NFC_V1_V2_CONFIG2);
558
559 /* Wait for operation to complete */
560 wait_op_done(host, true);
561 }
562
send_page_v1(struct mtd_info * mtd,unsigned int ops)563 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
564 {
565 struct nand_chip *nand_chip = mtd->priv;
566 struct mxc_nand_host *host = nand_chip->priv;
567 int bufs, i;
568
569 if (mtd->writesize > 512)
570 bufs = 4;
571 else
572 bufs = 1;
573
574 for (i = 0; i < bufs; i++) {
575
576 /* NANDFC buffer 0 is used for page read/write */
577 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
578
579 writew(ops, NFC_V1_V2_CONFIG2);
580
581 /* Wait for operation to complete */
582 wait_op_done(host, true);
583 }
584 }
585
send_read_id_v3(struct mxc_nand_host * host)586 static void send_read_id_v3(struct mxc_nand_host *host)
587 {
588 /* Read ID into main buffer */
589 writel(NFC_ID, NFC_V3_LAUNCH);
590
591 wait_op_done(host, true);
592
593 memcpy32_fromio(host->data_buf, host->main_area0, 16);
594 }
595
596 /* Request the NANDFC to perform a read of the NAND device ID. */
send_read_id_v1_v2(struct mxc_nand_host * host)597 static void send_read_id_v1_v2(struct mxc_nand_host *host)
598 {
599 /* NANDFC buffer 0 is used for device ID output */
600 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
601
602 writew(NFC_ID, NFC_V1_V2_CONFIG2);
603
604 /* Wait for operation to complete */
605 wait_op_done(host, true);
606
607 memcpy32_fromio(host->data_buf, host->main_area0, 16);
608 }
609
get_dev_status_v3(struct mxc_nand_host * host)610 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
611 {
612 writew(NFC_STATUS, NFC_V3_LAUNCH);
613 wait_op_done(host, true);
614
615 return readl(NFC_V3_CONFIG1) >> 16;
616 }
617
618 /* This function requests the NANDFC to perform a read of the
619 * NAND device status and returns the current status. */
get_dev_status_v1_v2(struct mxc_nand_host * host)620 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
621 {
622 void __iomem *main_buf = host->main_area0;
623 uint32_t store;
624 uint16_t ret;
625
626 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
627
628 /*
629 * The device status is stored in main_area0. To
630 * prevent corruption of the buffer save the value
631 * and restore it afterwards.
632 */
633 store = readl(main_buf);
634
635 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
636 wait_op_done(host, true);
637
638 ret = readw(main_buf);
639
640 writel(store, main_buf);
641
642 return ret;
643 }
644
645 /* This functions is used by upper layer to checks if device is ready */
mxc_nand_dev_ready(struct mtd_info * mtd)646 static int mxc_nand_dev_ready(struct mtd_info *mtd)
647 {
648 /*
649 * NFC handles R/B internally. Therefore, this function
650 * always returns status as ready.
651 */
652 return 1;
653 }
654
mxc_nand_enable_hwecc(struct mtd_info * mtd,int mode)655 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
656 {
657 /*
658 * If HW ECC is enabled, we turn it on during init. There is
659 * no need to enable again here.
660 */
661 }
662
mxc_nand_correct_data_v1(struct mtd_info * mtd,u_char * dat,u_char * read_ecc,u_char * calc_ecc)663 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
664 u_char *read_ecc, u_char *calc_ecc)
665 {
666 struct nand_chip *nand_chip = mtd->priv;
667 struct mxc_nand_host *host = nand_chip->priv;
668
669 /*
670 * 1-Bit errors are automatically corrected in HW. No need for
671 * additional correction. 2-Bit errors cannot be corrected by
672 * HW ECC, so we need to return failure
673 */
674 uint16_t ecc_status = get_ecc_status_v1(host);
675
676 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
677 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
678 return -1;
679 }
680
681 return 0;
682 }
683
mxc_nand_correct_data_v2_v3(struct mtd_info * mtd,u_char * dat,u_char * read_ecc,u_char * calc_ecc)684 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
685 u_char *read_ecc, u_char *calc_ecc)
686 {
687 struct nand_chip *nand_chip = mtd->priv;
688 struct mxc_nand_host *host = nand_chip->priv;
689 u32 ecc_stat, err;
690 int no_subpages = 1;
691 int ret = 0;
692 u8 ecc_bit_mask, err_limit;
693
694 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
695 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
696
697 no_subpages = mtd->writesize >> 9;
698
699 ecc_stat = host->devtype_data->get_ecc_status(host);
700
701 do {
702 err = ecc_stat & ecc_bit_mask;
703 if (err > err_limit) {
704 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
705 return -1;
706 } else {
707 ret += err;
708 }
709 ecc_stat >>= 4;
710 } while (--no_subpages);
711
712 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
713
714 return ret;
715 }
716
mxc_nand_calculate_ecc(struct mtd_info * mtd,const u_char * dat,u_char * ecc_code)717 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
718 u_char *ecc_code)
719 {
720 return 0;
721 }
722
mxc_nand_read_byte(struct mtd_info * mtd)723 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
724 {
725 struct nand_chip *nand_chip = mtd->priv;
726 struct mxc_nand_host *host = nand_chip->priv;
727 uint8_t ret;
728
729 /* Check for status request */
730 if (host->status_request)
731 return host->devtype_data->get_dev_status(host) & 0xFF;
732
733 if (nand_chip->options & NAND_BUSWIDTH_16) {
734 /* only take the lower byte of each word */
735 ret = *(uint16_t *)(host->data_buf + host->buf_start);
736
737 host->buf_start += 2;
738 } else {
739 ret = *(uint8_t *)(host->data_buf + host->buf_start);
740 host->buf_start++;
741 }
742
743 pr_debug("%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
744 return ret;
745 }
746
mxc_nand_read_word(struct mtd_info * mtd)747 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
748 {
749 struct nand_chip *nand_chip = mtd->priv;
750 struct mxc_nand_host *host = nand_chip->priv;
751 uint16_t ret;
752
753 ret = *(uint16_t *)(host->data_buf + host->buf_start);
754 host->buf_start += 2;
755
756 return ret;
757 }
758
759 /* Write data of length len to buffer buf. The data to be
760 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
761 * Operation by the NFC, the data is written to NAND Flash */
mxc_nand_write_buf(struct mtd_info * mtd,const u_char * buf,int len)762 static void mxc_nand_write_buf(struct mtd_info *mtd,
763 const u_char *buf, int len)
764 {
765 struct nand_chip *nand_chip = mtd->priv;
766 struct mxc_nand_host *host = nand_chip->priv;
767 u16 col = host->buf_start;
768 int n = mtd->oobsize + mtd->writesize - col;
769
770 n = min(n, len);
771
772 memcpy(host->data_buf + col, buf, n);
773
774 host->buf_start += n;
775 }
776
777 /* Read the data buffer from the NAND Flash. To read the data from NAND
778 * Flash first the data output cycle is initiated by the NFC, which copies
779 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
780 */
mxc_nand_read_buf(struct mtd_info * mtd,u_char * buf,int len)781 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
782 {
783 struct nand_chip *nand_chip = mtd->priv;
784 struct mxc_nand_host *host = nand_chip->priv;
785 u16 col = host->buf_start;
786 int n = mtd->oobsize + mtd->writesize - col;
787
788 n = min(n, len);
789
790 memcpy(buf, host->data_buf + col, n);
791
792 host->buf_start += n;
793 }
794
795 /* This function is used by upper layer for select and
796 * deselect of the NAND chip */
mxc_nand_select_chip_v1_v3(struct mtd_info * mtd,int chip)797 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
798 {
799 struct nand_chip *nand_chip = mtd->priv;
800 struct mxc_nand_host *host = nand_chip->priv;
801
802 if (chip == -1) {
803 /* Disable the NFC clock */
804 if (host->clk_act) {
805 clk_disable_unprepare(host->clk);
806 host->clk_act = 0;
807 }
808 return;
809 }
810
811 if (!host->clk_act) {
812 /* Enable the NFC clock */
813 clk_prepare_enable(host->clk);
814 host->clk_act = 1;
815 }
816 }
817
mxc_nand_select_chip_v2(struct mtd_info * mtd,int chip)818 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
819 {
820 struct nand_chip *nand_chip = mtd->priv;
821 struct mxc_nand_host *host = nand_chip->priv;
822
823 if (chip == -1) {
824 /* Disable the NFC clock */
825 if (host->clk_act) {
826 clk_disable_unprepare(host->clk);
827 host->clk_act = 0;
828 }
829 return;
830 }
831
832 if (!host->clk_act) {
833 /* Enable the NFC clock */
834 clk_prepare_enable(host->clk);
835 host->clk_act = 1;
836 }
837
838 host->active_cs = chip;
839 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
840 }
841
842 /*
843 * The controller splits a page into data chunks of 512 bytes + partial oob.
844 * There are writesize / 512 such chunks, the size of the partial oob parts is
845 * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then
846 * contains additionally the byte lost by rounding (if any).
847 * This function handles the needed shuffling between host->data_buf (which
848 * holds a page in natural order, i.e. writesize bytes data + oobsize bytes
849 * spare) and the NFC buffer.
850 */
copy_spare(struct mtd_info * mtd,bool bfrom)851 static void copy_spare(struct mtd_info *mtd, bool bfrom)
852 {
853 struct nand_chip *this = mtd->priv;
854 struct mxc_nand_host *host = this->priv;
855 u16 i, oob_chunk_size;
856 u16 num_chunks = mtd->writesize / 512;
857
858 u8 *d = host->data_buf + mtd->writesize;
859 u8 __iomem *s = host->spare0;
860 u16 sparebuf_size = host->devtype_data->spare_len;
861
862 /* size of oob chunk for all but possibly the last one */
863 oob_chunk_size = (host->used_oobsize / num_chunks) & ~1;
864
865 if (bfrom) {
866 for (i = 0; i < num_chunks - 1; i++)
867 memcpy16_fromio(d + i * oob_chunk_size,
868 s + i * sparebuf_size,
869 oob_chunk_size);
870
871 /* the last chunk */
872 memcpy16_fromio(d + i * oob_chunk_size,
873 s + i * sparebuf_size,
874 host->used_oobsize - i * oob_chunk_size);
875 } else {
876 for (i = 0; i < num_chunks - 1; i++)
877 memcpy16_toio(&s[i * sparebuf_size],
878 &d[i * oob_chunk_size],
879 oob_chunk_size);
880
881 /* the last chunk */
882 memcpy16_toio(&s[i * sparebuf_size],
883 &d[i * oob_chunk_size],
884 host->used_oobsize - i * oob_chunk_size);
885 }
886 }
887
888 /*
889 * MXC NANDFC can only perform full page+spare or spare-only read/write. When
890 * the upper layers perform a read/write buf operation, the saved column address
891 * is used to index into the full page. So usually this function is called with
892 * column == 0 (unless no column cycle is needed indicated by column == -1)
893 */
mxc_do_addr_cycle(struct mtd_info * mtd,int column,int page_addr)894 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
895 {
896 struct nand_chip *nand_chip = mtd->priv;
897 struct mxc_nand_host *host = nand_chip->priv;
898
899 /* Write out column address, if necessary */
900 if (column != -1) {
901 host->devtype_data->send_addr(host, column & 0xff,
902 page_addr == -1);
903 if (mtd->writesize > 512)
904 /* another col addr cycle for 2k page */
905 host->devtype_data->send_addr(host,
906 (column >> 8) & 0xff,
907 false);
908 }
909
910 /* Write out page address, if necessary */
911 if (page_addr != -1) {
912 /* paddr_0 - p_addr_7 */
913 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
914
915 if (mtd->writesize > 512) {
916 if (mtd->size >= 0x10000000) {
917 /* paddr_8 - paddr_15 */
918 host->devtype_data->send_addr(host,
919 (page_addr >> 8) & 0xff,
920 false);
921 host->devtype_data->send_addr(host,
922 (page_addr >> 16) & 0xff,
923 true);
924 } else
925 /* paddr_8 - paddr_15 */
926 host->devtype_data->send_addr(host,
927 (page_addr >> 8) & 0xff, true);
928 } else {
929 /* One more address cycle for higher density devices */
930 if (mtd->size >= 0x4000000) {
931 /* paddr_8 - paddr_15 */
932 host->devtype_data->send_addr(host,
933 (page_addr >> 8) & 0xff,
934 false);
935 host->devtype_data->send_addr(host,
936 (page_addr >> 16) & 0xff,
937 true);
938 } else
939 /* paddr_8 - paddr_15 */
940 host->devtype_data->send_addr(host,
941 (page_addr >> 8) & 0xff, true);
942 }
943 }
944 }
945
946 /*
947 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
948 * on how much oob the nand chip has. For 8bit ecc we need at least
949 * 26 bytes of oob data per 512 byte block.
950 */
get_eccsize(struct mtd_info * mtd)951 static int get_eccsize(struct mtd_info *mtd)
952 {
953 int oobbytes_per_512 = 0;
954
955 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
956
957 if (oobbytes_per_512 < 26)
958 return 4;
959 else
960 return 8;
961 }
962
ecc_8bit_layout_4k(struct nand_ecclayout * layout)963 static void ecc_8bit_layout_4k(struct nand_ecclayout *layout)
964 {
965 int i, j;
966
967 layout->eccbytes = 8*18;
968 for (i = 0; i < 8; i++)
969 for (j = 0; j < 18; j++)
970 layout->eccpos[i*18 + j] = i*26 + j + 7;
971
972 layout->oobfree[0].offset = 2;
973 layout->oobfree[0].length = 4;
974 for (i = 1; i < 8; i++) {
975 layout->oobfree[i].offset = i*26;
976 layout->oobfree[i].length = 7;
977 }
978 }
979
preset_v1(struct mtd_info * mtd)980 static void preset_v1(struct mtd_info *mtd)
981 {
982 struct nand_chip *nand_chip = mtd->priv;
983 struct mxc_nand_host *host = nand_chip->priv;
984 uint16_t config1 = 0;
985
986 if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize)
987 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
988
989 if (!host->devtype_data->irqpending_quirk)
990 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
991
992 host->eccsize = 1;
993
994 writew(config1, NFC_V1_V2_CONFIG1);
995 /* preset operation */
996
997 /* Unlock the internal RAM Buffer */
998 writew(0x2, NFC_V1_V2_CONFIG);
999
1000 /* Blocks to be unlocked */
1001 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
1002 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
1003
1004 /* Unlock Block Command for given address range */
1005 writew(0x4, NFC_V1_V2_WRPROT);
1006 }
1007
preset_v2(struct mtd_info * mtd)1008 static void preset_v2(struct mtd_info *mtd)
1009 {
1010 struct nand_chip *nand_chip = mtd->priv;
1011 struct mxc_nand_host *host = nand_chip->priv;
1012 uint16_t config1 = 0;
1013
1014 config1 |= NFC_V2_CONFIG1_FP_INT;
1015
1016 if (!host->devtype_data->irqpending_quirk)
1017 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1018
1019 if (mtd->writesize) {
1020 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
1021
1022 if (nand_chip->ecc.mode == NAND_ECC_HW)
1023 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1024
1025 host->eccsize = get_eccsize(mtd);
1026 if (host->eccsize == 4)
1027 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
1028
1029 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
1030 } else {
1031 host->eccsize = 1;
1032 }
1033
1034 writew(config1, NFC_V1_V2_CONFIG1);
1035 /* preset operation */
1036
1037 /* Unlock the internal RAM Buffer */
1038 writew(0x2, NFC_V1_V2_CONFIG);
1039
1040 /* Blocks to be unlocked */
1041 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
1042 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
1043 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
1044 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
1045 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
1046 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
1047 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
1048 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
1049
1050 /* Unlock Block Command for given address range */
1051 writew(0x4, NFC_V1_V2_WRPROT);
1052 }
1053
preset_v3(struct mtd_info * mtd)1054 static void preset_v3(struct mtd_info *mtd)
1055 {
1056 struct nand_chip *chip = mtd->priv;
1057 struct mxc_nand_host *host = chip->priv;
1058 uint32_t config2, config3;
1059 int i, addr_phases;
1060
1061 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
1062 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
1063
1064 /* Unlock the internal RAM Buffer */
1065 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1066 NFC_V3_WRPROT);
1067
1068 /* Blocks to be unlocked */
1069 for (i = 0; i < NAND_MAX_CHIPS; i++)
1070 writel(0x0 | (0xffff << 16),
1071 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1072
1073 writel(0, NFC_V3_IPC);
1074
1075 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1076 NFC_V3_CONFIG2_2CMD_PHASES |
1077 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1078 NFC_V3_CONFIG2_ST_CMD(0x70) |
1079 NFC_V3_CONFIG2_INT_MSK |
1080 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1081
1082 addr_phases = fls(chip->pagemask) >> 3;
1083
1084 if (mtd->writesize == 2048) {
1085 config2 |= NFC_V3_CONFIG2_PS_2048;
1086 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1087 } else if (mtd->writesize == 4096) {
1088 config2 |= NFC_V3_CONFIG2_PS_4096;
1089 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1090 } else {
1091 config2 |= NFC_V3_CONFIG2_PS_512;
1092 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1093 }
1094
1095 if (mtd->writesize) {
1096 if (chip->ecc.mode == NAND_ECC_HW)
1097 config2 |= NFC_V3_CONFIG2_ECC_EN;
1098
1099 config2 |= NFC_V3_CONFIG2_PPB(
1100 ffs(mtd->erasesize / mtd->writesize) - 6,
1101 host->devtype_data->ppb_shift);
1102 host->eccsize = get_eccsize(mtd);
1103 if (host->eccsize == 8)
1104 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1105 }
1106
1107 writel(config2, NFC_V3_CONFIG2);
1108
1109 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1110 NFC_V3_CONFIG3_NO_SDMA |
1111 NFC_V3_CONFIG3_RBB_MODE |
1112 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1113 NFC_V3_CONFIG3_ADD_OP(0);
1114
1115 if (!(chip->options & NAND_BUSWIDTH_16))
1116 config3 |= NFC_V3_CONFIG3_FW8;
1117
1118 writel(config3, NFC_V3_CONFIG3);
1119
1120 writel(0, NFC_V3_DELAY_LINE);
1121 }
1122
1123 /* Used by the upper layer to write command to NAND Flash for
1124 * different operations to be carried out on NAND Flash */
mxc_nand_command(struct mtd_info * mtd,unsigned command,int column,int page_addr)1125 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1126 int column, int page_addr)
1127 {
1128 struct nand_chip *nand_chip = mtd->priv;
1129 struct mxc_nand_host *host = nand_chip->priv;
1130
1131 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1132 command, column, page_addr);
1133
1134 /* Reset command state information */
1135 host->status_request = false;
1136
1137 /* Command pre-processing step */
1138 switch (command) {
1139 case NAND_CMD_RESET:
1140 host->devtype_data->preset(mtd);
1141 host->devtype_data->send_cmd(host, command, false);
1142 break;
1143
1144 case NAND_CMD_STATUS:
1145 host->buf_start = 0;
1146 host->status_request = true;
1147
1148 host->devtype_data->send_cmd(host, command, true);
1149 WARN_ONCE(column != -1 || page_addr != -1,
1150 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1151 command, column, page_addr);
1152 mxc_do_addr_cycle(mtd, column, page_addr);
1153 break;
1154
1155 case NAND_CMD_READ0:
1156 case NAND_CMD_READOOB:
1157 if (command == NAND_CMD_READ0)
1158 host->buf_start = column;
1159 else
1160 host->buf_start = column + mtd->writesize;
1161
1162 command = NAND_CMD_READ0; /* only READ0 is valid */
1163
1164 host->devtype_data->send_cmd(host, command, false);
1165 WARN_ONCE(column < 0,
1166 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1167 command, column, page_addr);
1168 mxc_do_addr_cycle(mtd, 0, page_addr);
1169
1170 if (mtd->writesize > 512)
1171 host->devtype_data->send_cmd(host,
1172 NAND_CMD_READSTART, true);
1173
1174 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1175
1176 memcpy32_fromio(host->data_buf, host->main_area0,
1177 mtd->writesize);
1178 copy_spare(mtd, true);
1179 break;
1180
1181 case NAND_CMD_SEQIN:
1182 if (column >= mtd->writesize)
1183 /* call ourself to read a page */
1184 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1185
1186 host->buf_start = column;
1187
1188 host->devtype_data->send_cmd(host, command, false);
1189 WARN_ONCE(column < -1,
1190 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1191 command, column, page_addr);
1192 mxc_do_addr_cycle(mtd, 0, page_addr);
1193 break;
1194
1195 case NAND_CMD_PAGEPROG:
1196 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1197 copy_spare(mtd, false);
1198 host->devtype_data->send_page(mtd, NFC_INPUT);
1199 host->devtype_data->send_cmd(host, command, true);
1200 WARN_ONCE(column != -1 || page_addr != -1,
1201 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1202 command, column, page_addr);
1203 mxc_do_addr_cycle(mtd, column, page_addr);
1204 break;
1205
1206 case NAND_CMD_READID:
1207 host->devtype_data->send_cmd(host, command, true);
1208 mxc_do_addr_cycle(mtd, column, page_addr);
1209 host->devtype_data->send_read_id(host);
1210 host->buf_start = 0;
1211 break;
1212
1213 case NAND_CMD_ERASE1:
1214 case NAND_CMD_ERASE2:
1215 host->devtype_data->send_cmd(host, command, false);
1216 WARN_ONCE(column != -1,
1217 "Unexpected column value (cmd=%u, col=%d)\n",
1218 command, column);
1219 mxc_do_addr_cycle(mtd, column, page_addr);
1220
1221 break;
1222 case NAND_CMD_PARAM:
1223 host->devtype_data->send_cmd(host, command, false);
1224 mxc_do_addr_cycle(mtd, column, page_addr);
1225 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1226 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1227 host->buf_start = 0;
1228 break;
1229 default:
1230 WARN_ONCE(1, "Unimplemented command (cmd=%u)\n",
1231 command);
1232 break;
1233 }
1234 }
1235
1236 /*
1237 * The generic flash bbt decriptors overlap with our ecc
1238 * hardware, so define some i.MX specific ones.
1239 */
1240 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1241 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1242
1243 static struct nand_bbt_descr bbt_main_descr = {
1244 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1245 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1246 .offs = 0,
1247 .len = 4,
1248 .veroffs = 4,
1249 .maxblocks = 4,
1250 .pattern = bbt_pattern,
1251 };
1252
1253 static struct nand_bbt_descr bbt_mirror_descr = {
1254 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1255 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1256 .offs = 0,
1257 .len = 4,
1258 .veroffs = 4,
1259 .maxblocks = 4,
1260 .pattern = mirror_pattern,
1261 };
1262
1263 /* v1 + irqpending_quirk: i.MX21 */
1264 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1265 .preset = preset_v1,
1266 .send_cmd = send_cmd_v1_v2,
1267 .send_addr = send_addr_v1_v2,
1268 .send_page = send_page_v1,
1269 .send_read_id = send_read_id_v1_v2,
1270 .get_dev_status = get_dev_status_v1_v2,
1271 .check_int = check_int_v1_v2,
1272 .irq_control = irq_control_v1_v2,
1273 .get_ecc_status = get_ecc_status_v1,
1274 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1275 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1276 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1277 .select_chip = mxc_nand_select_chip_v1_v3,
1278 .correct_data = mxc_nand_correct_data_v1,
1279 .irqpending_quirk = 1,
1280 .needs_ip = 0,
1281 .regs_offset = 0xe00,
1282 .spare0_offset = 0x800,
1283 .spare_len = 16,
1284 .eccbytes = 3,
1285 .eccsize = 1,
1286 };
1287
1288 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1289 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1290 .preset = preset_v1,
1291 .send_cmd = send_cmd_v1_v2,
1292 .send_addr = send_addr_v1_v2,
1293 .send_page = send_page_v1,
1294 .send_read_id = send_read_id_v1_v2,
1295 .get_dev_status = get_dev_status_v1_v2,
1296 .check_int = check_int_v1_v2,
1297 .irq_control = irq_control_v1_v2,
1298 .get_ecc_status = get_ecc_status_v1,
1299 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1300 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1301 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1302 .select_chip = mxc_nand_select_chip_v1_v3,
1303 .correct_data = mxc_nand_correct_data_v1,
1304 .irqpending_quirk = 0,
1305 .needs_ip = 0,
1306 .regs_offset = 0xe00,
1307 .spare0_offset = 0x800,
1308 .axi_offset = 0,
1309 .spare_len = 16,
1310 .eccbytes = 3,
1311 .eccsize = 1,
1312 };
1313
1314 /* v21: i.MX25, i.MX35 */
1315 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1316 .preset = preset_v2,
1317 .send_cmd = send_cmd_v1_v2,
1318 .send_addr = send_addr_v1_v2,
1319 .send_page = send_page_v2,
1320 .send_read_id = send_read_id_v1_v2,
1321 .get_dev_status = get_dev_status_v1_v2,
1322 .check_int = check_int_v1_v2,
1323 .irq_control = irq_control_v1_v2,
1324 .get_ecc_status = get_ecc_status_v2,
1325 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1326 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1327 .ecclayout_4k = &nandv2_hw_eccoob_4k,
1328 .select_chip = mxc_nand_select_chip_v2,
1329 .correct_data = mxc_nand_correct_data_v2_v3,
1330 .irqpending_quirk = 0,
1331 .needs_ip = 0,
1332 .regs_offset = 0x1e00,
1333 .spare0_offset = 0x1000,
1334 .axi_offset = 0,
1335 .spare_len = 64,
1336 .eccbytes = 9,
1337 .eccsize = 0,
1338 };
1339
1340 /* v3.2a: i.MX51 */
1341 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1342 .preset = preset_v3,
1343 .send_cmd = send_cmd_v3,
1344 .send_addr = send_addr_v3,
1345 .send_page = send_page_v3,
1346 .send_read_id = send_read_id_v3,
1347 .get_dev_status = get_dev_status_v3,
1348 .check_int = check_int_v3,
1349 .irq_control = irq_control_v3,
1350 .get_ecc_status = get_ecc_status_v3,
1351 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1352 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1353 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1354 .select_chip = mxc_nand_select_chip_v1_v3,
1355 .correct_data = mxc_nand_correct_data_v2_v3,
1356 .irqpending_quirk = 0,
1357 .needs_ip = 1,
1358 .regs_offset = 0,
1359 .spare0_offset = 0x1000,
1360 .axi_offset = 0x1e00,
1361 .spare_len = 64,
1362 .eccbytes = 0,
1363 .eccsize = 0,
1364 .ppb_shift = 7,
1365 };
1366
1367 /* v3.2b: i.MX53 */
1368 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1369 .preset = preset_v3,
1370 .send_cmd = send_cmd_v3,
1371 .send_addr = send_addr_v3,
1372 .send_page = send_page_v3,
1373 .send_read_id = send_read_id_v3,
1374 .get_dev_status = get_dev_status_v3,
1375 .check_int = check_int_v3,
1376 .irq_control = irq_control_v3,
1377 .get_ecc_status = get_ecc_status_v3,
1378 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1379 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1380 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1381 .select_chip = mxc_nand_select_chip_v1_v3,
1382 .correct_data = mxc_nand_correct_data_v2_v3,
1383 .irqpending_quirk = 0,
1384 .needs_ip = 1,
1385 .regs_offset = 0,
1386 .spare0_offset = 0x1000,
1387 .axi_offset = 0x1e00,
1388 .spare_len = 64,
1389 .eccbytes = 0,
1390 .eccsize = 0,
1391 .ppb_shift = 8,
1392 };
1393
is_imx21_nfc(struct mxc_nand_host * host)1394 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1395 {
1396 return host->devtype_data == &imx21_nand_devtype_data;
1397 }
1398
is_imx27_nfc(struct mxc_nand_host * host)1399 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1400 {
1401 return host->devtype_data == &imx27_nand_devtype_data;
1402 }
1403
is_imx25_nfc(struct mxc_nand_host * host)1404 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1405 {
1406 return host->devtype_data == &imx25_nand_devtype_data;
1407 }
1408
is_imx51_nfc(struct mxc_nand_host * host)1409 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1410 {
1411 return host->devtype_data == &imx51_nand_devtype_data;
1412 }
1413
is_imx53_nfc(struct mxc_nand_host * host)1414 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1415 {
1416 return host->devtype_data == &imx53_nand_devtype_data;
1417 }
1418
1419 static const struct platform_device_id mxcnd_devtype[] = {
1420 {
1421 .name = "imx21-nand",
1422 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1423 }, {
1424 .name = "imx27-nand",
1425 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1426 }, {
1427 .name = "imx25-nand",
1428 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1429 }, {
1430 .name = "imx51-nand",
1431 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1432 }, {
1433 .name = "imx53-nand",
1434 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1435 }, {
1436 /* sentinel */
1437 }
1438 };
1439 MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1440
1441 #ifdef CONFIG_OF_MTD
1442 static const struct of_device_id mxcnd_dt_ids[] = {
1443 {
1444 .compatible = "fsl,imx21-nand",
1445 .data = &imx21_nand_devtype_data,
1446 }, {
1447 .compatible = "fsl,imx27-nand",
1448 .data = &imx27_nand_devtype_data,
1449 }, {
1450 .compatible = "fsl,imx25-nand",
1451 .data = &imx25_nand_devtype_data,
1452 }, {
1453 .compatible = "fsl,imx51-nand",
1454 .data = &imx51_nand_devtype_data,
1455 }, {
1456 .compatible = "fsl,imx53-nand",
1457 .data = &imx53_nand_devtype_data,
1458 },
1459 { /* sentinel */ }
1460 };
1461 MODULE_DEVICE_TABLE(of, mxcnd_dt_ids);
1462
mxcnd_probe_dt(struct mxc_nand_host * host)1463 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1464 {
1465 struct device_node *np = host->dev->of_node;
1466 struct mxc_nand_platform_data *pdata = &host->pdata;
1467 const struct of_device_id *of_id =
1468 of_match_device(mxcnd_dt_ids, host->dev);
1469 int buswidth;
1470
1471 if (!np)
1472 return 1;
1473
1474 if (of_get_nand_ecc_mode(np) >= 0)
1475 pdata->hw_ecc = 1;
1476
1477 pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
1478
1479 buswidth = of_get_nand_bus_width(np);
1480 if (buswidth < 0)
1481 return buswidth;
1482
1483 pdata->width = buswidth / 8;
1484
1485 host->devtype_data = of_id->data;
1486
1487 return 0;
1488 }
1489 #else
mxcnd_probe_dt(struct mxc_nand_host * host)1490 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1491 {
1492 return 1;
1493 }
1494 #endif
1495
mxcnd_probe(struct platform_device * pdev)1496 static int mxcnd_probe(struct platform_device *pdev)
1497 {
1498 struct nand_chip *this;
1499 struct mtd_info *mtd;
1500 struct mxc_nand_host *host;
1501 struct resource *res;
1502 int err = 0;
1503
1504 /* Allocate memory for MTD device structure and private data */
1505 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1506 GFP_KERNEL);
1507 if (!host)
1508 return -ENOMEM;
1509
1510 /* allocate a temporary buffer for the nand_scan_ident() */
1511 host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1512 if (!host->data_buf)
1513 return -ENOMEM;
1514
1515 host->dev = &pdev->dev;
1516 /* structures must be linked */
1517 this = &host->nand;
1518 mtd = &host->mtd;
1519 mtd->priv = this;
1520 mtd->dev.parent = &pdev->dev;
1521 mtd->name = DRIVER_NAME;
1522
1523 /* 50 us command delay time */
1524 this->chip_delay = 5;
1525
1526 this->priv = host;
1527 this->dev_ready = mxc_nand_dev_ready;
1528 this->cmdfunc = mxc_nand_command;
1529 this->read_byte = mxc_nand_read_byte;
1530 this->read_word = mxc_nand_read_word;
1531 this->write_buf = mxc_nand_write_buf;
1532 this->read_buf = mxc_nand_read_buf;
1533
1534 host->clk = devm_clk_get(&pdev->dev, NULL);
1535 if (IS_ERR(host->clk))
1536 return PTR_ERR(host->clk);
1537
1538 err = mxcnd_probe_dt(host);
1539 if (err > 0) {
1540 struct mxc_nand_platform_data *pdata =
1541 dev_get_platdata(&pdev->dev);
1542 if (pdata) {
1543 host->pdata = *pdata;
1544 host->devtype_data = (struct mxc_nand_devtype_data *)
1545 pdev->id_entry->driver_data;
1546 } else {
1547 err = -ENODEV;
1548 }
1549 }
1550 if (err < 0)
1551 return err;
1552
1553 if (host->devtype_data->needs_ip) {
1554 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1555 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1556 if (IS_ERR(host->regs_ip))
1557 return PTR_ERR(host->regs_ip);
1558
1559 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1560 } else {
1561 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1562 }
1563
1564 host->base = devm_ioremap_resource(&pdev->dev, res);
1565 if (IS_ERR(host->base))
1566 return PTR_ERR(host->base);
1567
1568 host->main_area0 = host->base;
1569
1570 if (host->devtype_data->regs_offset)
1571 host->regs = host->base + host->devtype_data->regs_offset;
1572 host->spare0 = host->base + host->devtype_data->spare0_offset;
1573 if (host->devtype_data->axi_offset)
1574 host->regs_axi = host->base + host->devtype_data->axi_offset;
1575
1576 this->ecc.bytes = host->devtype_data->eccbytes;
1577 host->eccsize = host->devtype_data->eccsize;
1578
1579 this->select_chip = host->devtype_data->select_chip;
1580 this->ecc.size = 512;
1581 this->ecc.layout = host->devtype_data->ecclayout_512;
1582
1583 if (host->pdata.hw_ecc) {
1584 this->ecc.calculate = mxc_nand_calculate_ecc;
1585 this->ecc.hwctl = mxc_nand_enable_hwecc;
1586 this->ecc.correct = host->devtype_data->correct_data;
1587 this->ecc.mode = NAND_ECC_HW;
1588 } else {
1589 this->ecc.mode = NAND_ECC_SOFT;
1590 }
1591
1592 /* NAND bus width determines access functions used by upper layer */
1593 if (host->pdata.width == 2)
1594 this->options |= NAND_BUSWIDTH_16;
1595
1596 if (host->pdata.flash_bbt) {
1597 this->bbt_td = &bbt_main_descr;
1598 this->bbt_md = &bbt_mirror_descr;
1599 /* update flash based bbt */
1600 this->bbt_options |= NAND_BBT_USE_FLASH;
1601 }
1602
1603 init_completion(&host->op_completion);
1604
1605 host->irq = platform_get_irq(pdev, 0);
1606 if (host->irq < 0)
1607 return host->irq;
1608
1609 /*
1610 * Use host->devtype_data->irq_control() here instead of irq_control()
1611 * because we must not disable_irq_nosync without having requested the
1612 * irq.
1613 */
1614 host->devtype_data->irq_control(host, 0);
1615
1616 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1617 0, DRIVER_NAME, host);
1618 if (err)
1619 return err;
1620
1621 err = clk_prepare_enable(host->clk);
1622 if (err)
1623 return err;
1624 host->clk_act = 1;
1625
1626 /*
1627 * Now that we "own" the interrupt make sure the interrupt mask bit is
1628 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1629 * on this machine.
1630 */
1631 if (host->devtype_data->irqpending_quirk) {
1632 disable_irq_nosync(host->irq);
1633 host->devtype_data->irq_control(host, 1);
1634 }
1635
1636 /* first scan to find the device and get the page size */
1637 if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) {
1638 err = -ENXIO;
1639 goto escan;
1640 }
1641
1642 /* allocate the right size buffer now */
1643 devm_kfree(&pdev->dev, (void *)host->data_buf);
1644 host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize,
1645 GFP_KERNEL);
1646 if (!host->data_buf) {
1647 err = -ENOMEM;
1648 goto escan;
1649 }
1650
1651 /* Call preset again, with correct writesize this time */
1652 host->devtype_data->preset(mtd);
1653
1654 if (mtd->writesize == 2048)
1655 this->ecc.layout = host->devtype_data->ecclayout_2k;
1656 else if (mtd->writesize == 4096) {
1657 this->ecc.layout = host->devtype_data->ecclayout_4k;
1658 if (get_eccsize(mtd) == 8)
1659 ecc_8bit_layout_4k(this->ecc.layout);
1660 }
1661
1662 /*
1663 * Experimentation shows that i.MX NFC can only handle up to 218 oob
1664 * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare()
1665 * into copying invalid data to/from the spare IO buffer, as this
1666 * might cause ECC data corruption when doing sub-page write to a
1667 * partially written page.
1668 */
1669 host->used_oobsize = min(mtd->oobsize, 218U);
1670
1671 if (this->ecc.mode == NAND_ECC_HW) {
1672 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1673 this->ecc.strength = 1;
1674 else
1675 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1676 }
1677
1678 /* second phase scan */
1679 if (nand_scan_tail(mtd)) {
1680 err = -ENXIO;
1681 goto escan;
1682 }
1683
1684 /* Register the partitions */
1685 mtd_device_parse_register(mtd, part_probes,
1686 &(struct mtd_part_parser_data){
1687 .of_node = pdev->dev.of_node,
1688 },
1689 host->pdata.parts,
1690 host->pdata.nr_parts);
1691
1692 platform_set_drvdata(pdev, host);
1693
1694 return 0;
1695
1696 escan:
1697 if (host->clk_act)
1698 clk_disable_unprepare(host->clk);
1699
1700 return err;
1701 }
1702
mxcnd_remove(struct platform_device * pdev)1703 static int mxcnd_remove(struct platform_device *pdev)
1704 {
1705 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1706
1707 nand_release(&host->mtd);
1708 if (host->clk_act)
1709 clk_disable_unprepare(host->clk);
1710
1711 return 0;
1712 }
1713
1714 static struct platform_driver mxcnd_driver = {
1715 .driver = {
1716 .name = DRIVER_NAME,
1717 .of_match_table = of_match_ptr(mxcnd_dt_ids),
1718 },
1719 .id_table = mxcnd_devtype,
1720 .probe = mxcnd_probe,
1721 .remove = mxcnd_remove,
1722 };
1723 module_platform_driver(mxcnd_driver);
1724
1725 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1726 MODULE_DESCRIPTION("MXC NAND MTD driver");
1727 MODULE_LICENSE("GPL");
1728