1/* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 *	http://armlinux.simtec.co.uk/
6 *	Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C Platform - SDHCI (HSMMC) register definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C_SDHCI_REGS_H
16#define __PLAT_S3C_SDHCI_REGS_H __FILE__
17
18#define S3C_SDHCI_CONTROL2			(0x80)
19#define S3C_SDHCI_CONTROL3			(0x84)
20#define S3C64XX_SDHCI_CONTROL4			(0x8C)
21
22#define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR	(1 << 31)
23#define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK		(1 << 30)
24#define S3C_SDHCI_CTRL2_CDINVRXD3		(1 << 29)
25#define S3C_SDHCI_CTRL2_SLCARDOUT		(1 << 28)
26
27#define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK		(0xf << 24)
28#define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT		(24)
29#define S3C_SDHCI_CTRL2_FLTCLKSEL(_x)		((_x) << 24)
30
31#define S3C_SDHCI_CTRL2_LVLDAT_MASK		(0xff << 16)
32#define S3C_SDHCI_CTRL2_LVLDAT_SHIFT		(16)
33#define S3C_SDHCI_CTRL2_LVLDAT(_x)		((_x) << 16)
34
35#define S3C_SDHCI_CTRL2_ENFBCLKTX		(1 << 15)
36#define S3C_SDHCI_CTRL2_ENFBCLKRX		(1 << 14)
37#define S3C_SDHCI_CTRL2_SDCDSEL			(1 << 13)
38#define S3C_SDHCI_CTRL2_SDSIGPC			(1 << 12)
39#define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART	(1 << 11)
40
41#define S3C_SDHCI_CTRL2_DFCNT_MASK		(0x3 << 9)
42#define S3C_SDHCI_CTRL2_DFCNT_SHIFT		(9)
43#define S3C_SDHCI_CTRL2_DFCNT_NONE		(0x0 << 9)
44#define S3C_SDHCI_CTRL2_DFCNT_4SDCLK		(0x1 << 9)
45#define S3C_SDHCI_CTRL2_DFCNT_16SDCLK		(0x2 << 9)
46#define S3C_SDHCI_CTRL2_DFCNT_64SDCLK		(0x3 << 9)
47
48#define S3C_SDHCI_CTRL2_ENCLKOUTHOLD		(1 << 8)
49#define S3C_SDHCI_CTRL2_RWAITMODE		(1 << 7)
50#define S3C_SDHCI_CTRL2_DISBUFRD		(1 << 6)
51#define S3C_SDHCI_CTRL2_SELBASECLK_MASK		(0x3 << 4)
52#define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT	(4)
53#define S3C_SDHCI_CTRL2_PWRSYNC			(1 << 3)
54#define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON		(1 << 1)
55#define S3C_SDHCI_CTRL2_HWINITFIN		(1 << 0)
56
57#define S3C_SDHCI_CTRL3_FCSEL3			(1 << 31)
58#define S3C_SDHCI_CTRL3_FCSEL2			(1 << 23)
59#define S3C_SDHCI_CTRL3_FCSEL1			(1 << 15)
60#define S3C_SDHCI_CTRL3_FCSEL0			(1 << 7)
61
62#define S3C_SDHCI_CTRL3_FIA3_MASK		(0x7f << 24)
63#define S3C_SDHCI_CTRL3_FIA3_SHIFT		(24)
64#define S3C_SDHCI_CTRL3_FIA3(_x)		((_x) << 24)
65
66#define S3C_SDHCI_CTRL3_FIA2_MASK		(0x7f << 16)
67#define S3C_SDHCI_CTRL3_FIA2_SHIFT		(16)
68#define S3C_SDHCI_CTRL3_FIA2(_x)		((_x) << 16)
69
70#define S3C_SDHCI_CTRL3_FIA1_MASK		(0x7f << 8)
71#define S3C_SDHCI_CTRL3_FIA1_SHIFT		(8)
72#define S3C_SDHCI_CTRL3_FIA1(_x)		((_x) << 8)
73
74#define S3C_SDHCI_CTRL3_FIA0_MASK		(0x7f << 0)
75#define S3C_SDHCI_CTRL3_FIA0_SHIFT		(0)
76#define S3C_SDHCI_CTRL3_FIA0(_x)		((_x) << 0)
77
78#define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK	(0x3 << 16)
79#define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT	(16)
80#define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA	(0x0 << 16)
81#define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA	(0x1 << 16)
82#define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA	(0x2 << 16)
83#define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA	(0x3 << 16)
84
85#define S3C64XX_SDHCI_CONTROL4_BUSY		(1)
86
87#endif /* __PLAT_S3C_SDHCI_REGS_H */
88