1/*
2 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#define pr_fmt(fmt) "%s: " fmt, __func__
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/irqchip/chained_irq.h>
19#include <linux/irq.h>
20#include <linux/irqdomain.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include <linux/err.h>
25#include <linux/ssbi.h>
26#include <linux/regmap.h>
27#include <linux/of_platform.h>
28#include <linux/mfd/core.h>
29
30#define	SSBI_REG_ADDR_IRQ_BASE		0x1BB
31
32#define	SSBI_REG_ADDR_IRQ_ROOT		(SSBI_REG_ADDR_IRQ_BASE + 0)
33#define	SSBI_REG_ADDR_IRQ_M_STATUS1	(SSBI_REG_ADDR_IRQ_BASE + 1)
34#define	SSBI_REG_ADDR_IRQ_M_STATUS2	(SSBI_REG_ADDR_IRQ_BASE + 2)
35#define	SSBI_REG_ADDR_IRQ_M_STATUS3	(SSBI_REG_ADDR_IRQ_BASE + 3)
36#define	SSBI_REG_ADDR_IRQ_M_STATUS4	(SSBI_REG_ADDR_IRQ_BASE + 4)
37#define	SSBI_REG_ADDR_IRQ_BLK_SEL	(SSBI_REG_ADDR_IRQ_BASE + 5)
38#define	SSBI_REG_ADDR_IRQ_IT_STATUS	(SSBI_REG_ADDR_IRQ_BASE + 6)
39#define	SSBI_REG_ADDR_IRQ_CONFIG	(SSBI_REG_ADDR_IRQ_BASE + 7)
40#define	SSBI_REG_ADDR_IRQ_RT_STATUS	(SSBI_REG_ADDR_IRQ_BASE + 8)
41
42#define	PM_IRQF_LVL_SEL			0x01	/* level select */
43#define	PM_IRQF_MASK_FE			0x02	/* mask falling edge */
44#define	PM_IRQF_MASK_RE			0x04	/* mask rising edge */
45#define	PM_IRQF_CLR			0x08	/* clear interrupt */
46#define	PM_IRQF_BITS_MASK		0x70
47#define	PM_IRQF_BITS_SHIFT		4
48#define	PM_IRQF_WRITE			0x80
49
50#define	PM_IRQF_MASK_ALL		(PM_IRQF_MASK_FE | \
51					PM_IRQF_MASK_RE)
52
53#define REG_HWREV		0x002  /* PMIC4 revision */
54#define REG_HWREV_2		0x0E8  /* PMIC4 revision 2 */
55
56#define PM8921_NR_IRQS		256
57
58struct pm_irq_chip {
59	struct regmap		*regmap;
60	spinlock_t		pm_irq_lock;
61	struct irq_domain	*irqdomain;
62	unsigned int		num_irqs;
63	unsigned int		num_blocks;
64	unsigned int		num_masters;
65	u8			config[0];
66};
67
68static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
69				 unsigned int *ip)
70{
71	int	rc;
72
73	spin_lock(&chip->pm_irq_lock);
74	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
75	if (rc) {
76		pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
77		goto bail;
78	}
79
80	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
81	if (rc)
82		pr_err("Failed Reading Status rc=%d\n", rc);
83bail:
84	spin_unlock(&chip->pm_irq_lock);
85	return rc;
86}
87
88static int
89pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
90{
91	int	rc;
92
93	spin_lock(&chip->pm_irq_lock);
94	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
95	if (rc) {
96		pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
97		goto bail;
98	}
99
100	cp |= PM_IRQF_WRITE;
101	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
102	if (rc)
103		pr_err("Failed Configuring IRQ rc=%d\n", rc);
104bail:
105	spin_unlock(&chip->pm_irq_lock);
106	return rc;
107}
108
109static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
110{
111	int pmirq, irq, i, ret = 0;
112	unsigned int bits;
113
114	ret = pm8xxx_read_block_irq(chip, block, &bits);
115	if (ret) {
116		pr_err("Failed reading %d block ret=%d", block, ret);
117		return ret;
118	}
119	if (!bits) {
120		pr_err("block bit set in master but no irqs: %d", block);
121		return 0;
122	}
123
124	/* Check IRQ bits */
125	for (i = 0; i < 8; i++) {
126		if (bits & (1 << i)) {
127			pmirq = block * 8 + i;
128			irq = irq_find_mapping(chip->irqdomain, pmirq);
129			generic_handle_irq(irq);
130		}
131	}
132	return 0;
133}
134
135static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
136{
137	unsigned int blockbits;
138	int block_number, i, ret = 0;
139
140	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
141			  &blockbits);
142	if (ret) {
143		pr_err("Failed to read master %d ret=%d\n", master, ret);
144		return ret;
145	}
146	if (!blockbits) {
147		pr_err("master bit set in root but no blocks: %d", master);
148		return 0;
149	}
150
151	for (i = 0; i < 8; i++)
152		if (blockbits & (1 << i)) {
153			block_number = master * 8 + i;	/* block # */
154			ret |= pm8xxx_irq_block_handler(chip, block_number);
155		}
156	return ret;
157}
158
159static void pm8xxx_irq_handler(struct irq_desc *desc)
160{
161	struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
162	struct irq_chip *irq_chip = irq_desc_get_chip(desc);
163	unsigned int root;
164	int	i, ret, masters = 0;
165
166	chained_irq_enter(irq_chip, desc);
167
168	ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
169	if (ret) {
170		pr_err("Can't read root status ret=%d\n", ret);
171		return;
172	}
173
174	/* on pm8xxx series masters start from bit 1 of the root */
175	masters = root >> 1;
176
177	/* Read allowed masters for blocks. */
178	for (i = 0; i < chip->num_masters; i++)
179		if (masters & (1 << i))
180			pm8xxx_irq_master_handler(chip, i);
181
182	chained_irq_exit(irq_chip, desc);
183}
184
185static void pm8xxx_irq_mask_ack(struct irq_data *d)
186{
187	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
188	unsigned int pmirq = irqd_to_hwirq(d);
189	u8	block, config;
190
191	block = pmirq / 8;
192
193	config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
194	pm8xxx_config_irq(chip, block, config);
195}
196
197static void pm8xxx_irq_unmask(struct irq_data *d)
198{
199	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
200	unsigned int pmirq = irqd_to_hwirq(d);
201	u8	block, config;
202
203	block = pmirq / 8;
204
205	config = chip->config[pmirq];
206	pm8xxx_config_irq(chip, block, config);
207}
208
209static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
210{
211	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
212	unsigned int pmirq = irqd_to_hwirq(d);
213	int irq_bit;
214	u8 block, config;
215
216	block = pmirq / 8;
217	irq_bit  = pmirq % 8;
218
219	chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
220							| PM_IRQF_MASK_ALL;
221	if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
222		if (flow_type & IRQF_TRIGGER_RISING)
223			chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
224		if (flow_type & IRQF_TRIGGER_FALLING)
225			chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
226	} else {
227		chip->config[pmirq] |= PM_IRQF_LVL_SEL;
228
229		if (flow_type & IRQF_TRIGGER_HIGH)
230			chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
231		else
232			chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
233	}
234
235	config = chip->config[pmirq] | PM_IRQF_CLR;
236	return pm8xxx_config_irq(chip, block, config);
237}
238
239static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
240					enum irqchip_irq_state which,
241					bool *state)
242{
243	struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
244	unsigned int pmirq = irqd_to_hwirq(d);
245	unsigned int bits;
246	int irq_bit;
247	u8 block;
248	int rc;
249
250	if (which != IRQCHIP_STATE_LINE_LEVEL)
251		return -EINVAL;
252
253	block = pmirq / 8;
254	irq_bit = pmirq % 8;
255
256	spin_lock(&chip->pm_irq_lock);
257	rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
258	if (rc) {
259		pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
260		goto bail;
261	}
262
263	rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
264	if (rc) {
265		pr_err("Failed Reading Status rc=%d\n", rc);
266		goto bail;
267	}
268
269	*state = !!(bits & BIT(irq_bit));
270bail:
271	spin_unlock(&chip->pm_irq_lock);
272
273	return rc;
274}
275
276static struct irq_chip pm8xxx_irq_chip = {
277	.name		= "pm8xxx",
278	.irq_mask_ack	= pm8xxx_irq_mask_ack,
279	.irq_unmask	= pm8xxx_irq_unmask,
280	.irq_set_type	= pm8xxx_irq_set_type,
281	.irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
282	.flags		= IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
283};
284
285static int pm8xxx_irq_domain_map(struct irq_domain *d, unsigned int irq,
286				   irq_hw_number_t hwirq)
287{
288	struct pm_irq_chip *chip = d->host_data;
289
290	irq_set_chip_and_handler(irq, &pm8xxx_irq_chip, handle_level_irq);
291	irq_set_chip_data(irq, chip);
292	irq_set_noprobe(irq);
293
294	return 0;
295}
296
297static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
298	.xlate = irq_domain_xlate_twocell,
299	.map = pm8xxx_irq_domain_map,
300};
301
302static const struct regmap_config ssbi_regmap_config = {
303	.reg_bits = 16,
304	.val_bits = 8,
305	.max_register = 0x3ff,
306	.fast_io = true,
307	.reg_read = ssbi_reg_read,
308	.reg_write = ssbi_reg_write
309};
310
311static const struct of_device_id pm8921_id_table[] = {
312	{ .compatible = "qcom,pm8058", },
313	{ .compatible = "qcom,pm8921", },
314	{ }
315};
316MODULE_DEVICE_TABLE(of, pm8921_id_table);
317
318static int pm8921_probe(struct platform_device *pdev)
319{
320	struct regmap *regmap;
321	int irq, rc;
322	unsigned int val;
323	u32 rev;
324	struct pm_irq_chip *chip;
325	unsigned int nirqs = PM8921_NR_IRQS;
326
327	irq = platform_get_irq(pdev, 0);
328	if (irq < 0)
329		return irq;
330
331	regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
332				  &ssbi_regmap_config);
333	if (IS_ERR(regmap))
334		return PTR_ERR(regmap);
335
336	/* Read PMIC chip revision */
337	rc = regmap_read(regmap, REG_HWREV, &val);
338	if (rc) {
339		pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
340		return rc;
341	}
342	pr_info("PMIC revision 1: %02X\n", val);
343	rev = val;
344
345	/* Read PMIC chip revision 2 */
346	rc = regmap_read(regmap, REG_HWREV_2, &val);
347	if (rc) {
348		pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
349			REG_HWREV_2, rc);
350		return rc;
351	}
352	pr_info("PMIC revision 2: %02X\n", val);
353	rev |= val << BITS_PER_BYTE;
354
355	chip = devm_kzalloc(&pdev->dev, sizeof(*chip) +
356					sizeof(chip->config[0]) * nirqs,
357					GFP_KERNEL);
358	if (!chip)
359		return -ENOMEM;
360
361	platform_set_drvdata(pdev, chip);
362	chip->regmap = regmap;
363	chip->num_irqs = nirqs;
364	chip->num_blocks = DIV_ROUND_UP(chip->num_irqs, 8);
365	chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
366	spin_lock_init(&chip->pm_irq_lock);
367
368	chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node, nirqs,
369						&pm8xxx_irq_domain_ops,
370						chip);
371	if (!chip->irqdomain)
372		return -ENODEV;
373
374	irq_set_chained_handler_and_data(irq, pm8xxx_irq_handler, chip);
375	irq_set_irq_wake(irq, 1);
376
377	rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
378	if (rc) {
379		irq_set_chained_handler_and_data(irq, NULL, NULL);
380		irq_domain_remove(chip->irqdomain);
381	}
382
383	return rc;
384}
385
386static int pm8921_remove_child(struct device *dev, void *unused)
387{
388	platform_device_unregister(to_platform_device(dev));
389	return 0;
390}
391
392static int pm8921_remove(struct platform_device *pdev)
393{
394	int irq = platform_get_irq(pdev, 0);
395	struct pm_irq_chip *chip = platform_get_drvdata(pdev);
396
397	device_for_each_child(&pdev->dev, NULL, pm8921_remove_child);
398	irq_set_chained_handler_and_data(irq, NULL, NULL);
399	irq_domain_remove(chip->irqdomain);
400
401	return 0;
402}
403
404static struct platform_driver pm8921_driver = {
405	.probe		= pm8921_probe,
406	.remove		= pm8921_remove,
407	.driver		= {
408		.name	= "pm8921-core",
409		.of_match_table = pm8921_id_table,
410	},
411};
412
413static int __init pm8921_init(void)
414{
415	return platform_driver_register(&pm8921_driver);
416}
417subsys_initcall(pm8921_init);
418
419static void __exit pm8921_exit(void)
420{
421	platform_driver_unregister(&pm8921_driver);
422}
423module_exit(pm8921_exit);
424
425MODULE_LICENSE("GPL v2");
426MODULE_DESCRIPTION("PMIC 8921 core driver");
427MODULE_VERSION("1.0");
428MODULE_ALIAS("platform:pm8921-core");
429