1/*
2 * Copyright 2010 Broadcom
3 * Copyright 2012 Simon Arlott, Chris Boot, Stephen Warren
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 *
15 * Quirk 1: Shortcut interrupts don't set the bank 1/2 register pending bits
16 *
17 * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
18 * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
19 * to look in the bank 1 status register for more information.
20 *
21 * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
22 * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
23 * status register, but bank 0 bit 8 is _not_ set.
24 *
25 * Quirk 2: You can't mask the register 1/2 pending interrupts
26 *
27 * In a proper cascaded interrupt controller, the interrupt lines with
28 * cascaded interrupt controllers on them are just normal interrupt lines.
29 * You can mask the interrupts and get on with things. With this controller
30 * you can't do that.
31 *
32 * Quirk 3: The shortcut interrupts can't be (un)masked in bank 0
33 *
34 * Those interrupts that have shortcuts can only be masked/unmasked in
35 * their respective banks' enable/disable registers. Doing so in the bank 0
36 * enable/disable registers has no effect.
37 *
38 * The FIQ control register:
39 *  Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
40 *  Bit    7: Enable FIQ generation
41 *  Bits  8+: Unused
42 *
43 * An interrupt must be disabled before configuring it for FIQ generation
44 * otherwise both handlers will fire at the same time!
45 */
46
47#include <linux/io.h>
48#include <linux/slab.h>
49#include <linux/of_address.h>
50#include <linux/of_irq.h>
51#include <linux/irqchip.h>
52#include <linux/irqdomain.h>
53
54#include <asm/exception.h>
55#include <asm/mach/irq.h>
56
57/* Put the bank and irq (32 bits) into the hwirq */
58#define MAKE_HWIRQ(b, n)	((b << 5) | (n))
59#define HWIRQ_BANK(i)		(i >> 5)
60#define HWIRQ_BIT(i)		BIT(i & 0x1f)
61
62#define NR_IRQS_BANK0		8
63#define BANK0_HWIRQ_MASK	0xff
64/* Shortcuts can't be disabled so any unknown new ones need to be masked */
65#define SHORTCUT1_MASK		0x00007c00
66#define SHORTCUT2_MASK		0x001f8000
67#define SHORTCUT_SHIFT		10
68#define BANK1_HWIRQ		BIT(8)
69#define BANK2_HWIRQ		BIT(9)
70#define BANK0_VALID_MASK	(BANK0_HWIRQ_MASK | BANK1_HWIRQ | BANK2_HWIRQ \
71					| SHORTCUT1_MASK | SHORTCUT2_MASK)
72
73#define REG_FIQ_CONTROL		0x0c
74
75#define NR_BANKS		3
76#define IRQS_PER_BANK		32
77
78static const int reg_pending[] __initconst = { 0x00, 0x04, 0x08 };
79static const int reg_enable[] __initconst = { 0x18, 0x10, 0x14 };
80static const int reg_disable[] __initconst = { 0x24, 0x1c, 0x20 };
81static const int bank_irqs[] __initconst = { 8, 32, 32 };
82
83static const int shortcuts[] = {
84	7, 9, 10, 18, 19,		/* Bank 1 */
85	21, 22, 23, 24, 25, 30		/* Bank 2 */
86};
87
88struct armctrl_ic {
89	void __iomem *base;
90	void __iomem *pending[NR_BANKS];
91	void __iomem *enable[NR_BANKS];
92	void __iomem *disable[NR_BANKS];
93	struct irq_domain *domain;
94};
95
96static struct armctrl_ic intc __read_mostly;
97static void __exception_irq_entry bcm2835_handle_irq(
98	struct pt_regs *regs);
99static void bcm2836_chained_handle_irq(struct irq_desc *desc);
100
101static void armctrl_mask_irq(struct irq_data *d)
102{
103	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);
104}
105
106static void armctrl_unmask_irq(struct irq_data *d)
107{
108	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);
109}
110
111static struct irq_chip armctrl_chip = {
112	.name = "ARMCTRL-level",
113	.irq_mask = armctrl_mask_irq,
114	.irq_unmask = armctrl_unmask_irq
115};
116
117static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
118	const u32 *intspec, unsigned int intsize,
119	unsigned long *out_hwirq, unsigned int *out_type)
120{
121	if (WARN_ON(intsize != 2))
122		return -EINVAL;
123
124	if (WARN_ON(intspec[0] >= NR_BANKS))
125		return -EINVAL;
126
127	if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
128		return -EINVAL;
129
130	if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
131		return -EINVAL;
132
133	*out_hwirq = MAKE_HWIRQ(intspec[0], intspec[1]);
134	*out_type = IRQ_TYPE_NONE;
135	return 0;
136}
137
138static const struct irq_domain_ops armctrl_ops = {
139	.xlate = armctrl_xlate
140};
141
142static int __init armctrl_of_init(struct device_node *node,
143				  struct device_node *parent,
144				  bool is_2836)
145{
146	void __iomem *base;
147	int irq, b, i;
148
149	base = of_iomap(node, 0);
150	if (!base)
151		panic("%s: unable to map IC registers\n",
152			node->full_name);
153
154	intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0),
155			&armctrl_ops, NULL);
156	if (!intc.domain)
157		panic("%s: unable to create IRQ domain\n", node->full_name);
158
159	for (b = 0; b < NR_BANKS; b++) {
160		intc.pending[b] = base + reg_pending[b];
161		intc.enable[b] = base + reg_enable[b];
162		intc.disable[b] = base + reg_disable[b];
163
164		for (i = 0; i < bank_irqs[b]; i++) {
165			irq = irq_create_mapping(intc.domain, MAKE_HWIRQ(b, i));
166			BUG_ON(irq <= 0);
167			irq_set_chip_and_handler(irq, &armctrl_chip,
168				handle_level_irq);
169			irq_set_probe(irq);
170		}
171	}
172
173	if (is_2836) {
174		int parent_irq = irq_of_parse_and_map(node, 0);
175
176		if (!parent_irq) {
177			panic("%s: unable to get parent interrupt.\n",
178			      node->full_name);
179		}
180		irq_set_chained_handler(parent_irq, bcm2836_chained_handle_irq);
181	} else {
182		set_handle_irq(bcm2835_handle_irq);
183	}
184
185	return 0;
186}
187
188static int __init bcm2835_armctrl_of_init(struct device_node *node,
189					  struct device_node *parent)
190{
191	return armctrl_of_init(node, parent, false);
192}
193
194static int __init bcm2836_armctrl_of_init(struct device_node *node,
195					  struct device_node *parent)
196{
197	return armctrl_of_init(node, parent, true);
198}
199
200
201/*
202 * Handle each interrupt across the entire interrupt controller.  This reads the
203 * status register before handling each interrupt, which is necessary given that
204 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
205 */
206
207static u32 armctrl_translate_bank(int bank)
208{
209	u32 stat = readl_relaxed(intc.pending[bank]);
210
211	return MAKE_HWIRQ(bank, ffs(stat) - 1);
212}
213
214static u32 armctrl_translate_shortcut(int bank, u32 stat)
215{
216	return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);
217}
218
219static u32 get_next_armctrl_hwirq(void)
220{
221	u32 stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK;
222
223	if (stat == 0)
224		return ~0;
225	else if (stat & BANK0_HWIRQ_MASK)
226		return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);
227	else if (stat & SHORTCUT1_MASK)
228		return armctrl_translate_shortcut(1, stat & SHORTCUT1_MASK);
229	else if (stat & SHORTCUT2_MASK)
230		return armctrl_translate_shortcut(2, stat & SHORTCUT2_MASK);
231	else if (stat & BANK1_HWIRQ)
232		return armctrl_translate_bank(1);
233	else if (stat & BANK2_HWIRQ)
234		return armctrl_translate_bank(2);
235	else
236		BUG();
237}
238
239static void __exception_irq_entry bcm2835_handle_irq(
240	struct pt_regs *regs)
241{
242	u32 hwirq;
243
244	while ((hwirq = get_next_armctrl_hwirq()) != ~0)
245		handle_IRQ(irq_linear_revmap(intc.domain, hwirq), regs);
246}
247
248static void bcm2836_chained_handle_irq(struct irq_desc *desc)
249{
250	u32 hwirq;
251
252	while ((hwirq = get_next_armctrl_hwirq()) != ~0)
253		generic_handle_irq(irq_linear_revmap(intc.domain, hwirq));
254}
255
256IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
257		bcm2835_armctrl_of_init);
258IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",
259		bcm2836_armctrl_of_init);
260