1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <linux/dma-contiguous.h>
37 #include <linux/irqdomain.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/io_apic.h>
40 #include <asm/apic.h>
41 #include <asm/hw_irq.h>
42 #include <asm/msidef.h>
43 #include <asm/proto.h>
44 #include <asm/iommu.h>
45 #include <asm/gart.h>
46 #include <asm/dma.h>
47
48 #include "amd_iommu_proto.h"
49 #include "amd_iommu_types.h"
50 #include "irq_remapping.h"
51
52 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
53
54 #define LOOP_TIMEOUT 100000
55
56 /*
57 * This bitmap is used to advertise the page sizes our hardware support
58 * to the IOMMU core, which will then use this information to split
59 * physically contiguous memory regions it is mapping into page sizes
60 * that we support.
61 *
62 * 512GB Pages are not supported due to a hardware bug
63 */
64 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
65
66 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
67
68 /* List of all available dev_data structures */
69 static LIST_HEAD(dev_data_list);
70 static DEFINE_SPINLOCK(dev_data_list_lock);
71
72 LIST_HEAD(ioapic_map);
73 LIST_HEAD(hpet_map);
74
75 /*
76 * Domain for untranslated devices - only allocated
77 * if iommu=pt passed on kernel cmd line.
78 */
79 static const struct iommu_ops amd_iommu_ops;
80
81 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
82 int amd_iommu_max_glx_val = -1;
83
84 static struct dma_map_ops amd_iommu_dma_ops;
85
86 /*
87 * This struct contains device specific data for the IOMMU
88 */
89 struct iommu_dev_data {
90 struct list_head list; /* For domain->dev_list */
91 struct list_head dev_data_list; /* For global dev_data_list */
92 struct protection_domain *domain; /* Domain the device is bound to */
93 u16 devid; /* PCI Device ID */
94 u16 alias; /* Alias Device ID */
95 bool iommu_v2; /* Device can make use of IOMMUv2 */
96 bool passthrough; /* Device is identity mapped */
97 struct {
98 bool enabled;
99 int qdep;
100 } ats; /* ATS state */
101 bool pri_tlp; /* PASID TLB required for
102 PPR completions */
103 u32 errata; /* Bitmap for errata to apply */
104 };
105
106 /*
107 * general struct to manage commands send to an IOMMU
108 */
109 struct iommu_cmd {
110 u32 data[4];
111 };
112
113 struct kmem_cache *amd_iommu_irq_cache;
114
115 static void update_domain(struct protection_domain *domain);
116 static int protection_domain_init(struct protection_domain *domain);
117
118 /****************************************************************************
119 *
120 * Helper functions
121 *
122 ****************************************************************************/
123
to_pdomain(struct iommu_domain * dom)124 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
125 {
126 return container_of(dom, struct protection_domain, domain);
127 }
128
get_device_id(struct device * dev)129 static inline u16 get_device_id(struct device *dev)
130 {
131 struct pci_dev *pdev = to_pci_dev(dev);
132
133 return PCI_DEVID(pdev->bus->number, pdev->devfn);
134 }
135
alloc_dev_data(u16 devid)136 static struct iommu_dev_data *alloc_dev_data(u16 devid)
137 {
138 struct iommu_dev_data *dev_data;
139 unsigned long flags;
140
141 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
142 if (!dev_data)
143 return NULL;
144
145 dev_data->devid = devid;
146
147 spin_lock_irqsave(&dev_data_list_lock, flags);
148 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
149 spin_unlock_irqrestore(&dev_data_list_lock, flags);
150
151 return dev_data;
152 }
153
search_dev_data(u16 devid)154 static struct iommu_dev_data *search_dev_data(u16 devid)
155 {
156 struct iommu_dev_data *dev_data;
157 unsigned long flags;
158
159 spin_lock_irqsave(&dev_data_list_lock, flags);
160 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
161 if (dev_data->devid == devid)
162 goto out_unlock;
163 }
164
165 dev_data = NULL;
166
167 out_unlock:
168 spin_unlock_irqrestore(&dev_data_list_lock, flags);
169
170 return dev_data;
171 }
172
__last_alias(struct pci_dev * pdev,u16 alias,void * data)173 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
174 {
175 *(u16 *)data = alias;
176 return 0;
177 }
178
get_alias(struct device * dev)179 static u16 get_alias(struct device *dev)
180 {
181 struct pci_dev *pdev = to_pci_dev(dev);
182 u16 devid, ivrs_alias, pci_alias;
183
184 devid = get_device_id(dev);
185 ivrs_alias = amd_iommu_alias_table[devid];
186 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
187
188 if (ivrs_alias == pci_alias)
189 return ivrs_alias;
190
191 /*
192 * DMA alias showdown
193 *
194 * The IVRS is fairly reliable in telling us about aliases, but it
195 * can't know about every screwy device. If we don't have an IVRS
196 * reported alias, use the PCI reported alias. In that case we may
197 * still need to initialize the rlookup and dev_table entries if the
198 * alias is to a non-existent device.
199 */
200 if (ivrs_alias == devid) {
201 if (!amd_iommu_rlookup_table[pci_alias]) {
202 amd_iommu_rlookup_table[pci_alias] =
203 amd_iommu_rlookup_table[devid];
204 memcpy(amd_iommu_dev_table[pci_alias].data,
205 amd_iommu_dev_table[devid].data,
206 sizeof(amd_iommu_dev_table[pci_alias].data));
207 }
208
209 return pci_alias;
210 }
211
212 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
213 "for device %s[%04x:%04x], kernel reported alias "
214 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
215 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
216 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
217 PCI_FUNC(pci_alias));
218
219 /*
220 * If we don't have a PCI DMA alias and the IVRS alias is on the same
221 * bus, then the IVRS table may know about a quirk that we don't.
222 */
223 if (pci_alias == devid &&
224 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
225 pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
226 pdev->dma_alias_devfn = ivrs_alias & 0xff;
227 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
228 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
229 dev_name(dev));
230 }
231
232 return ivrs_alias;
233 }
234
find_dev_data(u16 devid)235 static struct iommu_dev_data *find_dev_data(u16 devid)
236 {
237 struct iommu_dev_data *dev_data;
238
239 dev_data = search_dev_data(devid);
240
241 if (dev_data == NULL)
242 dev_data = alloc_dev_data(devid);
243
244 return dev_data;
245 }
246
get_dev_data(struct device * dev)247 static struct iommu_dev_data *get_dev_data(struct device *dev)
248 {
249 return dev->archdata.iommu;
250 }
251
pci_iommuv2_capable(struct pci_dev * pdev)252 static bool pci_iommuv2_capable(struct pci_dev *pdev)
253 {
254 static const int caps[] = {
255 PCI_EXT_CAP_ID_ATS,
256 PCI_EXT_CAP_ID_PRI,
257 PCI_EXT_CAP_ID_PASID,
258 };
259 int i, pos;
260
261 for (i = 0; i < 3; ++i) {
262 pos = pci_find_ext_capability(pdev, caps[i]);
263 if (pos == 0)
264 return false;
265 }
266
267 return true;
268 }
269
pdev_pri_erratum(struct pci_dev * pdev,u32 erratum)270 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
271 {
272 struct iommu_dev_data *dev_data;
273
274 dev_data = get_dev_data(&pdev->dev);
275
276 return dev_data->errata & (1 << erratum) ? true : false;
277 }
278
279 /*
280 * This function actually applies the mapping to the page table of the
281 * dma_ops domain.
282 */
alloc_unity_mapping(struct dma_ops_domain * dma_dom,struct unity_map_entry * e)283 static void alloc_unity_mapping(struct dma_ops_domain *dma_dom,
284 struct unity_map_entry *e)
285 {
286 u64 addr;
287
288 for (addr = e->address_start; addr < e->address_end;
289 addr += PAGE_SIZE) {
290 if (addr < dma_dom->aperture_size)
291 __set_bit(addr >> PAGE_SHIFT,
292 dma_dom->aperture[0]->bitmap);
293 }
294 }
295
296 /*
297 * Inits the unity mappings required for a specific device
298 */
init_unity_mappings_for_device(struct device * dev,struct dma_ops_domain * dma_dom)299 static void init_unity_mappings_for_device(struct device *dev,
300 struct dma_ops_domain *dma_dom)
301 {
302 struct unity_map_entry *e;
303 u16 devid;
304
305 devid = get_device_id(dev);
306
307 list_for_each_entry(e, &amd_iommu_unity_map, list) {
308 if (!(devid >= e->devid_start && devid <= e->devid_end))
309 continue;
310 alloc_unity_mapping(dma_dom, e);
311 }
312 }
313
314 /*
315 * This function checks if the driver got a valid device from the caller to
316 * avoid dereferencing invalid pointers.
317 */
check_device(struct device * dev)318 static bool check_device(struct device *dev)
319 {
320 u16 devid;
321
322 if (!dev || !dev->dma_mask)
323 return false;
324
325 /* No PCI device */
326 if (!dev_is_pci(dev))
327 return false;
328
329 devid = get_device_id(dev);
330
331 /* Out of our scope? */
332 if (devid > amd_iommu_last_bdf)
333 return false;
334
335 if (amd_iommu_rlookup_table[devid] == NULL)
336 return false;
337
338 return true;
339 }
340
init_iommu_group(struct device * dev)341 static void init_iommu_group(struct device *dev)
342 {
343 struct dma_ops_domain *dma_domain;
344 struct iommu_domain *domain;
345 struct iommu_group *group;
346
347 group = iommu_group_get_for_dev(dev);
348 if (IS_ERR(group))
349 return;
350
351 domain = iommu_group_default_domain(group);
352 if (!domain)
353 goto out;
354
355 dma_domain = to_pdomain(domain)->priv;
356
357 init_unity_mappings_for_device(dev, dma_domain);
358 out:
359 iommu_group_put(group);
360 }
361
iommu_init_device(struct device * dev)362 static int iommu_init_device(struct device *dev)
363 {
364 struct pci_dev *pdev = to_pci_dev(dev);
365 struct iommu_dev_data *dev_data;
366
367 if (dev->archdata.iommu)
368 return 0;
369
370 dev_data = find_dev_data(get_device_id(dev));
371 if (!dev_data)
372 return -ENOMEM;
373
374 dev_data->alias = get_alias(dev);
375
376 if (pci_iommuv2_capable(pdev)) {
377 struct amd_iommu *iommu;
378
379 iommu = amd_iommu_rlookup_table[dev_data->devid];
380 dev_data->iommu_v2 = iommu->is_iommu_v2;
381 }
382
383 dev->archdata.iommu = dev_data;
384
385 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
386 dev);
387
388 return 0;
389 }
390
iommu_ignore_device(struct device * dev)391 static void iommu_ignore_device(struct device *dev)
392 {
393 u16 devid, alias;
394
395 devid = get_device_id(dev);
396 alias = get_alias(dev);
397
398 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
399 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
400
401 amd_iommu_rlookup_table[devid] = NULL;
402 amd_iommu_rlookup_table[alias] = NULL;
403 }
404
iommu_uninit_device(struct device * dev)405 static void iommu_uninit_device(struct device *dev)
406 {
407 struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev));
408
409 if (!dev_data)
410 return;
411
412 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
413 dev);
414
415 iommu_group_remove_device(dev);
416
417 /* Remove dma-ops */
418 dev->archdata.dma_ops = NULL;
419
420 /*
421 * We keep dev_data around for unplugged devices and reuse it when the
422 * device is re-plugged - not doing so would introduce a ton of races.
423 */
424 }
425
426 #ifdef CONFIG_AMD_IOMMU_STATS
427
428 /*
429 * Initialization code for statistics collection
430 */
431
432 DECLARE_STATS_COUNTER(compl_wait);
433 DECLARE_STATS_COUNTER(cnt_map_single);
434 DECLARE_STATS_COUNTER(cnt_unmap_single);
435 DECLARE_STATS_COUNTER(cnt_map_sg);
436 DECLARE_STATS_COUNTER(cnt_unmap_sg);
437 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
438 DECLARE_STATS_COUNTER(cnt_free_coherent);
439 DECLARE_STATS_COUNTER(cross_page);
440 DECLARE_STATS_COUNTER(domain_flush_single);
441 DECLARE_STATS_COUNTER(domain_flush_all);
442 DECLARE_STATS_COUNTER(alloced_io_mem);
443 DECLARE_STATS_COUNTER(total_map_requests);
444 DECLARE_STATS_COUNTER(complete_ppr);
445 DECLARE_STATS_COUNTER(invalidate_iotlb);
446 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
447 DECLARE_STATS_COUNTER(pri_requests);
448
449 static struct dentry *stats_dir;
450 static struct dentry *de_fflush;
451
amd_iommu_stats_add(struct __iommu_counter * cnt)452 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
453 {
454 if (stats_dir == NULL)
455 return;
456
457 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
458 &cnt->value);
459 }
460
amd_iommu_stats_init(void)461 static void amd_iommu_stats_init(void)
462 {
463 stats_dir = debugfs_create_dir("amd-iommu", NULL);
464 if (stats_dir == NULL)
465 return;
466
467 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
468 &amd_iommu_unmap_flush);
469
470 amd_iommu_stats_add(&compl_wait);
471 amd_iommu_stats_add(&cnt_map_single);
472 amd_iommu_stats_add(&cnt_unmap_single);
473 amd_iommu_stats_add(&cnt_map_sg);
474 amd_iommu_stats_add(&cnt_unmap_sg);
475 amd_iommu_stats_add(&cnt_alloc_coherent);
476 amd_iommu_stats_add(&cnt_free_coherent);
477 amd_iommu_stats_add(&cross_page);
478 amd_iommu_stats_add(&domain_flush_single);
479 amd_iommu_stats_add(&domain_flush_all);
480 amd_iommu_stats_add(&alloced_io_mem);
481 amd_iommu_stats_add(&total_map_requests);
482 amd_iommu_stats_add(&complete_ppr);
483 amd_iommu_stats_add(&invalidate_iotlb);
484 amd_iommu_stats_add(&invalidate_iotlb_all);
485 amd_iommu_stats_add(&pri_requests);
486 }
487
488 #endif
489
490 /****************************************************************************
491 *
492 * Interrupt handling functions
493 *
494 ****************************************************************************/
495
dump_dte_entry(u16 devid)496 static void dump_dte_entry(u16 devid)
497 {
498 int i;
499
500 for (i = 0; i < 4; ++i)
501 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
502 amd_iommu_dev_table[devid].data[i]);
503 }
504
dump_command(unsigned long phys_addr)505 static void dump_command(unsigned long phys_addr)
506 {
507 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
508 int i;
509
510 for (i = 0; i < 4; ++i)
511 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
512 }
513
iommu_print_event(struct amd_iommu * iommu,void * __evt)514 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
515 {
516 int type, devid, domid, flags;
517 volatile u32 *event = __evt;
518 int count = 0;
519 u64 address;
520
521 retry:
522 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
523 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
524 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
525 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
526 address = (u64)(((u64)event[3]) << 32) | event[2];
527
528 if (type == 0) {
529 /* Did we hit the erratum? */
530 if (++count == LOOP_TIMEOUT) {
531 pr_err("AMD-Vi: No event written to event log\n");
532 return;
533 }
534 udelay(1);
535 goto retry;
536 }
537
538 printk(KERN_ERR "AMD-Vi: Event logged [");
539
540 switch (type) {
541 case EVENT_TYPE_ILL_DEV:
542 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
543 "address=0x%016llx flags=0x%04x]\n",
544 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
545 address, flags);
546 dump_dte_entry(devid);
547 break;
548 case EVENT_TYPE_IO_FAULT:
549 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
550 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
551 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
552 domid, address, flags);
553 break;
554 case EVENT_TYPE_DEV_TAB_ERR:
555 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
556 "address=0x%016llx flags=0x%04x]\n",
557 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
558 address, flags);
559 break;
560 case EVENT_TYPE_PAGE_TAB_ERR:
561 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
562 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
563 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
564 domid, address, flags);
565 break;
566 case EVENT_TYPE_ILL_CMD:
567 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
568 dump_command(address);
569 break;
570 case EVENT_TYPE_CMD_HARD_ERR:
571 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
572 "flags=0x%04x]\n", address, flags);
573 break;
574 case EVENT_TYPE_IOTLB_INV_TO:
575 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
576 "address=0x%016llx]\n",
577 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
578 address);
579 break;
580 case EVENT_TYPE_INV_DEV_REQ:
581 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
582 "address=0x%016llx flags=0x%04x]\n",
583 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
584 address, flags);
585 break;
586 default:
587 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
588 }
589
590 memset(__evt, 0, 4 * sizeof(u32));
591 }
592
iommu_poll_events(struct amd_iommu * iommu)593 static void iommu_poll_events(struct amd_iommu *iommu)
594 {
595 u32 head, tail;
596
597 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
598 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
599
600 while (head != tail) {
601 iommu_print_event(iommu, iommu->evt_buf + head);
602 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
603 }
604
605 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
606 }
607
iommu_handle_ppr_entry(struct amd_iommu * iommu,u64 * raw)608 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
609 {
610 struct amd_iommu_fault fault;
611
612 INC_STATS_COUNTER(pri_requests);
613
614 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
615 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
616 return;
617 }
618
619 fault.address = raw[1];
620 fault.pasid = PPR_PASID(raw[0]);
621 fault.device_id = PPR_DEVID(raw[0]);
622 fault.tag = PPR_TAG(raw[0]);
623 fault.flags = PPR_FLAGS(raw[0]);
624
625 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
626 }
627
iommu_poll_ppr_log(struct amd_iommu * iommu)628 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
629 {
630 u32 head, tail;
631
632 if (iommu->ppr_log == NULL)
633 return;
634
635 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
636 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
637
638 while (head != tail) {
639 volatile u64 *raw;
640 u64 entry[2];
641 int i;
642
643 raw = (u64 *)(iommu->ppr_log + head);
644
645 /*
646 * Hardware bug: Interrupt may arrive before the entry is
647 * written to memory. If this happens we need to wait for the
648 * entry to arrive.
649 */
650 for (i = 0; i < LOOP_TIMEOUT; ++i) {
651 if (PPR_REQ_TYPE(raw[0]) != 0)
652 break;
653 udelay(1);
654 }
655
656 /* Avoid memcpy function-call overhead */
657 entry[0] = raw[0];
658 entry[1] = raw[1];
659
660 /*
661 * To detect the hardware bug we need to clear the entry
662 * back to zero.
663 */
664 raw[0] = raw[1] = 0UL;
665
666 /* Update head pointer of hardware ring-buffer */
667 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
668 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
669
670 /* Handle PPR entry */
671 iommu_handle_ppr_entry(iommu, entry);
672
673 /* Refresh ring-buffer information */
674 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
675 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
676 }
677 }
678
amd_iommu_int_thread(int irq,void * data)679 irqreturn_t amd_iommu_int_thread(int irq, void *data)
680 {
681 struct amd_iommu *iommu = (struct amd_iommu *) data;
682 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
683
684 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
685 /* Enable EVT and PPR interrupts again */
686 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
687 iommu->mmio_base + MMIO_STATUS_OFFSET);
688
689 if (status & MMIO_STATUS_EVT_INT_MASK) {
690 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
691 iommu_poll_events(iommu);
692 }
693
694 if (status & MMIO_STATUS_PPR_INT_MASK) {
695 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
696 iommu_poll_ppr_log(iommu);
697 }
698
699 /*
700 * Hardware bug: ERBT1312
701 * When re-enabling interrupt (by writing 1
702 * to clear the bit), the hardware might also try to set
703 * the interrupt bit in the event status register.
704 * In this scenario, the bit will be set, and disable
705 * subsequent interrupts.
706 *
707 * Workaround: The IOMMU driver should read back the
708 * status register and check if the interrupt bits are cleared.
709 * If not, driver will need to go through the interrupt handler
710 * again and re-clear the bits
711 */
712 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
713 }
714 return IRQ_HANDLED;
715 }
716
amd_iommu_int_handler(int irq,void * data)717 irqreturn_t amd_iommu_int_handler(int irq, void *data)
718 {
719 return IRQ_WAKE_THREAD;
720 }
721
722 /****************************************************************************
723 *
724 * IOMMU command queuing functions
725 *
726 ****************************************************************************/
727
wait_on_sem(volatile u64 * sem)728 static int wait_on_sem(volatile u64 *sem)
729 {
730 int i = 0;
731
732 while (*sem == 0 && i < LOOP_TIMEOUT) {
733 udelay(1);
734 i += 1;
735 }
736
737 if (i == LOOP_TIMEOUT) {
738 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
739 return -EIO;
740 }
741
742 return 0;
743 }
744
copy_cmd_to_buffer(struct amd_iommu * iommu,struct iommu_cmd * cmd,u32 tail)745 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
746 struct iommu_cmd *cmd,
747 u32 tail)
748 {
749 u8 *target;
750
751 target = iommu->cmd_buf + tail;
752 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
753
754 /* Copy command to buffer */
755 memcpy(target, cmd, sizeof(*cmd));
756
757 /* Tell the IOMMU about it */
758 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
759 }
760
build_completion_wait(struct iommu_cmd * cmd,u64 address)761 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
762 {
763 WARN_ON(address & 0x7ULL);
764
765 memset(cmd, 0, sizeof(*cmd));
766 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
767 cmd->data[1] = upper_32_bits(__pa(address));
768 cmd->data[2] = 1;
769 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
770 }
771
build_inv_dte(struct iommu_cmd * cmd,u16 devid)772 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
773 {
774 memset(cmd, 0, sizeof(*cmd));
775 cmd->data[0] = devid;
776 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
777 }
778
build_inv_iommu_pages(struct iommu_cmd * cmd,u64 address,size_t size,u16 domid,int pde)779 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
780 size_t size, u16 domid, int pde)
781 {
782 u64 pages;
783 bool s;
784
785 pages = iommu_num_pages(address, size, PAGE_SIZE);
786 s = false;
787
788 if (pages > 1) {
789 /*
790 * If we have to flush more than one page, flush all
791 * TLB entries for this domain
792 */
793 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
794 s = true;
795 }
796
797 address &= PAGE_MASK;
798
799 memset(cmd, 0, sizeof(*cmd));
800 cmd->data[1] |= domid;
801 cmd->data[2] = lower_32_bits(address);
802 cmd->data[3] = upper_32_bits(address);
803 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
804 if (s) /* size bit - we flush more than one 4kb page */
805 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
806 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
807 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
808 }
809
build_inv_iotlb_pages(struct iommu_cmd * cmd,u16 devid,int qdep,u64 address,size_t size)810 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
811 u64 address, size_t size)
812 {
813 u64 pages;
814 bool s;
815
816 pages = iommu_num_pages(address, size, PAGE_SIZE);
817 s = false;
818
819 if (pages > 1) {
820 /*
821 * If we have to flush more than one page, flush all
822 * TLB entries for this domain
823 */
824 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
825 s = true;
826 }
827
828 address &= PAGE_MASK;
829
830 memset(cmd, 0, sizeof(*cmd));
831 cmd->data[0] = devid;
832 cmd->data[0] |= (qdep & 0xff) << 24;
833 cmd->data[1] = devid;
834 cmd->data[2] = lower_32_bits(address);
835 cmd->data[3] = upper_32_bits(address);
836 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
837 if (s)
838 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
839 }
840
build_inv_iommu_pasid(struct iommu_cmd * cmd,u16 domid,int pasid,u64 address,bool size)841 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
842 u64 address, bool size)
843 {
844 memset(cmd, 0, sizeof(*cmd));
845
846 address &= ~(0xfffULL);
847
848 cmd->data[0] = pasid;
849 cmd->data[1] = domid;
850 cmd->data[2] = lower_32_bits(address);
851 cmd->data[3] = upper_32_bits(address);
852 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
853 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
854 if (size)
855 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
856 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
857 }
858
build_inv_iotlb_pasid(struct iommu_cmd * cmd,u16 devid,int pasid,int qdep,u64 address,bool size)859 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
860 int qdep, u64 address, bool size)
861 {
862 memset(cmd, 0, sizeof(*cmd));
863
864 address &= ~(0xfffULL);
865
866 cmd->data[0] = devid;
867 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
868 cmd->data[0] |= (qdep & 0xff) << 24;
869 cmd->data[1] = devid;
870 cmd->data[1] |= (pasid & 0xff) << 16;
871 cmd->data[2] = lower_32_bits(address);
872 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
873 cmd->data[3] = upper_32_bits(address);
874 if (size)
875 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
876 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
877 }
878
build_complete_ppr(struct iommu_cmd * cmd,u16 devid,int pasid,int status,int tag,bool gn)879 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
880 int status, int tag, bool gn)
881 {
882 memset(cmd, 0, sizeof(*cmd));
883
884 cmd->data[0] = devid;
885 if (gn) {
886 cmd->data[1] = pasid;
887 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
888 }
889 cmd->data[3] = tag & 0x1ff;
890 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
891
892 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
893 }
894
build_inv_all(struct iommu_cmd * cmd)895 static void build_inv_all(struct iommu_cmd *cmd)
896 {
897 memset(cmd, 0, sizeof(*cmd));
898 CMD_SET_TYPE(cmd, CMD_INV_ALL);
899 }
900
build_inv_irt(struct iommu_cmd * cmd,u16 devid)901 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
902 {
903 memset(cmd, 0, sizeof(*cmd));
904 cmd->data[0] = devid;
905 CMD_SET_TYPE(cmd, CMD_INV_IRT);
906 }
907
908 /*
909 * Writes the command to the IOMMUs command buffer and informs the
910 * hardware about the new command.
911 */
iommu_queue_command_sync(struct amd_iommu * iommu,struct iommu_cmd * cmd,bool sync)912 static int iommu_queue_command_sync(struct amd_iommu *iommu,
913 struct iommu_cmd *cmd,
914 bool sync)
915 {
916 u32 left, tail, head, next_tail;
917 unsigned long flags;
918
919 again:
920 spin_lock_irqsave(&iommu->lock, flags);
921
922 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
923 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
924 next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
925 left = (head - next_tail) % CMD_BUFFER_SIZE;
926
927 if (left <= 2) {
928 struct iommu_cmd sync_cmd;
929 volatile u64 sem = 0;
930 int ret;
931
932 build_completion_wait(&sync_cmd, (u64)&sem);
933 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
934
935 spin_unlock_irqrestore(&iommu->lock, flags);
936
937 if ((ret = wait_on_sem(&sem)) != 0)
938 return ret;
939
940 goto again;
941 }
942
943 copy_cmd_to_buffer(iommu, cmd, tail);
944
945 /* We need to sync now to make sure all commands are processed */
946 iommu->need_sync = sync;
947
948 spin_unlock_irqrestore(&iommu->lock, flags);
949
950 return 0;
951 }
952
iommu_queue_command(struct amd_iommu * iommu,struct iommu_cmd * cmd)953 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
954 {
955 return iommu_queue_command_sync(iommu, cmd, true);
956 }
957
958 /*
959 * This function queues a completion wait command into the command
960 * buffer of an IOMMU
961 */
iommu_completion_wait(struct amd_iommu * iommu)962 static int iommu_completion_wait(struct amd_iommu *iommu)
963 {
964 struct iommu_cmd cmd;
965 volatile u64 sem = 0;
966 int ret;
967
968 if (!iommu->need_sync)
969 return 0;
970
971 build_completion_wait(&cmd, (u64)&sem);
972
973 ret = iommu_queue_command_sync(iommu, &cmd, false);
974 if (ret)
975 return ret;
976
977 return wait_on_sem(&sem);
978 }
979
iommu_flush_dte(struct amd_iommu * iommu,u16 devid)980 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
981 {
982 struct iommu_cmd cmd;
983
984 build_inv_dte(&cmd, devid);
985
986 return iommu_queue_command(iommu, &cmd);
987 }
988
iommu_flush_dte_all(struct amd_iommu * iommu)989 static void iommu_flush_dte_all(struct amd_iommu *iommu)
990 {
991 u32 devid;
992
993 for (devid = 0; devid <= 0xffff; ++devid)
994 iommu_flush_dte(iommu, devid);
995
996 iommu_completion_wait(iommu);
997 }
998
999 /*
1000 * This function uses heavy locking and may disable irqs for some time. But
1001 * this is no issue because it is only called during resume.
1002 */
iommu_flush_tlb_all(struct amd_iommu * iommu)1003 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1004 {
1005 u32 dom_id;
1006
1007 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1008 struct iommu_cmd cmd;
1009 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1010 dom_id, 1);
1011 iommu_queue_command(iommu, &cmd);
1012 }
1013
1014 iommu_completion_wait(iommu);
1015 }
1016
iommu_flush_all(struct amd_iommu * iommu)1017 static void iommu_flush_all(struct amd_iommu *iommu)
1018 {
1019 struct iommu_cmd cmd;
1020
1021 build_inv_all(&cmd);
1022
1023 iommu_queue_command(iommu, &cmd);
1024 iommu_completion_wait(iommu);
1025 }
1026
iommu_flush_irt(struct amd_iommu * iommu,u16 devid)1027 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1028 {
1029 struct iommu_cmd cmd;
1030
1031 build_inv_irt(&cmd, devid);
1032
1033 iommu_queue_command(iommu, &cmd);
1034 }
1035
iommu_flush_irt_all(struct amd_iommu * iommu)1036 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1037 {
1038 u32 devid;
1039
1040 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1041 iommu_flush_irt(iommu, devid);
1042
1043 iommu_completion_wait(iommu);
1044 }
1045
iommu_flush_all_caches(struct amd_iommu * iommu)1046 void iommu_flush_all_caches(struct amd_iommu *iommu)
1047 {
1048 if (iommu_feature(iommu, FEATURE_IA)) {
1049 iommu_flush_all(iommu);
1050 } else {
1051 iommu_flush_dte_all(iommu);
1052 iommu_flush_irt_all(iommu);
1053 iommu_flush_tlb_all(iommu);
1054 }
1055 }
1056
1057 /*
1058 * Command send function for flushing on-device TLB
1059 */
device_flush_iotlb(struct iommu_dev_data * dev_data,u64 address,size_t size)1060 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1061 u64 address, size_t size)
1062 {
1063 struct amd_iommu *iommu;
1064 struct iommu_cmd cmd;
1065 int qdep;
1066
1067 qdep = dev_data->ats.qdep;
1068 iommu = amd_iommu_rlookup_table[dev_data->devid];
1069
1070 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1071
1072 return iommu_queue_command(iommu, &cmd);
1073 }
1074
1075 /*
1076 * Command send function for invalidating a device table entry
1077 */
device_flush_dte(struct iommu_dev_data * dev_data)1078 static int device_flush_dte(struct iommu_dev_data *dev_data)
1079 {
1080 struct amd_iommu *iommu;
1081 u16 alias;
1082 int ret;
1083
1084 iommu = amd_iommu_rlookup_table[dev_data->devid];
1085 alias = dev_data->alias;
1086
1087 ret = iommu_flush_dte(iommu, dev_data->devid);
1088 if (!ret && alias != dev_data->devid)
1089 ret = iommu_flush_dte(iommu, alias);
1090 if (ret)
1091 return ret;
1092
1093 if (dev_data->ats.enabled)
1094 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1095
1096 return ret;
1097 }
1098
1099 /*
1100 * TLB invalidation function which is called from the mapping functions.
1101 * It invalidates a single PTE if the range to flush is within a single
1102 * page. Otherwise it flushes the whole TLB of the IOMMU.
1103 */
__domain_flush_pages(struct protection_domain * domain,u64 address,size_t size,int pde)1104 static void __domain_flush_pages(struct protection_domain *domain,
1105 u64 address, size_t size, int pde)
1106 {
1107 struct iommu_dev_data *dev_data;
1108 struct iommu_cmd cmd;
1109 int ret = 0, i;
1110
1111 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1112
1113 for (i = 0; i < amd_iommus_present; ++i) {
1114 if (!domain->dev_iommu[i])
1115 continue;
1116
1117 /*
1118 * Devices of this domain are behind this IOMMU
1119 * We need a TLB flush
1120 */
1121 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1122 }
1123
1124 list_for_each_entry(dev_data, &domain->dev_list, list) {
1125
1126 if (!dev_data->ats.enabled)
1127 continue;
1128
1129 ret |= device_flush_iotlb(dev_data, address, size);
1130 }
1131
1132 WARN_ON(ret);
1133 }
1134
domain_flush_pages(struct protection_domain * domain,u64 address,size_t size)1135 static void domain_flush_pages(struct protection_domain *domain,
1136 u64 address, size_t size)
1137 {
1138 __domain_flush_pages(domain, address, size, 0);
1139 }
1140
1141 /* Flush the whole IO/TLB for a given protection domain */
domain_flush_tlb(struct protection_domain * domain)1142 static void domain_flush_tlb(struct protection_domain *domain)
1143 {
1144 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1145 }
1146
1147 /* Flush the whole IO/TLB for a given protection domain - including PDE */
domain_flush_tlb_pde(struct protection_domain * domain)1148 static void domain_flush_tlb_pde(struct protection_domain *domain)
1149 {
1150 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1151 }
1152
domain_flush_complete(struct protection_domain * domain)1153 static void domain_flush_complete(struct protection_domain *domain)
1154 {
1155 int i;
1156
1157 for (i = 0; i < amd_iommus_present; ++i) {
1158 if (!domain->dev_iommu[i])
1159 continue;
1160
1161 /*
1162 * Devices of this domain are behind this IOMMU
1163 * We need to wait for completion of all commands.
1164 */
1165 iommu_completion_wait(amd_iommus[i]);
1166 }
1167 }
1168
1169
1170 /*
1171 * This function flushes the DTEs for all devices in domain
1172 */
domain_flush_devices(struct protection_domain * domain)1173 static void domain_flush_devices(struct protection_domain *domain)
1174 {
1175 struct iommu_dev_data *dev_data;
1176
1177 list_for_each_entry(dev_data, &domain->dev_list, list)
1178 device_flush_dte(dev_data);
1179 }
1180
1181 /****************************************************************************
1182 *
1183 * The functions below are used the create the page table mappings for
1184 * unity mapped regions.
1185 *
1186 ****************************************************************************/
1187
1188 /*
1189 * This function is used to add another level to an IO page table. Adding
1190 * another level increases the size of the address space by 9 bits to a size up
1191 * to 64 bits.
1192 */
increase_address_space(struct protection_domain * domain,gfp_t gfp)1193 static bool increase_address_space(struct protection_domain *domain,
1194 gfp_t gfp)
1195 {
1196 u64 *pte;
1197
1198 if (domain->mode == PAGE_MODE_6_LEVEL)
1199 /* address space already 64 bit large */
1200 return false;
1201
1202 pte = (void *)get_zeroed_page(gfp);
1203 if (!pte)
1204 return false;
1205
1206 *pte = PM_LEVEL_PDE(domain->mode,
1207 virt_to_phys(domain->pt_root));
1208 domain->pt_root = pte;
1209 domain->mode += 1;
1210 domain->updated = true;
1211
1212 return true;
1213 }
1214
alloc_pte(struct protection_domain * domain,unsigned long address,unsigned long page_size,u64 ** pte_page,gfp_t gfp)1215 static u64 *alloc_pte(struct protection_domain *domain,
1216 unsigned long address,
1217 unsigned long page_size,
1218 u64 **pte_page,
1219 gfp_t gfp)
1220 {
1221 int level, end_lvl;
1222 u64 *pte, *page;
1223
1224 BUG_ON(!is_power_of_2(page_size));
1225
1226 while (address > PM_LEVEL_SIZE(domain->mode))
1227 increase_address_space(domain, gfp);
1228
1229 level = domain->mode - 1;
1230 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1231 address = PAGE_SIZE_ALIGN(address, page_size);
1232 end_lvl = PAGE_SIZE_LEVEL(page_size);
1233
1234 while (level > end_lvl) {
1235 if (!IOMMU_PTE_PRESENT(*pte)) {
1236 page = (u64 *)get_zeroed_page(gfp);
1237 if (!page)
1238 return NULL;
1239 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1240 }
1241
1242 /* No level skipping support yet */
1243 if (PM_PTE_LEVEL(*pte) != level)
1244 return NULL;
1245
1246 level -= 1;
1247
1248 pte = IOMMU_PTE_PAGE(*pte);
1249
1250 if (pte_page && level == end_lvl)
1251 *pte_page = pte;
1252
1253 pte = &pte[PM_LEVEL_INDEX(level, address)];
1254 }
1255
1256 return pte;
1257 }
1258
1259 /*
1260 * This function checks if there is a PTE for a given dma address. If
1261 * there is one, it returns the pointer to it.
1262 */
fetch_pte(struct protection_domain * domain,unsigned long address,unsigned long * page_size)1263 static u64 *fetch_pte(struct protection_domain *domain,
1264 unsigned long address,
1265 unsigned long *page_size)
1266 {
1267 int level;
1268 u64 *pte;
1269
1270 if (address > PM_LEVEL_SIZE(domain->mode))
1271 return NULL;
1272
1273 level = domain->mode - 1;
1274 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1275 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1276
1277 while (level > 0) {
1278
1279 /* Not Present */
1280 if (!IOMMU_PTE_PRESENT(*pte))
1281 return NULL;
1282
1283 /* Large PTE */
1284 if (PM_PTE_LEVEL(*pte) == 7 ||
1285 PM_PTE_LEVEL(*pte) == 0)
1286 break;
1287
1288 /* No level skipping support yet */
1289 if (PM_PTE_LEVEL(*pte) != level)
1290 return NULL;
1291
1292 level -= 1;
1293
1294 /* Walk to the next level */
1295 pte = IOMMU_PTE_PAGE(*pte);
1296 pte = &pte[PM_LEVEL_INDEX(level, address)];
1297 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1298 }
1299
1300 if (PM_PTE_LEVEL(*pte) == 0x07) {
1301 unsigned long pte_mask;
1302
1303 /*
1304 * If we have a series of large PTEs, make
1305 * sure to return a pointer to the first one.
1306 */
1307 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1308 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1309 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1310 }
1311
1312 return pte;
1313 }
1314
1315 /*
1316 * Generic mapping functions. It maps a physical address into a DMA
1317 * address space. It allocates the page table pages if necessary.
1318 * In the future it can be extended to a generic mapping function
1319 * supporting all features of AMD IOMMU page tables like level skipping
1320 * and full 64 bit address spaces.
1321 */
iommu_map_page(struct protection_domain * dom,unsigned long bus_addr,unsigned long phys_addr,int prot,unsigned long page_size)1322 static int iommu_map_page(struct protection_domain *dom,
1323 unsigned long bus_addr,
1324 unsigned long phys_addr,
1325 int prot,
1326 unsigned long page_size)
1327 {
1328 u64 __pte, *pte;
1329 int i, count;
1330
1331 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1332 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1333
1334 if (!(prot & IOMMU_PROT_MASK))
1335 return -EINVAL;
1336
1337 count = PAGE_SIZE_PTE_COUNT(page_size);
1338 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1339
1340 if (!pte)
1341 return -ENOMEM;
1342
1343 for (i = 0; i < count; ++i)
1344 if (IOMMU_PTE_PRESENT(pte[i]))
1345 return -EBUSY;
1346
1347 if (count > 1) {
1348 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1349 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1350 } else
1351 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1352
1353 if (prot & IOMMU_PROT_IR)
1354 __pte |= IOMMU_PTE_IR;
1355 if (prot & IOMMU_PROT_IW)
1356 __pte |= IOMMU_PTE_IW;
1357
1358 for (i = 0; i < count; ++i)
1359 pte[i] = __pte;
1360
1361 update_domain(dom);
1362
1363 return 0;
1364 }
1365
iommu_unmap_page(struct protection_domain * dom,unsigned long bus_addr,unsigned long page_size)1366 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1367 unsigned long bus_addr,
1368 unsigned long page_size)
1369 {
1370 unsigned long long unmapped;
1371 unsigned long unmap_size;
1372 u64 *pte;
1373
1374 BUG_ON(!is_power_of_2(page_size));
1375
1376 unmapped = 0;
1377
1378 while (unmapped < page_size) {
1379
1380 pte = fetch_pte(dom, bus_addr, &unmap_size);
1381
1382 if (pte) {
1383 int i, count;
1384
1385 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1386 for (i = 0; i < count; i++)
1387 pte[i] = 0ULL;
1388 }
1389
1390 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1391 unmapped += unmap_size;
1392 }
1393
1394 BUG_ON(unmapped && !is_power_of_2(unmapped));
1395
1396 return unmapped;
1397 }
1398
1399 /****************************************************************************
1400 *
1401 * The next functions belong to the address allocator for the dma_ops
1402 * interface functions. They work like the allocators in the other IOMMU
1403 * drivers. Its basically a bitmap which marks the allocated pages in
1404 * the aperture. Maybe it could be enhanced in the future to a more
1405 * efficient allocator.
1406 *
1407 ****************************************************************************/
1408
1409 /*
1410 * The address allocator core functions.
1411 *
1412 * called with domain->lock held
1413 */
1414
1415 /*
1416 * Used to reserve address ranges in the aperture (e.g. for exclusion
1417 * ranges.
1418 */
dma_ops_reserve_addresses(struct dma_ops_domain * dom,unsigned long start_page,unsigned int pages)1419 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1420 unsigned long start_page,
1421 unsigned int pages)
1422 {
1423 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1424
1425 if (start_page + pages > last_page)
1426 pages = last_page - start_page;
1427
1428 for (i = start_page; i < start_page + pages; ++i) {
1429 int index = i / APERTURE_RANGE_PAGES;
1430 int page = i % APERTURE_RANGE_PAGES;
1431 __set_bit(page, dom->aperture[index]->bitmap);
1432 }
1433 }
1434
1435 /*
1436 * This function is used to add a new aperture range to an existing
1437 * aperture in case of dma_ops domain allocation or address allocation
1438 * failure.
1439 */
alloc_new_range(struct dma_ops_domain * dma_dom,bool populate,gfp_t gfp)1440 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1441 bool populate, gfp_t gfp)
1442 {
1443 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1444 struct amd_iommu *iommu;
1445 unsigned long i, old_size, pte_pgsize;
1446
1447 #ifdef CONFIG_IOMMU_STRESS
1448 populate = false;
1449 #endif
1450
1451 if (index >= APERTURE_MAX_RANGES)
1452 return -ENOMEM;
1453
1454 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1455 if (!dma_dom->aperture[index])
1456 return -ENOMEM;
1457
1458 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1459 if (!dma_dom->aperture[index]->bitmap)
1460 goto out_free;
1461
1462 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1463
1464 if (populate) {
1465 unsigned long address = dma_dom->aperture_size;
1466 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1467 u64 *pte, *pte_page;
1468
1469 for (i = 0; i < num_ptes; ++i) {
1470 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1471 &pte_page, gfp);
1472 if (!pte)
1473 goto out_free;
1474
1475 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1476
1477 address += APERTURE_RANGE_SIZE / 64;
1478 }
1479 }
1480
1481 old_size = dma_dom->aperture_size;
1482 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1483
1484 /* Reserve address range used for MSI messages */
1485 if (old_size < MSI_ADDR_BASE_LO &&
1486 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1487 unsigned long spage;
1488 int pages;
1489
1490 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1491 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1492
1493 dma_ops_reserve_addresses(dma_dom, spage, pages);
1494 }
1495
1496 /* Initialize the exclusion range if necessary */
1497 for_each_iommu(iommu) {
1498 if (iommu->exclusion_start &&
1499 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1500 && iommu->exclusion_start < dma_dom->aperture_size) {
1501 unsigned long startpage;
1502 int pages = iommu_num_pages(iommu->exclusion_start,
1503 iommu->exclusion_length,
1504 PAGE_SIZE);
1505 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1506 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1507 }
1508 }
1509
1510 /*
1511 * Check for areas already mapped as present in the new aperture
1512 * range and mark those pages as reserved in the allocator. Such
1513 * mappings may already exist as a result of requested unity
1514 * mappings for devices.
1515 */
1516 for (i = dma_dom->aperture[index]->offset;
1517 i < dma_dom->aperture_size;
1518 i += pte_pgsize) {
1519 u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize);
1520 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1521 continue;
1522
1523 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT,
1524 pte_pgsize >> 12);
1525 }
1526
1527 update_domain(&dma_dom->domain);
1528
1529 return 0;
1530
1531 out_free:
1532 update_domain(&dma_dom->domain);
1533
1534 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1535
1536 kfree(dma_dom->aperture[index]);
1537 dma_dom->aperture[index] = NULL;
1538
1539 return -ENOMEM;
1540 }
1541
dma_ops_area_alloc(struct device * dev,struct dma_ops_domain * dom,unsigned int pages,unsigned long align_mask,u64 dma_mask,unsigned long start)1542 static unsigned long dma_ops_area_alloc(struct device *dev,
1543 struct dma_ops_domain *dom,
1544 unsigned int pages,
1545 unsigned long align_mask,
1546 u64 dma_mask,
1547 unsigned long start)
1548 {
1549 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1550 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1551 int i = start >> APERTURE_RANGE_SHIFT;
1552 unsigned long boundary_size, mask;
1553 unsigned long address = -1;
1554 unsigned long limit;
1555
1556 next_bit >>= PAGE_SHIFT;
1557
1558 mask = dma_get_seg_boundary(dev);
1559
1560 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
1561 1UL << (BITS_PER_LONG - PAGE_SHIFT);
1562
1563 for (;i < max_index; ++i) {
1564 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1565
1566 if (dom->aperture[i]->offset >= dma_mask)
1567 break;
1568
1569 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1570 dma_mask >> PAGE_SHIFT);
1571
1572 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1573 limit, next_bit, pages, 0,
1574 boundary_size, align_mask);
1575 if (address != -1) {
1576 address = dom->aperture[i]->offset +
1577 (address << PAGE_SHIFT);
1578 dom->next_address = address + (pages << PAGE_SHIFT);
1579 break;
1580 }
1581
1582 next_bit = 0;
1583 }
1584
1585 return address;
1586 }
1587
dma_ops_alloc_addresses(struct device * dev,struct dma_ops_domain * dom,unsigned int pages,unsigned long align_mask,u64 dma_mask)1588 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1589 struct dma_ops_domain *dom,
1590 unsigned int pages,
1591 unsigned long align_mask,
1592 u64 dma_mask)
1593 {
1594 unsigned long address;
1595
1596 #ifdef CONFIG_IOMMU_STRESS
1597 dom->next_address = 0;
1598 dom->need_flush = true;
1599 #endif
1600
1601 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1602 dma_mask, dom->next_address);
1603
1604 if (address == -1) {
1605 dom->next_address = 0;
1606 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1607 dma_mask, 0);
1608 dom->need_flush = true;
1609 }
1610
1611 if (unlikely(address == -1))
1612 address = DMA_ERROR_CODE;
1613
1614 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1615
1616 return address;
1617 }
1618
1619 /*
1620 * The address free function.
1621 *
1622 * called with domain->lock held
1623 */
dma_ops_free_addresses(struct dma_ops_domain * dom,unsigned long address,unsigned int pages)1624 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1625 unsigned long address,
1626 unsigned int pages)
1627 {
1628 unsigned i = address >> APERTURE_RANGE_SHIFT;
1629 struct aperture_range *range = dom->aperture[i];
1630
1631 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1632
1633 #ifdef CONFIG_IOMMU_STRESS
1634 if (i < 4)
1635 return;
1636 #endif
1637
1638 if (address >= dom->next_address)
1639 dom->need_flush = true;
1640
1641 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1642
1643 bitmap_clear(range->bitmap, address, pages);
1644
1645 }
1646
1647 /****************************************************************************
1648 *
1649 * The next functions belong to the domain allocation. A domain is
1650 * allocated for every IOMMU as the default domain. If device isolation
1651 * is enabled, every device get its own domain. The most important thing
1652 * about domains is the page table mapping the DMA address space they
1653 * contain.
1654 *
1655 ****************************************************************************/
1656
1657 /*
1658 * This function adds a protection domain to the global protection domain list
1659 */
add_domain_to_list(struct protection_domain * domain)1660 static void add_domain_to_list(struct protection_domain *domain)
1661 {
1662 unsigned long flags;
1663
1664 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1665 list_add(&domain->list, &amd_iommu_pd_list);
1666 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1667 }
1668
1669 /*
1670 * This function removes a protection domain to the global
1671 * protection domain list
1672 */
del_domain_from_list(struct protection_domain * domain)1673 static void del_domain_from_list(struct protection_domain *domain)
1674 {
1675 unsigned long flags;
1676
1677 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1678 list_del(&domain->list);
1679 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1680 }
1681
domain_id_alloc(void)1682 static u16 domain_id_alloc(void)
1683 {
1684 unsigned long flags;
1685 int id;
1686
1687 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1688 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1689 BUG_ON(id == 0);
1690 if (id > 0 && id < MAX_DOMAIN_ID)
1691 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1692 else
1693 id = 0;
1694 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1695
1696 return id;
1697 }
1698
domain_id_free(int id)1699 static void domain_id_free(int id)
1700 {
1701 unsigned long flags;
1702
1703 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1704 if (id > 0 && id < MAX_DOMAIN_ID)
1705 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1706 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1707 }
1708
1709 #define DEFINE_FREE_PT_FN(LVL, FN) \
1710 static void free_pt_##LVL (unsigned long __pt) \
1711 { \
1712 unsigned long p; \
1713 u64 *pt; \
1714 int i; \
1715 \
1716 pt = (u64 *)__pt; \
1717 \
1718 for (i = 0; i < 512; ++i) { \
1719 /* PTE present? */ \
1720 if (!IOMMU_PTE_PRESENT(pt[i])) \
1721 continue; \
1722 \
1723 /* Large PTE? */ \
1724 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1725 PM_PTE_LEVEL(pt[i]) == 7) \
1726 continue; \
1727 \
1728 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1729 FN(p); \
1730 } \
1731 free_page((unsigned long)pt); \
1732 }
1733
DEFINE_FREE_PT_FN(l2,free_page)1734 DEFINE_FREE_PT_FN(l2, free_page)
1735 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1736 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1737 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1738 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1739
1740 static void free_pagetable(struct protection_domain *domain)
1741 {
1742 unsigned long root = (unsigned long)domain->pt_root;
1743
1744 switch (domain->mode) {
1745 case PAGE_MODE_NONE:
1746 break;
1747 case PAGE_MODE_1_LEVEL:
1748 free_page(root);
1749 break;
1750 case PAGE_MODE_2_LEVEL:
1751 free_pt_l2(root);
1752 break;
1753 case PAGE_MODE_3_LEVEL:
1754 free_pt_l3(root);
1755 break;
1756 case PAGE_MODE_4_LEVEL:
1757 free_pt_l4(root);
1758 break;
1759 case PAGE_MODE_5_LEVEL:
1760 free_pt_l5(root);
1761 break;
1762 case PAGE_MODE_6_LEVEL:
1763 free_pt_l6(root);
1764 break;
1765 default:
1766 BUG();
1767 }
1768 }
1769
free_gcr3_tbl_level1(u64 * tbl)1770 static void free_gcr3_tbl_level1(u64 *tbl)
1771 {
1772 u64 *ptr;
1773 int i;
1774
1775 for (i = 0; i < 512; ++i) {
1776 if (!(tbl[i] & GCR3_VALID))
1777 continue;
1778
1779 ptr = __va(tbl[i] & PAGE_MASK);
1780
1781 free_page((unsigned long)ptr);
1782 }
1783 }
1784
free_gcr3_tbl_level2(u64 * tbl)1785 static void free_gcr3_tbl_level2(u64 *tbl)
1786 {
1787 u64 *ptr;
1788 int i;
1789
1790 for (i = 0; i < 512; ++i) {
1791 if (!(tbl[i] & GCR3_VALID))
1792 continue;
1793
1794 ptr = __va(tbl[i] & PAGE_MASK);
1795
1796 free_gcr3_tbl_level1(ptr);
1797 }
1798 }
1799
free_gcr3_table(struct protection_domain * domain)1800 static void free_gcr3_table(struct protection_domain *domain)
1801 {
1802 if (domain->glx == 2)
1803 free_gcr3_tbl_level2(domain->gcr3_tbl);
1804 else if (domain->glx == 1)
1805 free_gcr3_tbl_level1(domain->gcr3_tbl);
1806 else
1807 BUG_ON(domain->glx != 0);
1808
1809 free_page((unsigned long)domain->gcr3_tbl);
1810 }
1811
1812 /*
1813 * Free a domain, only used if something went wrong in the
1814 * allocation path and we need to free an already allocated page table
1815 */
dma_ops_domain_free(struct dma_ops_domain * dom)1816 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1817 {
1818 int i;
1819
1820 if (!dom)
1821 return;
1822
1823 del_domain_from_list(&dom->domain);
1824
1825 free_pagetable(&dom->domain);
1826
1827 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1828 if (!dom->aperture[i])
1829 continue;
1830 free_page((unsigned long)dom->aperture[i]->bitmap);
1831 kfree(dom->aperture[i]);
1832 }
1833
1834 kfree(dom);
1835 }
1836
1837 /*
1838 * Allocates a new protection domain usable for the dma_ops functions.
1839 * It also initializes the page table and the address allocator data
1840 * structures required for the dma_ops interface
1841 */
dma_ops_domain_alloc(void)1842 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1843 {
1844 struct dma_ops_domain *dma_dom;
1845
1846 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1847 if (!dma_dom)
1848 return NULL;
1849
1850 if (protection_domain_init(&dma_dom->domain))
1851 goto free_dma_dom;
1852
1853 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1854 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1855 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1856 dma_dom->domain.priv = dma_dom;
1857 if (!dma_dom->domain.pt_root)
1858 goto free_dma_dom;
1859
1860 dma_dom->need_flush = false;
1861
1862 add_domain_to_list(&dma_dom->domain);
1863
1864 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1865 goto free_dma_dom;
1866
1867 /*
1868 * mark the first page as allocated so we never return 0 as
1869 * a valid dma-address. So we can use 0 as error value
1870 */
1871 dma_dom->aperture[0]->bitmap[0] = 1;
1872 dma_dom->next_address = 0;
1873
1874
1875 return dma_dom;
1876
1877 free_dma_dom:
1878 dma_ops_domain_free(dma_dom);
1879
1880 return NULL;
1881 }
1882
1883 /*
1884 * little helper function to check whether a given protection domain is a
1885 * dma_ops domain
1886 */
dma_ops_domain(struct protection_domain * domain)1887 static bool dma_ops_domain(struct protection_domain *domain)
1888 {
1889 return domain->flags & PD_DMA_OPS_MASK;
1890 }
1891
set_dte_entry(u16 devid,struct protection_domain * domain,bool ats)1892 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1893 {
1894 u64 pte_root = 0;
1895 u64 flags = 0;
1896
1897 if (domain->mode != PAGE_MODE_NONE)
1898 pte_root = virt_to_phys(domain->pt_root);
1899
1900 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1901 << DEV_ENTRY_MODE_SHIFT;
1902 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1903
1904 flags = amd_iommu_dev_table[devid].data[1];
1905
1906 if (ats)
1907 flags |= DTE_FLAG_IOTLB;
1908
1909 if (domain->flags & PD_IOMMUV2_MASK) {
1910 u64 gcr3 = __pa(domain->gcr3_tbl);
1911 u64 glx = domain->glx;
1912 u64 tmp;
1913
1914 pte_root |= DTE_FLAG_GV;
1915 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1916
1917 /* First mask out possible old values for GCR3 table */
1918 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1919 flags &= ~tmp;
1920
1921 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1922 flags &= ~tmp;
1923
1924 /* Encode GCR3 table into DTE */
1925 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1926 pte_root |= tmp;
1927
1928 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1929 flags |= tmp;
1930
1931 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1932 flags |= tmp;
1933 }
1934
1935 flags &= ~(0xffffUL);
1936 flags |= domain->id;
1937
1938 amd_iommu_dev_table[devid].data[1] = flags;
1939 amd_iommu_dev_table[devid].data[0] = pte_root;
1940 }
1941
clear_dte_entry(u16 devid)1942 static void clear_dte_entry(u16 devid)
1943 {
1944 /* remove entry from the device table seen by the hardware */
1945 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1946 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1947
1948 amd_iommu_apply_erratum_63(devid);
1949 }
1950
do_attach(struct iommu_dev_data * dev_data,struct protection_domain * domain)1951 static void do_attach(struct iommu_dev_data *dev_data,
1952 struct protection_domain *domain)
1953 {
1954 struct amd_iommu *iommu;
1955 u16 alias;
1956 bool ats;
1957
1958 iommu = amd_iommu_rlookup_table[dev_data->devid];
1959 alias = dev_data->alias;
1960 ats = dev_data->ats.enabled;
1961
1962 /* Update data structures */
1963 dev_data->domain = domain;
1964 list_add(&dev_data->list, &domain->dev_list);
1965
1966 /* Do reference counting */
1967 domain->dev_iommu[iommu->index] += 1;
1968 domain->dev_cnt += 1;
1969
1970 /* Update device table */
1971 set_dte_entry(dev_data->devid, domain, ats);
1972 if (alias != dev_data->devid)
1973 set_dte_entry(alias, domain, ats);
1974
1975 device_flush_dte(dev_data);
1976 }
1977
do_detach(struct iommu_dev_data * dev_data)1978 static void do_detach(struct iommu_dev_data *dev_data)
1979 {
1980 struct amd_iommu *iommu;
1981 u16 alias;
1982
1983 /*
1984 * First check if the device is still attached. It might already
1985 * be detached from its domain because the generic
1986 * iommu_detach_group code detached it and we try again here in
1987 * our alias handling.
1988 */
1989 if (!dev_data->domain)
1990 return;
1991
1992 iommu = amd_iommu_rlookup_table[dev_data->devid];
1993 alias = dev_data->alias;
1994
1995 /* decrease reference counters */
1996 dev_data->domain->dev_iommu[iommu->index] -= 1;
1997 dev_data->domain->dev_cnt -= 1;
1998
1999 /* Update data structures */
2000 dev_data->domain = NULL;
2001 list_del(&dev_data->list);
2002 clear_dte_entry(dev_data->devid);
2003 if (alias != dev_data->devid)
2004 clear_dte_entry(alias);
2005
2006 /* Flush the DTE entry */
2007 device_flush_dte(dev_data);
2008 }
2009
2010 /*
2011 * If a device is not yet associated with a domain, this function does
2012 * assigns it visible for the hardware
2013 */
__attach_device(struct iommu_dev_data * dev_data,struct protection_domain * domain)2014 static int __attach_device(struct iommu_dev_data *dev_data,
2015 struct protection_domain *domain)
2016 {
2017 int ret;
2018
2019 /*
2020 * Must be called with IRQs disabled. Warn here to detect early
2021 * when its not.
2022 */
2023 WARN_ON(!irqs_disabled());
2024
2025 /* lock domain */
2026 spin_lock(&domain->lock);
2027
2028 ret = -EBUSY;
2029 if (dev_data->domain != NULL)
2030 goto out_unlock;
2031
2032 /* Attach alias group root */
2033 do_attach(dev_data, domain);
2034
2035 ret = 0;
2036
2037 out_unlock:
2038
2039 /* ready */
2040 spin_unlock(&domain->lock);
2041
2042 return ret;
2043 }
2044
2045
pdev_iommuv2_disable(struct pci_dev * pdev)2046 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2047 {
2048 pci_disable_ats(pdev);
2049 pci_disable_pri(pdev);
2050 pci_disable_pasid(pdev);
2051 }
2052
2053 /* FIXME: Change generic reset-function to do the same */
pri_reset_while_enabled(struct pci_dev * pdev)2054 static int pri_reset_while_enabled(struct pci_dev *pdev)
2055 {
2056 u16 control;
2057 int pos;
2058
2059 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2060 if (!pos)
2061 return -EINVAL;
2062
2063 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2064 control |= PCI_PRI_CTRL_RESET;
2065 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2066
2067 return 0;
2068 }
2069
pdev_iommuv2_enable(struct pci_dev * pdev)2070 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2071 {
2072 bool reset_enable;
2073 int reqs, ret;
2074
2075 /* FIXME: Hardcode number of outstanding requests for now */
2076 reqs = 32;
2077 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2078 reqs = 1;
2079 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2080
2081 /* Only allow access to user-accessible pages */
2082 ret = pci_enable_pasid(pdev, 0);
2083 if (ret)
2084 goto out_err;
2085
2086 /* First reset the PRI state of the device */
2087 ret = pci_reset_pri(pdev);
2088 if (ret)
2089 goto out_err;
2090
2091 /* Enable PRI */
2092 ret = pci_enable_pri(pdev, reqs);
2093 if (ret)
2094 goto out_err;
2095
2096 if (reset_enable) {
2097 ret = pri_reset_while_enabled(pdev);
2098 if (ret)
2099 goto out_err;
2100 }
2101
2102 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2103 if (ret)
2104 goto out_err;
2105
2106 return 0;
2107
2108 out_err:
2109 pci_disable_pri(pdev);
2110 pci_disable_pasid(pdev);
2111
2112 return ret;
2113 }
2114
2115 /* FIXME: Move this to PCI code */
2116 #define PCI_PRI_TLP_OFF (1 << 15)
2117
pci_pri_tlp_required(struct pci_dev * pdev)2118 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2119 {
2120 u16 status;
2121 int pos;
2122
2123 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2124 if (!pos)
2125 return false;
2126
2127 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2128
2129 return (status & PCI_PRI_TLP_OFF) ? true : false;
2130 }
2131
2132 /*
2133 * If a device is not yet associated with a domain, this function
2134 * assigns it visible for the hardware
2135 */
attach_device(struct device * dev,struct protection_domain * domain)2136 static int attach_device(struct device *dev,
2137 struct protection_domain *domain)
2138 {
2139 struct pci_dev *pdev = to_pci_dev(dev);
2140 struct iommu_dev_data *dev_data;
2141 unsigned long flags;
2142 int ret;
2143
2144 dev_data = get_dev_data(dev);
2145
2146 if (domain->flags & PD_IOMMUV2_MASK) {
2147 if (!dev_data->passthrough)
2148 return -EINVAL;
2149
2150 if (dev_data->iommu_v2) {
2151 if (pdev_iommuv2_enable(pdev) != 0)
2152 return -EINVAL;
2153
2154 dev_data->ats.enabled = true;
2155 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2156 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2157 }
2158 } else if (amd_iommu_iotlb_sup &&
2159 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2160 dev_data->ats.enabled = true;
2161 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2162 }
2163
2164 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2165 ret = __attach_device(dev_data, domain);
2166 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2167
2168 /*
2169 * We might boot into a crash-kernel here. The crashed kernel
2170 * left the caches in the IOMMU dirty. So we have to flush
2171 * here to evict all dirty stuff.
2172 */
2173 domain_flush_tlb_pde(domain);
2174
2175 return ret;
2176 }
2177
2178 /*
2179 * Removes a device from a protection domain (unlocked)
2180 */
__detach_device(struct iommu_dev_data * dev_data)2181 static void __detach_device(struct iommu_dev_data *dev_data)
2182 {
2183 struct protection_domain *domain;
2184
2185 /*
2186 * Must be called with IRQs disabled. Warn here to detect early
2187 * when its not.
2188 */
2189 WARN_ON(!irqs_disabled());
2190
2191 if (WARN_ON(!dev_data->domain))
2192 return;
2193
2194 domain = dev_data->domain;
2195
2196 spin_lock(&domain->lock);
2197
2198 do_detach(dev_data);
2199
2200 spin_unlock(&domain->lock);
2201 }
2202
2203 /*
2204 * Removes a device from a protection domain (with devtable_lock held)
2205 */
detach_device(struct device * dev)2206 static void detach_device(struct device *dev)
2207 {
2208 struct protection_domain *domain;
2209 struct iommu_dev_data *dev_data;
2210 unsigned long flags;
2211
2212 dev_data = get_dev_data(dev);
2213 domain = dev_data->domain;
2214
2215 /* lock device table */
2216 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2217 __detach_device(dev_data);
2218 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2219
2220 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2221 pdev_iommuv2_disable(to_pci_dev(dev));
2222 else if (dev_data->ats.enabled)
2223 pci_disable_ats(to_pci_dev(dev));
2224
2225 dev_data->ats.enabled = false;
2226 }
2227
amd_iommu_add_device(struct device * dev)2228 static int amd_iommu_add_device(struct device *dev)
2229 {
2230 struct iommu_dev_data *dev_data;
2231 struct iommu_domain *domain;
2232 struct amd_iommu *iommu;
2233 u16 devid;
2234 int ret;
2235
2236 if (!check_device(dev) || get_dev_data(dev))
2237 return 0;
2238
2239 devid = get_device_id(dev);
2240 iommu = amd_iommu_rlookup_table[devid];
2241
2242 ret = iommu_init_device(dev);
2243 if (ret) {
2244 if (ret != -ENOTSUPP)
2245 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2246 dev_name(dev));
2247
2248 iommu_ignore_device(dev);
2249 dev->archdata.dma_ops = &nommu_dma_ops;
2250 goto out;
2251 }
2252 init_iommu_group(dev);
2253
2254 dev_data = get_dev_data(dev);
2255
2256 BUG_ON(!dev_data);
2257
2258 if (iommu_pass_through || dev_data->iommu_v2)
2259 iommu_request_dm_for_dev(dev);
2260
2261 /* Domains are initialized for this device - have a look what we ended up with */
2262 domain = iommu_get_domain_for_dev(dev);
2263 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2264 dev_data->passthrough = true;
2265 else
2266 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2267
2268 out:
2269 iommu_completion_wait(iommu);
2270
2271 return 0;
2272 }
2273
amd_iommu_remove_device(struct device * dev)2274 static void amd_iommu_remove_device(struct device *dev)
2275 {
2276 struct amd_iommu *iommu;
2277 u16 devid;
2278
2279 if (!check_device(dev))
2280 return;
2281
2282 devid = get_device_id(dev);
2283 iommu = amd_iommu_rlookup_table[devid];
2284
2285 iommu_uninit_device(dev);
2286 iommu_completion_wait(iommu);
2287 }
2288
2289 /*****************************************************************************
2290 *
2291 * The next functions belong to the dma_ops mapping/unmapping code.
2292 *
2293 *****************************************************************************/
2294
2295 /*
2296 * In the dma_ops path we only have the struct device. This function
2297 * finds the corresponding IOMMU, the protection domain and the
2298 * requestor id for a given device.
2299 * If the device is not yet associated with a domain this is also done
2300 * in this function.
2301 */
get_domain(struct device * dev)2302 static struct protection_domain *get_domain(struct device *dev)
2303 {
2304 struct protection_domain *domain;
2305 struct iommu_domain *io_domain;
2306
2307 if (!check_device(dev))
2308 return ERR_PTR(-EINVAL);
2309
2310 io_domain = iommu_get_domain_for_dev(dev);
2311 if (!io_domain)
2312 return NULL;
2313
2314 domain = to_pdomain(io_domain);
2315 if (!dma_ops_domain(domain))
2316 return ERR_PTR(-EBUSY);
2317
2318 return domain;
2319 }
2320
update_device_table(struct protection_domain * domain)2321 static void update_device_table(struct protection_domain *domain)
2322 {
2323 struct iommu_dev_data *dev_data;
2324
2325 list_for_each_entry(dev_data, &domain->dev_list, list)
2326 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2327 }
2328
update_domain(struct protection_domain * domain)2329 static void update_domain(struct protection_domain *domain)
2330 {
2331 if (!domain->updated)
2332 return;
2333
2334 update_device_table(domain);
2335
2336 domain_flush_devices(domain);
2337 domain_flush_tlb_pde(domain);
2338
2339 domain->updated = false;
2340 }
2341
2342 /*
2343 * This function fetches the PTE for a given address in the aperture
2344 */
dma_ops_get_pte(struct dma_ops_domain * dom,unsigned long address)2345 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2346 unsigned long address)
2347 {
2348 struct aperture_range *aperture;
2349 u64 *pte, *pte_page;
2350
2351 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2352 if (!aperture)
2353 return NULL;
2354
2355 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2356 if (!pte) {
2357 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2358 GFP_ATOMIC);
2359 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2360 } else
2361 pte += PM_LEVEL_INDEX(0, address);
2362
2363 update_domain(&dom->domain);
2364
2365 return pte;
2366 }
2367
2368 /*
2369 * This is the generic map function. It maps one 4kb page at paddr to
2370 * the given address in the DMA address space for the domain.
2371 */
dma_ops_domain_map(struct dma_ops_domain * dom,unsigned long address,phys_addr_t paddr,int direction)2372 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2373 unsigned long address,
2374 phys_addr_t paddr,
2375 int direction)
2376 {
2377 u64 *pte, __pte;
2378
2379 WARN_ON(address > dom->aperture_size);
2380
2381 paddr &= PAGE_MASK;
2382
2383 pte = dma_ops_get_pte(dom, address);
2384 if (!pte)
2385 return DMA_ERROR_CODE;
2386
2387 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2388
2389 if (direction == DMA_TO_DEVICE)
2390 __pte |= IOMMU_PTE_IR;
2391 else if (direction == DMA_FROM_DEVICE)
2392 __pte |= IOMMU_PTE_IW;
2393 else if (direction == DMA_BIDIRECTIONAL)
2394 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2395
2396 WARN_ON(*pte);
2397
2398 *pte = __pte;
2399
2400 return (dma_addr_t)address;
2401 }
2402
2403 /*
2404 * The generic unmapping function for on page in the DMA address space.
2405 */
dma_ops_domain_unmap(struct dma_ops_domain * dom,unsigned long address)2406 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2407 unsigned long address)
2408 {
2409 struct aperture_range *aperture;
2410 u64 *pte;
2411
2412 if (address >= dom->aperture_size)
2413 return;
2414
2415 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2416 if (!aperture)
2417 return;
2418
2419 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2420 if (!pte)
2421 return;
2422
2423 pte += PM_LEVEL_INDEX(0, address);
2424
2425 WARN_ON(!*pte);
2426
2427 *pte = 0ULL;
2428 }
2429
2430 /*
2431 * This function contains common code for mapping of a physically
2432 * contiguous memory region into DMA address space. It is used by all
2433 * mapping functions provided with this IOMMU driver.
2434 * Must be called with the domain lock held.
2435 */
__map_single(struct device * dev,struct dma_ops_domain * dma_dom,phys_addr_t paddr,size_t size,int dir,bool align,u64 dma_mask)2436 static dma_addr_t __map_single(struct device *dev,
2437 struct dma_ops_domain *dma_dom,
2438 phys_addr_t paddr,
2439 size_t size,
2440 int dir,
2441 bool align,
2442 u64 dma_mask)
2443 {
2444 dma_addr_t offset = paddr & ~PAGE_MASK;
2445 dma_addr_t address, start, ret;
2446 unsigned int pages;
2447 unsigned long align_mask = 0;
2448 int i;
2449
2450 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2451 paddr &= PAGE_MASK;
2452
2453 INC_STATS_COUNTER(total_map_requests);
2454
2455 if (pages > 1)
2456 INC_STATS_COUNTER(cross_page);
2457
2458 if (align)
2459 align_mask = (1UL << get_order(size)) - 1;
2460
2461 retry:
2462 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2463 dma_mask);
2464 if (unlikely(address == DMA_ERROR_CODE)) {
2465 /*
2466 * setting next_address here will let the address
2467 * allocator only scan the new allocated range in the
2468 * first run. This is a small optimization.
2469 */
2470 dma_dom->next_address = dma_dom->aperture_size;
2471
2472 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2473 goto out;
2474
2475 /*
2476 * aperture was successfully enlarged by 128 MB, try
2477 * allocation again
2478 */
2479 goto retry;
2480 }
2481
2482 start = address;
2483 for (i = 0; i < pages; ++i) {
2484 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2485 if (ret == DMA_ERROR_CODE)
2486 goto out_unmap;
2487
2488 paddr += PAGE_SIZE;
2489 start += PAGE_SIZE;
2490 }
2491 address += offset;
2492
2493 ADD_STATS_COUNTER(alloced_io_mem, size);
2494
2495 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2496 domain_flush_tlb(&dma_dom->domain);
2497 dma_dom->need_flush = false;
2498 } else if (unlikely(amd_iommu_np_cache))
2499 domain_flush_pages(&dma_dom->domain, address, size);
2500
2501 out:
2502 return address;
2503
2504 out_unmap:
2505
2506 for (--i; i >= 0; --i) {
2507 start -= PAGE_SIZE;
2508 dma_ops_domain_unmap(dma_dom, start);
2509 }
2510
2511 dma_ops_free_addresses(dma_dom, address, pages);
2512
2513 return DMA_ERROR_CODE;
2514 }
2515
2516 /*
2517 * Does the reverse of the __map_single function. Must be called with
2518 * the domain lock held too
2519 */
__unmap_single(struct dma_ops_domain * dma_dom,dma_addr_t dma_addr,size_t size,int dir)2520 static void __unmap_single(struct dma_ops_domain *dma_dom,
2521 dma_addr_t dma_addr,
2522 size_t size,
2523 int dir)
2524 {
2525 dma_addr_t flush_addr;
2526 dma_addr_t i, start;
2527 unsigned int pages;
2528
2529 if ((dma_addr == DMA_ERROR_CODE) ||
2530 (dma_addr + size > dma_dom->aperture_size))
2531 return;
2532
2533 flush_addr = dma_addr;
2534 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2535 dma_addr &= PAGE_MASK;
2536 start = dma_addr;
2537
2538 for (i = 0; i < pages; ++i) {
2539 dma_ops_domain_unmap(dma_dom, start);
2540 start += PAGE_SIZE;
2541 }
2542
2543 SUB_STATS_COUNTER(alloced_io_mem, size);
2544
2545 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2546
2547 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2548 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2549 dma_dom->need_flush = false;
2550 }
2551 }
2552
2553 /*
2554 * The exported map_single function for dma_ops.
2555 */
map_page(struct device * dev,struct page * page,unsigned long offset,size_t size,enum dma_data_direction dir,struct dma_attrs * attrs)2556 static dma_addr_t map_page(struct device *dev, struct page *page,
2557 unsigned long offset, size_t size,
2558 enum dma_data_direction dir,
2559 struct dma_attrs *attrs)
2560 {
2561 unsigned long flags;
2562 struct protection_domain *domain;
2563 dma_addr_t addr;
2564 u64 dma_mask;
2565 phys_addr_t paddr = page_to_phys(page) + offset;
2566
2567 INC_STATS_COUNTER(cnt_map_single);
2568
2569 domain = get_domain(dev);
2570 if (PTR_ERR(domain) == -EINVAL)
2571 return (dma_addr_t)paddr;
2572 else if (IS_ERR(domain))
2573 return DMA_ERROR_CODE;
2574
2575 dma_mask = *dev->dma_mask;
2576
2577 spin_lock_irqsave(&domain->lock, flags);
2578
2579 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2580 dma_mask);
2581 if (addr == DMA_ERROR_CODE)
2582 goto out;
2583
2584 domain_flush_complete(domain);
2585
2586 out:
2587 spin_unlock_irqrestore(&domain->lock, flags);
2588
2589 return addr;
2590 }
2591
2592 /*
2593 * The exported unmap_single function for dma_ops.
2594 */
unmap_page(struct device * dev,dma_addr_t dma_addr,size_t size,enum dma_data_direction dir,struct dma_attrs * attrs)2595 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2596 enum dma_data_direction dir, struct dma_attrs *attrs)
2597 {
2598 unsigned long flags;
2599 struct protection_domain *domain;
2600
2601 INC_STATS_COUNTER(cnt_unmap_single);
2602
2603 domain = get_domain(dev);
2604 if (IS_ERR(domain))
2605 return;
2606
2607 spin_lock_irqsave(&domain->lock, flags);
2608
2609 __unmap_single(domain->priv, dma_addr, size, dir);
2610
2611 domain_flush_complete(domain);
2612
2613 spin_unlock_irqrestore(&domain->lock, flags);
2614 }
2615
2616 /*
2617 * The exported map_sg function for dma_ops (handles scatter-gather
2618 * lists).
2619 */
map_sg(struct device * dev,struct scatterlist * sglist,int nelems,enum dma_data_direction dir,struct dma_attrs * attrs)2620 static int map_sg(struct device *dev, struct scatterlist *sglist,
2621 int nelems, enum dma_data_direction dir,
2622 struct dma_attrs *attrs)
2623 {
2624 unsigned long flags;
2625 struct protection_domain *domain;
2626 int i;
2627 struct scatterlist *s;
2628 phys_addr_t paddr;
2629 int mapped_elems = 0;
2630 u64 dma_mask;
2631
2632 INC_STATS_COUNTER(cnt_map_sg);
2633
2634 domain = get_domain(dev);
2635 if (IS_ERR(domain))
2636 return 0;
2637
2638 dma_mask = *dev->dma_mask;
2639
2640 spin_lock_irqsave(&domain->lock, flags);
2641
2642 for_each_sg(sglist, s, nelems, i) {
2643 paddr = sg_phys(s);
2644
2645 s->dma_address = __map_single(dev, domain->priv,
2646 paddr, s->length, dir, false,
2647 dma_mask);
2648
2649 if (s->dma_address) {
2650 s->dma_length = s->length;
2651 mapped_elems++;
2652 } else
2653 goto unmap;
2654 }
2655
2656 domain_flush_complete(domain);
2657
2658 out:
2659 spin_unlock_irqrestore(&domain->lock, flags);
2660
2661 return mapped_elems;
2662 unmap:
2663 for_each_sg(sglist, s, mapped_elems, i) {
2664 if (s->dma_address)
2665 __unmap_single(domain->priv, s->dma_address,
2666 s->dma_length, dir);
2667 s->dma_address = s->dma_length = 0;
2668 }
2669
2670 mapped_elems = 0;
2671
2672 goto out;
2673 }
2674
2675 /*
2676 * The exported map_sg function for dma_ops (handles scatter-gather
2677 * lists).
2678 */
unmap_sg(struct device * dev,struct scatterlist * sglist,int nelems,enum dma_data_direction dir,struct dma_attrs * attrs)2679 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2680 int nelems, enum dma_data_direction dir,
2681 struct dma_attrs *attrs)
2682 {
2683 unsigned long flags;
2684 struct protection_domain *domain;
2685 struct scatterlist *s;
2686 int i;
2687
2688 INC_STATS_COUNTER(cnt_unmap_sg);
2689
2690 domain = get_domain(dev);
2691 if (IS_ERR(domain))
2692 return;
2693
2694 spin_lock_irqsave(&domain->lock, flags);
2695
2696 for_each_sg(sglist, s, nelems, i) {
2697 __unmap_single(domain->priv, s->dma_address,
2698 s->dma_length, dir);
2699 s->dma_address = s->dma_length = 0;
2700 }
2701
2702 domain_flush_complete(domain);
2703
2704 spin_unlock_irqrestore(&domain->lock, flags);
2705 }
2706
2707 /*
2708 * The exported alloc_coherent function for dma_ops.
2709 */
alloc_coherent(struct device * dev,size_t size,dma_addr_t * dma_addr,gfp_t flag,struct dma_attrs * attrs)2710 static void *alloc_coherent(struct device *dev, size_t size,
2711 dma_addr_t *dma_addr, gfp_t flag,
2712 struct dma_attrs *attrs)
2713 {
2714 u64 dma_mask = dev->coherent_dma_mask;
2715 struct protection_domain *domain;
2716 unsigned long flags;
2717 struct page *page;
2718
2719 INC_STATS_COUNTER(cnt_alloc_coherent);
2720
2721 domain = get_domain(dev);
2722 if (PTR_ERR(domain) == -EINVAL) {
2723 page = alloc_pages(flag, get_order(size));
2724 *dma_addr = page_to_phys(page);
2725 return page_address(page);
2726 } else if (IS_ERR(domain))
2727 return NULL;
2728
2729 size = PAGE_ALIGN(size);
2730 dma_mask = dev->coherent_dma_mask;
2731 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2732 flag |= __GFP_ZERO;
2733
2734 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2735 if (!page) {
2736 if (!gfpflags_allow_blocking(flag))
2737 return NULL;
2738
2739 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2740 get_order(size));
2741 if (!page)
2742 return NULL;
2743 }
2744
2745 if (!dma_mask)
2746 dma_mask = *dev->dma_mask;
2747
2748 spin_lock_irqsave(&domain->lock, flags);
2749
2750 *dma_addr = __map_single(dev, domain->priv, page_to_phys(page),
2751 size, DMA_BIDIRECTIONAL, true, dma_mask);
2752
2753 if (*dma_addr == DMA_ERROR_CODE) {
2754 spin_unlock_irqrestore(&domain->lock, flags);
2755 goto out_free;
2756 }
2757
2758 domain_flush_complete(domain);
2759
2760 spin_unlock_irqrestore(&domain->lock, flags);
2761
2762 return page_address(page);
2763
2764 out_free:
2765
2766 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2767 __free_pages(page, get_order(size));
2768
2769 return NULL;
2770 }
2771
2772 /*
2773 * The exported free_coherent function for dma_ops.
2774 */
free_coherent(struct device * dev,size_t size,void * virt_addr,dma_addr_t dma_addr,struct dma_attrs * attrs)2775 static void free_coherent(struct device *dev, size_t size,
2776 void *virt_addr, dma_addr_t dma_addr,
2777 struct dma_attrs *attrs)
2778 {
2779 struct protection_domain *domain;
2780 unsigned long flags;
2781 struct page *page;
2782
2783 INC_STATS_COUNTER(cnt_free_coherent);
2784
2785 page = virt_to_page(virt_addr);
2786 size = PAGE_ALIGN(size);
2787
2788 domain = get_domain(dev);
2789 if (IS_ERR(domain))
2790 goto free_mem;
2791
2792 spin_lock_irqsave(&domain->lock, flags);
2793
2794 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2795
2796 domain_flush_complete(domain);
2797
2798 spin_unlock_irqrestore(&domain->lock, flags);
2799
2800 free_mem:
2801 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2802 __free_pages(page, get_order(size));
2803 }
2804
2805 /*
2806 * This function is called by the DMA layer to find out if we can handle a
2807 * particular device. It is part of the dma_ops.
2808 */
amd_iommu_dma_supported(struct device * dev,u64 mask)2809 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2810 {
2811 return check_device(dev);
2812 }
2813
2814 static struct dma_map_ops amd_iommu_dma_ops = {
2815 .alloc = alloc_coherent,
2816 .free = free_coherent,
2817 .map_page = map_page,
2818 .unmap_page = unmap_page,
2819 .map_sg = map_sg,
2820 .unmap_sg = unmap_sg,
2821 .dma_supported = amd_iommu_dma_supported,
2822 };
2823
amd_iommu_init_api(void)2824 int __init amd_iommu_init_api(void)
2825 {
2826 return bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2827 }
2828
amd_iommu_init_dma_ops(void)2829 int __init amd_iommu_init_dma_ops(void)
2830 {
2831 swiotlb = iommu_pass_through ? 1 : 0;
2832 iommu_detected = 1;
2833
2834 /*
2835 * In case we don't initialize SWIOTLB (actually the common case
2836 * when AMD IOMMU is enabled), make sure there are global
2837 * dma_ops set as a fall-back for devices not handled by this
2838 * driver (for example non-PCI devices).
2839 */
2840 if (!swiotlb)
2841 dma_ops = &nommu_dma_ops;
2842
2843 amd_iommu_stats_init();
2844
2845 if (amd_iommu_unmap_flush)
2846 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2847 else
2848 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2849
2850 return 0;
2851 }
2852
2853 /*****************************************************************************
2854 *
2855 * The following functions belong to the exported interface of AMD IOMMU
2856 *
2857 * This interface allows access to lower level functions of the IOMMU
2858 * like protection domain handling and assignement of devices to domains
2859 * which is not possible with the dma_ops interface.
2860 *
2861 *****************************************************************************/
2862
cleanup_domain(struct protection_domain * domain)2863 static void cleanup_domain(struct protection_domain *domain)
2864 {
2865 struct iommu_dev_data *entry;
2866 unsigned long flags;
2867
2868 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2869
2870 while (!list_empty(&domain->dev_list)) {
2871 entry = list_first_entry(&domain->dev_list,
2872 struct iommu_dev_data, list);
2873 __detach_device(entry);
2874 }
2875
2876 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2877 }
2878
protection_domain_free(struct protection_domain * domain)2879 static void protection_domain_free(struct protection_domain *domain)
2880 {
2881 if (!domain)
2882 return;
2883
2884 del_domain_from_list(domain);
2885
2886 if (domain->id)
2887 domain_id_free(domain->id);
2888
2889 kfree(domain);
2890 }
2891
protection_domain_init(struct protection_domain * domain)2892 static int protection_domain_init(struct protection_domain *domain)
2893 {
2894 spin_lock_init(&domain->lock);
2895 mutex_init(&domain->api_lock);
2896 domain->id = domain_id_alloc();
2897 if (!domain->id)
2898 return -ENOMEM;
2899 INIT_LIST_HEAD(&domain->dev_list);
2900
2901 return 0;
2902 }
2903
protection_domain_alloc(void)2904 static struct protection_domain *protection_domain_alloc(void)
2905 {
2906 struct protection_domain *domain;
2907
2908 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2909 if (!domain)
2910 return NULL;
2911
2912 if (protection_domain_init(domain))
2913 goto out_err;
2914
2915 add_domain_to_list(domain);
2916
2917 return domain;
2918
2919 out_err:
2920 kfree(domain);
2921
2922 return NULL;
2923 }
2924
amd_iommu_domain_alloc(unsigned type)2925 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2926 {
2927 struct protection_domain *pdomain;
2928 struct dma_ops_domain *dma_domain;
2929
2930 switch (type) {
2931 case IOMMU_DOMAIN_UNMANAGED:
2932 pdomain = protection_domain_alloc();
2933 if (!pdomain)
2934 return NULL;
2935
2936 pdomain->mode = PAGE_MODE_3_LEVEL;
2937 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2938 if (!pdomain->pt_root) {
2939 protection_domain_free(pdomain);
2940 return NULL;
2941 }
2942
2943 pdomain->domain.geometry.aperture_start = 0;
2944 pdomain->domain.geometry.aperture_end = ~0ULL;
2945 pdomain->domain.geometry.force_aperture = true;
2946
2947 break;
2948 case IOMMU_DOMAIN_DMA:
2949 dma_domain = dma_ops_domain_alloc();
2950 if (!dma_domain) {
2951 pr_err("AMD-Vi: Failed to allocate\n");
2952 return NULL;
2953 }
2954 pdomain = &dma_domain->domain;
2955 break;
2956 case IOMMU_DOMAIN_IDENTITY:
2957 pdomain = protection_domain_alloc();
2958 if (!pdomain)
2959 return NULL;
2960
2961 pdomain->mode = PAGE_MODE_NONE;
2962 break;
2963 default:
2964 return NULL;
2965 }
2966
2967 return &pdomain->domain;
2968 }
2969
amd_iommu_domain_free(struct iommu_domain * dom)2970 static void amd_iommu_domain_free(struct iommu_domain *dom)
2971 {
2972 struct protection_domain *domain;
2973
2974 if (!dom)
2975 return;
2976
2977 domain = to_pdomain(dom);
2978
2979 if (domain->dev_cnt > 0)
2980 cleanup_domain(domain);
2981
2982 BUG_ON(domain->dev_cnt != 0);
2983
2984 if (domain->mode != PAGE_MODE_NONE)
2985 free_pagetable(domain);
2986
2987 if (domain->flags & PD_IOMMUV2_MASK)
2988 free_gcr3_table(domain);
2989
2990 protection_domain_free(domain);
2991 }
2992
amd_iommu_detach_device(struct iommu_domain * dom,struct device * dev)2993 static void amd_iommu_detach_device(struct iommu_domain *dom,
2994 struct device *dev)
2995 {
2996 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2997 struct amd_iommu *iommu;
2998 u16 devid;
2999
3000 if (!check_device(dev))
3001 return;
3002
3003 devid = get_device_id(dev);
3004
3005 if (dev_data->domain != NULL)
3006 detach_device(dev);
3007
3008 iommu = amd_iommu_rlookup_table[devid];
3009 if (!iommu)
3010 return;
3011
3012 iommu_completion_wait(iommu);
3013 }
3014
amd_iommu_attach_device(struct iommu_domain * dom,struct device * dev)3015 static int amd_iommu_attach_device(struct iommu_domain *dom,
3016 struct device *dev)
3017 {
3018 struct protection_domain *domain = to_pdomain(dom);
3019 struct iommu_dev_data *dev_data;
3020 struct amd_iommu *iommu;
3021 int ret;
3022
3023 if (!check_device(dev))
3024 return -EINVAL;
3025
3026 dev_data = dev->archdata.iommu;
3027
3028 iommu = amd_iommu_rlookup_table[dev_data->devid];
3029 if (!iommu)
3030 return -EINVAL;
3031
3032 if (dev_data->domain)
3033 detach_device(dev);
3034
3035 ret = attach_device(dev, domain);
3036
3037 iommu_completion_wait(iommu);
3038
3039 return ret;
3040 }
3041
amd_iommu_map(struct iommu_domain * dom,unsigned long iova,phys_addr_t paddr,size_t page_size,int iommu_prot)3042 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3043 phys_addr_t paddr, size_t page_size, int iommu_prot)
3044 {
3045 struct protection_domain *domain = to_pdomain(dom);
3046 int prot = 0;
3047 int ret;
3048
3049 if (domain->mode == PAGE_MODE_NONE)
3050 return -EINVAL;
3051
3052 if (iommu_prot & IOMMU_READ)
3053 prot |= IOMMU_PROT_IR;
3054 if (iommu_prot & IOMMU_WRITE)
3055 prot |= IOMMU_PROT_IW;
3056
3057 mutex_lock(&domain->api_lock);
3058 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3059 mutex_unlock(&domain->api_lock);
3060
3061 return ret;
3062 }
3063
amd_iommu_unmap(struct iommu_domain * dom,unsigned long iova,size_t page_size)3064 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3065 size_t page_size)
3066 {
3067 struct protection_domain *domain = to_pdomain(dom);
3068 size_t unmap_size;
3069
3070 if (domain->mode == PAGE_MODE_NONE)
3071 return -EINVAL;
3072
3073 mutex_lock(&domain->api_lock);
3074 unmap_size = iommu_unmap_page(domain, iova, page_size);
3075 mutex_unlock(&domain->api_lock);
3076
3077 domain_flush_tlb_pde(domain);
3078
3079 return unmap_size;
3080 }
3081
amd_iommu_iova_to_phys(struct iommu_domain * dom,dma_addr_t iova)3082 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3083 dma_addr_t iova)
3084 {
3085 struct protection_domain *domain = to_pdomain(dom);
3086 unsigned long offset_mask, pte_pgsize;
3087 u64 *pte, __pte;
3088
3089 if (domain->mode == PAGE_MODE_NONE)
3090 return iova;
3091
3092 pte = fetch_pte(domain, iova, &pte_pgsize);
3093
3094 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3095 return 0;
3096
3097 offset_mask = pte_pgsize - 1;
3098 __pte = *pte & PM_ADDR_MASK;
3099
3100 return (__pte & ~offset_mask) | (iova & offset_mask);
3101 }
3102
amd_iommu_capable(enum iommu_cap cap)3103 static bool amd_iommu_capable(enum iommu_cap cap)
3104 {
3105 switch (cap) {
3106 case IOMMU_CAP_CACHE_COHERENCY:
3107 return true;
3108 case IOMMU_CAP_INTR_REMAP:
3109 return (irq_remapping_enabled == 1);
3110 case IOMMU_CAP_NOEXEC:
3111 return false;
3112 }
3113
3114 return false;
3115 }
3116
amd_iommu_get_dm_regions(struct device * dev,struct list_head * head)3117 static void amd_iommu_get_dm_regions(struct device *dev,
3118 struct list_head *head)
3119 {
3120 struct unity_map_entry *entry;
3121 u16 devid;
3122
3123 devid = get_device_id(dev);
3124
3125 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3126 struct iommu_dm_region *region;
3127
3128 if (devid < entry->devid_start || devid > entry->devid_end)
3129 continue;
3130
3131 region = kzalloc(sizeof(*region), GFP_KERNEL);
3132 if (!region) {
3133 pr_err("Out of memory allocating dm-regions for %s\n",
3134 dev_name(dev));
3135 return;
3136 }
3137
3138 region->start = entry->address_start;
3139 region->length = entry->address_end - entry->address_start;
3140 if (entry->prot & IOMMU_PROT_IR)
3141 region->prot |= IOMMU_READ;
3142 if (entry->prot & IOMMU_PROT_IW)
3143 region->prot |= IOMMU_WRITE;
3144
3145 list_add_tail(®ion->list, head);
3146 }
3147 }
3148
amd_iommu_put_dm_regions(struct device * dev,struct list_head * head)3149 static void amd_iommu_put_dm_regions(struct device *dev,
3150 struct list_head *head)
3151 {
3152 struct iommu_dm_region *entry, *next;
3153
3154 list_for_each_entry_safe(entry, next, head, list)
3155 kfree(entry);
3156 }
3157
3158 static const struct iommu_ops amd_iommu_ops = {
3159 .capable = amd_iommu_capable,
3160 .domain_alloc = amd_iommu_domain_alloc,
3161 .domain_free = amd_iommu_domain_free,
3162 .attach_dev = amd_iommu_attach_device,
3163 .detach_dev = amd_iommu_detach_device,
3164 .map = amd_iommu_map,
3165 .unmap = amd_iommu_unmap,
3166 .map_sg = default_iommu_map_sg,
3167 .iova_to_phys = amd_iommu_iova_to_phys,
3168 .add_device = amd_iommu_add_device,
3169 .remove_device = amd_iommu_remove_device,
3170 .device_group = pci_device_group,
3171 .get_dm_regions = amd_iommu_get_dm_regions,
3172 .put_dm_regions = amd_iommu_put_dm_regions,
3173 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3174 };
3175
3176 /*****************************************************************************
3177 *
3178 * The next functions do a basic initialization of IOMMU for pass through
3179 * mode
3180 *
3181 * In passthrough mode the IOMMU is initialized and enabled but not used for
3182 * DMA-API translation.
3183 *
3184 *****************************************************************************/
3185
3186 /* IOMMUv2 specific functions */
amd_iommu_register_ppr_notifier(struct notifier_block * nb)3187 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3188 {
3189 return atomic_notifier_chain_register(&ppr_notifier, nb);
3190 }
3191 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3192
amd_iommu_unregister_ppr_notifier(struct notifier_block * nb)3193 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3194 {
3195 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3196 }
3197 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3198
amd_iommu_domain_direct_map(struct iommu_domain * dom)3199 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3200 {
3201 struct protection_domain *domain = to_pdomain(dom);
3202 unsigned long flags;
3203
3204 spin_lock_irqsave(&domain->lock, flags);
3205
3206 /* Update data structure */
3207 domain->mode = PAGE_MODE_NONE;
3208 domain->updated = true;
3209
3210 /* Make changes visible to IOMMUs */
3211 update_domain(domain);
3212
3213 /* Page-table is not visible to IOMMU anymore, so free it */
3214 free_pagetable(domain);
3215
3216 spin_unlock_irqrestore(&domain->lock, flags);
3217 }
3218 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3219
amd_iommu_domain_enable_v2(struct iommu_domain * dom,int pasids)3220 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3221 {
3222 struct protection_domain *domain = to_pdomain(dom);
3223 unsigned long flags;
3224 int levels, ret;
3225
3226 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3227 return -EINVAL;
3228
3229 /* Number of GCR3 table levels required */
3230 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3231 levels += 1;
3232
3233 if (levels > amd_iommu_max_glx_val)
3234 return -EINVAL;
3235
3236 spin_lock_irqsave(&domain->lock, flags);
3237
3238 /*
3239 * Save us all sanity checks whether devices already in the
3240 * domain support IOMMUv2. Just force that the domain has no
3241 * devices attached when it is switched into IOMMUv2 mode.
3242 */
3243 ret = -EBUSY;
3244 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3245 goto out;
3246
3247 ret = -ENOMEM;
3248 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3249 if (domain->gcr3_tbl == NULL)
3250 goto out;
3251
3252 domain->glx = levels;
3253 domain->flags |= PD_IOMMUV2_MASK;
3254 domain->updated = true;
3255
3256 update_domain(domain);
3257
3258 ret = 0;
3259
3260 out:
3261 spin_unlock_irqrestore(&domain->lock, flags);
3262
3263 return ret;
3264 }
3265 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3266
__flush_pasid(struct protection_domain * domain,int pasid,u64 address,bool size)3267 static int __flush_pasid(struct protection_domain *domain, int pasid,
3268 u64 address, bool size)
3269 {
3270 struct iommu_dev_data *dev_data;
3271 struct iommu_cmd cmd;
3272 int i, ret;
3273
3274 if (!(domain->flags & PD_IOMMUV2_MASK))
3275 return -EINVAL;
3276
3277 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3278
3279 /*
3280 * IOMMU TLB needs to be flushed before Device TLB to
3281 * prevent device TLB refill from IOMMU TLB
3282 */
3283 for (i = 0; i < amd_iommus_present; ++i) {
3284 if (domain->dev_iommu[i] == 0)
3285 continue;
3286
3287 ret = iommu_queue_command(amd_iommus[i], &cmd);
3288 if (ret != 0)
3289 goto out;
3290 }
3291
3292 /* Wait until IOMMU TLB flushes are complete */
3293 domain_flush_complete(domain);
3294
3295 /* Now flush device TLBs */
3296 list_for_each_entry(dev_data, &domain->dev_list, list) {
3297 struct amd_iommu *iommu;
3298 int qdep;
3299
3300 /*
3301 There might be non-IOMMUv2 capable devices in an IOMMUv2
3302 * domain.
3303 */
3304 if (!dev_data->ats.enabled)
3305 continue;
3306
3307 qdep = dev_data->ats.qdep;
3308 iommu = amd_iommu_rlookup_table[dev_data->devid];
3309
3310 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3311 qdep, address, size);
3312
3313 ret = iommu_queue_command(iommu, &cmd);
3314 if (ret != 0)
3315 goto out;
3316 }
3317
3318 /* Wait until all device TLBs are flushed */
3319 domain_flush_complete(domain);
3320
3321 ret = 0;
3322
3323 out:
3324
3325 return ret;
3326 }
3327
__amd_iommu_flush_page(struct protection_domain * domain,int pasid,u64 address)3328 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3329 u64 address)
3330 {
3331 INC_STATS_COUNTER(invalidate_iotlb);
3332
3333 return __flush_pasid(domain, pasid, address, false);
3334 }
3335
amd_iommu_flush_page(struct iommu_domain * dom,int pasid,u64 address)3336 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3337 u64 address)
3338 {
3339 struct protection_domain *domain = to_pdomain(dom);
3340 unsigned long flags;
3341 int ret;
3342
3343 spin_lock_irqsave(&domain->lock, flags);
3344 ret = __amd_iommu_flush_page(domain, pasid, address);
3345 spin_unlock_irqrestore(&domain->lock, flags);
3346
3347 return ret;
3348 }
3349 EXPORT_SYMBOL(amd_iommu_flush_page);
3350
__amd_iommu_flush_tlb(struct protection_domain * domain,int pasid)3351 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3352 {
3353 INC_STATS_COUNTER(invalidate_iotlb_all);
3354
3355 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3356 true);
3357 }
3358
amd_iommu_flush_tlb(struct iommu_domain * dom,int pasid)3359 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3360 {
3361 struct protection_domain *domain = to_pdomain(dom);
3362 unsigned long flags;
3363 int ret;
3364
3365 spin_lock_irqsave(&domain->lock, flags);
3366 ret = __amd_iommu_flush_tlb(domain, pasid);
3367 spin_unlock_irqrestore(&domain->lock, flags);
3368
3369 return ret;
3370 }
3371 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3372
__get_gcr3_pte(u64 * root,int level,int pasid,bool alloc)3373 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3374 {
3375 int index;
3376 u64 *pte;
3377
3378 while (true) {
3379
3380 index = (pasid >> (9 * level)) & 0x1ff;
3381 pte = &root[index];
3382
3383 if (level == 0)
3384 break;
3385
3386 if (!(*pte & GCR3_VALID)) {
3387 if (!alloc)
3388 return NULL;
3389
3390 root = (void *)get_zeroed_page(GFP_ATOMIC);
3391 if (root == NULL)
3392 return NULL;
3393
3394 *pte = __pa(root) | GCR3_VALID;
3395 }
3396
3397 root = __va(*pte & PAGE_MASK);
3398
3399 level -= 1;
3400 }
3401
3402 return pte;
3403 }
3404
__set_gcr3(struct protection_domain * domain,int pasid,unsigned long cr3)3405 static int __set_gcr3(struct protection_domain *domain, int pasid,
3406 unsigned long cr3)
3407 {
3408 u64 *pte;
3409
3410 if (domain->mode != PAGE_MODE_NONE)
3411 return -EINVAL;
3412
3413 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3414 if (pte == NULL)
3415 return -ENOMEM;
3416
3417 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3418
3419 return __amd_iommu_flush_tlb(domain, pasid);
3420 }
3421
__clear_gcr3(struct protection_domain * domain,int pasid)3422 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3423 {
3424 u64 *pte;
3425
3426 if (domain->mode != PAGE_MODE_NONE)
3427 return -EINVAL;
3428
3429 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3430 if (pte == NULL)
3431 return 0;
3432
3433 *pte = 0;
3434
3435 return __amd_iommu_flush_tlb(domain, pasid);
3436 }
3437
amd_iommu_domain_set_gcr3(struct iommu_domain * dom,int pasid,unsigned long cr3)3438 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3439 unsigned long cr3)
3440 {
3441 struct protection_domain *domain = to_pdomain(dom);
3442 unsigned long flags;
3443 int ret;
3444
3445 spin_lock_irqsave(&domain->lock, flags);
3446 ret = __set_gcr3(domain, pasid, cr3);
3447 spin_unlock_irqrestore(&domain->lock, flags);
3448
3449 return ret;
3450 }
3451 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3452
amd_iommu_domain_clear_gcr3(struct iommu_domain * dom,int pasid)3453 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3454 {
3455 struct protection_domain *domain = to_pdomain(dom);
3456 unsigned long flags;
3457 int ret;
3458
3459 spin_lock_irqsave(&domain->lock, flags);
3460 ret = __clear_gcr3(domain, pasid);
3461 spin_unlock_irqrestore(&domain->lock, flags);
3462
3463 return ret;
3464 }
3465 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3466
amd_iommu_complete_ppr(struct pci_dev * pdev,int pasid,int status,int tag)3467 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3468 int status, int tag)
3469 {
3470 struct iommu_dev_data *dev_data;
3471 struct amd_iommu *iommu;
3472 struct iommu_cmd cmd;
3473
3474 INC_STATS_COUNTER(complete_ppr);
3475
3476 dev_data = get_dev_data(&pdev->dev);
3477 iommu = amd_iommu_rlookup_table[dev_data->devid];
3478
3479 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3480 tag, dev_data->pri_tlp);
3481
3482 return iommu_queue_command(iommu, &cmd);
3483 }
3484 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3485
amd_iommu_get_v2_domain(struct pci_dev * pdev)3486 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3487 {
3488 struct protection_domain *pdomain;
3489
3490 pdomain = get_domain(&pdev->dev);
3491 if (IS_ERR(pdomain))
3492 return NULL;
3493
3494 /* Only return IOMMUv2 domains */
3495 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3496 return NULL;
3497
3498 return &pdomain->domain;
3499 }
3500 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3501
amd_iommu_enable_device_erratum(struct pci_dev * pdev,u32 erratum)3502 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3503 {
3504 struct iommu_dev_data *dev_data;
3505
3506 if (!amd_iommu_v2_supported())
3507 return;
3508
3509 dev_data = get_dev_data(&pdev->dev);
3510 dev_data->errata |= (1 << erratum);
3511 }
3512 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3513
amd_iommu_device_info(struct pci_dev * pdev,struct amd_iommu_device_info * info)3514 int amd_iommu_device_info(struct pci_dev *pdev,
3515 struct amd_iommu_device_info *info)
3516 {
3517 int max_pasids;
3518 int pos;
3519
3520 if (pdev == NULL || info == NULL)
3521 return -EINVAL;
3522
3523 if (!amd_iommu_v2_supported())
3524 return -EINVAL;
3525
3526 memset(info, 0, sizeof(*info));
3527
3528 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3529 if (pos)
3530 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3531
3532 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3533 if (pos)
3534 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3535
3536 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3537 if (pos) {
3538 int features;
3539
3540 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3541 max_pasids = min(max_pasids, (1 << 20));
3542
3543 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3544 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3545
3546 features = pci_pasid_features(pdev);
3547 if (features & PCI_PASID_CAP_EXEC)
3548 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3549 if (features & PCI_PASID_CAP_PRIV)
3550 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3551 }
3552
3553 return 0;
3554 }
3555 EXPORT_SYMBOL(amd_iommu_device_info);
3556
3557 #ifdef CONFIG_IRQ_REMAP
3558
3559 /*****************************************************************************
3560 *
3561 * Interrupt Remapping Implementation
3562 *
3563 *****************************************************************************/
3564
3565 union irte {
3566 u32 val;
3567 struct {
3568 u32 valid : 1,
3569 no_fault : 1,
3570 int_type : 3,
3571 rq_eoi : 1,
3572 dm : 1,
3573 rsvd_1 : 1,
3574 destination : 8,
3575 vector : 8,
3576 rsvd_2 : 8;
3577 } fields;
3578 };
3579
3580 struct irq_2_irte {
3581 u16 devid; /* Device ID for IRTE table */
3582 u16 index; /* Index into IRTE table*/
3583 };
3584
3585 struct amd_ir_data {
3586 struct irq_2_irte irq_2_irte;
3587 union irte irte_entry;
3588 union {
3589 struct msi_msg msi_entry;
3590 };
3591 };
3592
3593 static struct irq_chip amd_ir_chip;
3594
3595 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3596 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3597 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3598 #define DTE_IRQ_REMAP_ENABLE 1ULL
3599
set_dte_irq_entry(u16 devid,struct irq_remap_table * table)3600 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3601 {
3602 u64 dte;
3603
3604 dte = amd_iommu_dev_table[devid].data[2];
3605 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3606 dte |= virt_to_phys(table->table);
3607 dte |= DTE_IRQ_REMAP_INTCTL;
3608 dte |= DTE_IRQ_TABLE_LEN;
3609 dte |= DTE_IRQ_REMAP_ENABLE;
3610
3611 amd_iommu_dev_table[devid].data[2] = dte;
3612 }
3613
3614 #define IRTE_ALLOCATED (~1U)
3615
get_irq_table(u16 devid,bool ioapic)3616 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3617 {
3618 struct irq_remap_table *table = NULL;
3619 struct amd_iommu *iommu;
3620 unsigned long flags;
3621 u16 alias;
3622
3623 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3624
3625 iommu = amd_iommu_rlookup_table[devid];
3626 if (!iommu)
3627 goto out_unlock;
3628
3629 table = irq_lookup_table[devid];
3630 if (table)
3631 goto out;
3632
3633 alias = amd_iommu_alias_table[devid];
3634 table = irq_lookup_table[alias];
3635 if (table) {
3636 irq_lookup_table[devid] = table;
3637 set_dte_irq_entry(devid, table);
3638 iommu_flush_dte(iommu, devid);
3639 goto out;
3640 }
3641
3642 /* Nothing there yet, allocate new irq remapping table */
3643 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3644 if (!table)
3645 goto out;
3646
3647 /* Initialize table spin-lock */
3648 spin_lock_init(&table->lock);
3649
3650 if (ioapic)
3651 /* Keep the first 32 indexes free for IOAPIC interrupts */
3652 table->min_index = 32;
3653
3654 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3655 if (!table->table) {
3656 kfree(table);
3657 table = NULL;
3658 goto out;
3659 }
3660
3661 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3662
3663 if (ioapic) {
3664 int i;
3665
3666 for (i = 0; i < 32; ++i)
3667 table->table[i] = IRTE_ALLOCATED;
3668 }
3669
3670 irq_lookup_table[devid] = table;
3671 set_dte_irq_entry(devid, table);
3672 iommu_flush_dte(iommu, devid);
3673 if (devid != alias) {
3674 irq_lookup_table[alias] = table;
3675 set_dte_irq_entry(alias, table);
3676 iommu_flush_dte(iommu, alias);
3677 }
3678
3679 out:
3680 iommu_completion_wait(iommu);
3681
3682 out_unlock:
3683 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3684
3685 return table;
3686 }
3687
alloc_irq_index(u16 devid,int count)3688 static int alloc_irq_index(u16 devid, int count)
3689 {
3690 struct irq_remap_table *table;
3691 unsigned long flags;
3692 int index, c;
3693
3694 table = get_irq_table(devid, false);
3695 if (!table)
3696 return -ENODEV;
3697
3698 spin_lock_irqsave(&table->lock, flags);
3699
3700 /* Scan table for free entries */
3701 for (c = 0, index = table->min_index;
3702 index < MAX_IRQS_PER_TABLE;
3703 ++index) {
3704 if (table->table[index] == 0)
3705 c += 1;
3706 else
3707 c = 0;
3708
3709 if (c == count) {
3710 for (; c != 0; --c)
3711 table->table[index - c + 1] = IRTE_ALLOCATED;
3712
3713 index -= count - 1;
3714 goto out;
3715 }
3716 }
3717
3718 index = -ENOSPC;
3719
3720 out:
3721 spin_unlock_irqrestore(&table->lock, flags);
3722
3723 return index;
3724 }
3725
modify_irte(u16 devid,int index,union irte irte)3726 static int modify_irte(u16 devid, int index, union irte irte)
3727 {
3728 struct irq_remap_table *table;
3729 struct amd_iommu *iommu;
3730 unsigned long flags;
3731
3732 iommu = amd_iommu_rlookup_table[devid];
3733 if (iommu == NULL)
3734 return -EINVAL;
3735
3736 table = get_irq_table(devid, false);
3737 if (!table)
3738 return -ENOMEM;
3739
3740 spin_lock_irqsave(&table->lock, flags);
3741 table->table[index] = irte.val;
3742 spin_unlock_irqrestore(&table->lock, flags);
3743
3744 iommu_flush_irt(iommu, devid);
3745 iommu_completion_wait(iommu);
3746
3747 return 0;
3748 }
3749
free_irte(u16 devid,int index)3750 static void free_irte(u16 devid, int index)
3751 {
3752 struct irq_remap_table *table;
3753 struct amd_iommu *iommu;
3754 unsigned long flags;
3755
3756 iommu = amd_iommu_rlookup_table[devid];
3757 if (iommu == NULL)
3758 return;
3759
3760 table = get_irq_table(devid, false);
3761 if (!table)
3762 return;
3763
3764 spin_lock_irqsave(&table->lock, flags);
3765 table->table[index] = 0;
3766 spin_unlock_irqrestore(&table->lock, flags);
3767
3768 iommu_flush_irt(iommu, devid);
3769 iommu_completion_wait(iommu);
3770 }
3771
get_devid(struct irq_alloc_info * info)3772 static int get_devid(struct irq_alloc_info *info)
3773 {
3774 int devid = -1;
3775
3776 switch (info->type) {
3777 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3778 devid = get_ioapic_devid(info->ioapic_id);
3779 break;
3780 case X86_IRQ_ALLOC_TYPE_HPET:
3781 devid = get_hpet_devid(info->hpet_id);
3782 break;
3783 case X86_IRQ_ALLOC_TYPE_MSI:
3784 case X86_IRQ_ALLOC_TYPE_MSIX:
3785 devid = get_device_id(&info->msi_dev->dev);
3786 break;
3787 default:
3788 BUG_ON(1);
3789 break;
3790 }
3791
3792 return devid;
3793 }
3794
get_ir_irq_domain(struct irq_alloc_info * info)3795 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3796 {
3797 struct amd_iommu *iommu;
3798 int devid;
3799
3800 if (!info)
3801 return NULL;
3802
3803 devid = get_devid(info);
3804 if (devid >= 0) {
3805 iommu = amd_iommu_rlookup_table[devid];
3806 if (iommu)
3807 return iommu->ir_domain;
3808 }
3809
3810 return NULL;
3811 }
3812
get_irq_domain(struct irq_alloc_info * info)3813 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3814 {
3815 struct amd_iommu *iommu;
3816 int devid;
3817
3818 if (!info)
3819 return NULL;
3820
3821 switch (info->type) {
3822 case X86_IRQ_ALLOC_TYPE_MSI:
3823 case X86_IRQ_ALLOC_TYPE_MSIX:
3824 devid = get_device_id(&info->msi_dev->dev);
3825 if (devid >= 0) {
3826 iommu = amd_iommu_rlookup_table[devid];
3827 if (iommu)
3828 return iommu->msi_domain;
3829 }
3830 break;
3831 default:
3832 break;
3833 }
3834
3835 return NULL;
3836 }
3837
3838 struct irq_remap_ops amd_iommu_irq_ops = {
3839 .prepare = amd_iommu_prepare,
3840 .enable = amd_iommu_enable,
3841 .disable = amd_iommu_disable,
3842 .reenable = amd_iommu_reenable,
3843 .enable_faulting = amd_iommu_enable_faulting,
3844 .get_ir_irq_domain = get_ir_irq_domain,
3845 .get_irq_domain = get_irq_domain,
3846 };
3847
irq_remapping_prepare_irte(struct amd_ir_data * data,struct irq_cfg * irq_cfg,struct irq_alloc_info * info,int devid,int index,int sub_handle)3848 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3849 struct irq_cfg *irq_cfg,
3850 struct irq_alloc_info *info,
3851 int devid, int index, int sub_handle)
3852 {
3853 struct irq_2_irte *irte_info = &data->irq_2_irte;
3854 struct msi_msg *msg = &data->msi_entry;
3855 union irte *irte = &data->irte_entry;
3856 struct IO_APIC_route_entry *entry;
3857
3858 data->irq_2_irte.devid = devid;
3859 data->irq_2_irte.index = index + sub_handle;
3860
3861 /* Setup IRTE for IOMMU */
3862 irte->val = 0;
3863 irte->fields.vector = irq_cfg->vector;
3864 irte->fields.int_type = apic->irq_delivery_mode;
3865 irte->fields.destination = irq_cfg->dest_apicid;
3866 irte->fields.dm = apic->irq_dest_mode;
3867 irte->fields.valid = 1;
3868
3869 switch (info->type) {
3870 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3871 /* Setup IOAPIC entry */
3872 entry = info->ioapic_entry;
3873 info->ioapic_entry = NULL;
3874 memset(entry, 0, sizeof(*entry));
3875 entry->vector = index;
3876 entry->mask = 0;
3877 entry->trigger = info->ioapic_trigger;
3878 entry->polarity = info->ioapic_polarity;
3879 /* Mask level triggered irqs. */
3880 if (info->ioapic_trigger)
3881 entry->mask = 1;
3882 break;
3883
3884 case X86_IRQ_ALLOC_TYPE_HPET:
3885 case X86_IRQ_ALLOC_TYPE_MSI:
3886 case X86_IRQ_ALLOC_TYPE_MSIX:
3887 msg->address_hi = MSI_ADDR_BASE_HI;
3888 msg->address_lo = MSI_ADDR_BASE_LO;
3889 msg->data = irte_info->index;
3890 break;
3891
3892 default:
3893 BUG_ON(1);
3894 break;
3895 }
3896 }
3897
irq_remapping_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)3898 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3899 unsigned int nr_irqs, void *arg)
3900 {
3901 struct irq_alloc_info *info = arg;
3902 struct irq_data *irq_data;
3903 struct amd_ir_data *data;
3904 struct irq_cfg *cfg;
3905 int i, ret, devid;
3906 int index = -1;
3907
3908 if (!info)
3909 return -EINVAL;
3910 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
3911 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
3912 return -EINVAL;
3913
3914 /*
3915 * With IRQ remapping enabled, don't need contiguous CPU vectors
3916 * to support multiple MSI interrupts.
3917 */
3918 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
3919 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3920
3921 devid = get_devid(info);
3922 if (devid < 0)
3923 return -EINVAL;
3924
3925 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3926 if (ret < 0)
3927 return ret;
3928
3929 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3930 if (get_irq_table(devid, true))
3931 index = info->ioapic_pin;
3932 else
3933 ret = -ENOMEM;
3934 } else {
3935 index = alloc_irq_index(devid, nr_irqs);
3936 }
3937 if (index < 0) {
3938 pr_warn("Failed to allocate IRTE\n");
3939 goto out_free_parent;
3940 }
3941
3942 for (i = 0; i < nr_irqs; i++) {
3943 irq_data = irq_domain_get_irq_data(domain, virq + i);
3944 cfg = irqd_cfg(irq_data);
3945 if (!irq_data || !cfg) {
3946 ret = -EINVAL;
3947 goto out_free_data;
3948 }
3949
3950 ret = -ENOMEM;
3951 data = kzalloc(sizeof(*data), GFP_KERNEL);
3952 if (!data)
3953 goto out_free_data;
3954
3955 irq_data->hwirq = (devid << 16) + i;
3956 irq_data->chip_data = data;
3957 irq_data->chip = &amd_ir_chip;
3958 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3959 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3960 }
3961
3962 return 0;
3963
3964 out_free_data:
3965 for (i--; i >= 0; i--) {
3966 irq_data = irq_domain_get_irq_data(domain, virq + i);
3967 if (irq_data)
3968 kfree(irq_data->chip_data);
3969 }
3970 for (i = 0; i < nr_irqs; i++)
3971 free_irte(devid, index + i);
3972 out_free_parent:
3973 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3974 return ret;
3975 }
3976
irq_remapping_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)3977 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3978 unsigned int nr_irqs)
3979 {
3980 struct irq_2_irte *irte_info;
3981 struct irq_data *irq_data;
3982 struct amd_ir_data *data;
3983 int i;
3984
3985 for (i = 0; i < nr_irqs; i++) {
3986 irq_data = irq_domain_get_irq_data(domain, virq + i);
3987 if (irq_data && irq_data->chip_data) {
3988 data = irq_data->chip_data;
3989 irte_info = &data->irq_2_irte;
3990 free_irte(irte_info->devid, irte_info->index);
3991 kfree(data);
3992 }
3993 }
3994 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3995 }
3996
irq_remapping_activate(struct irq_domain * domain,struct irq_data * irq_data)3997 static void irq_remapping_activate(struct irq_domain *domain,
3998 struct irq_data *irq_data)
3999 {
4000 struct amd_ir_data *data = irq_data->chip_data;
4001 struct irq_2_irte *irte_info = &data->irq_2_irte;
4002
4003 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
4004 }
4005
irq_remapping_deactivate(struct irq_domain * domain,struct irq_data * irq_data)4006 static void irq_remapping_deactivate(struct irq_domain *domain,
4007 struct irq_data *irq_data)
4008 {
4009 struct amd_ir_data *data = irq_data->chip_data;
4010 struct irq_2_irte *irte_info = &data->irq_2_irte;
4011 union irte entry;
4012
4013 entry.val = 0;
4014 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
4015 }
4016
4017 static struct irq_domain_ops amd_ir_domain_ops = {
4018 .alloc = irq_remapping_alloc,
4019 .free = irq_remapping_free,
4020 .activate = irq_remapping_activate,
4021 .deactivate = irq_remapping_deactivate,
4022 };
4023
amd_ir_set_affinity(struct irq_data * data,const struct cpumask * mask,bool force)4024 static int amd_ir_set_affinity(struct irq_data *data,
4025 const struct cpumask *mask, bool force)
4026 {
4027 struct amd_ir_data *ir_data = data->chip_data;
4028 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4029 struct irq_cfg *cfg = irqd_cfg(data);
4030 struct irq_data *parent = data->parent_data;
4031 int ret;
4032
4033 ret = parent->chip->irq_set_affinity(parent, mask, force);
4034 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4035 return ret;
4036
4037 /*
4038 * Atomically updates the IRTE with the new destination, vector
4039 * and flushes the interrupt entry cache.
4040 */
4041 ir_data->irte_entry.fields.vector = cfg->vector;
4042 ir_data->irte_entry.fields.destination = cfg->dest_apicid;
4043 modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry);
4044
4045 /*
4046 * After this point, all the interrupts will start arriving
4047 * at the new destination. So, time to cleanup the previous
4048 * vector allocation.
4049 */
4050 send_cleanup_vector(cfg);
4051
4052 return IRQ_SET_MASK_OK_DONE;
4053 }
4054
ir_compose_msi_msg(struct irq_data * irq_data,struct msi_msg * msg)4055 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4056 {
4057 struct amd_ir_data *ir_data = irq_data->chip_data;
4058
4059 *msg = ir_data->msi_entry;
4060 }
4061
4062 static struct irq_chip amd_ir_chip = {
4063 .irq_ack = ir_ack_apic_edge,
4064 .irq_set_affinity = amd_ir_set_affinity,
4065 .irq_compose_msi_msg = ir_compose_msi_msg,
4066 };
4067
amd_iommu_create_irq_domain(struct amd_iommu * iommu)4068 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4069 {
4070 iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu);
4071 if (!iommu->ir_domain)
4072 return -ENOMEM;
4073
4074 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4075 iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
4076
4077 return 0;
4078 }
4079 #endif
4080