1/*
2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#include "ctxgf100.h"
23#include "gf100.h"
24
25#include <subdev/mc.h>
26
27static void
28gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info)
29{
30	struct nvkm_device *device = gr->base.engine.subdev.device;
31	const struct gf100_grctx_func *grctx = gr->func->grctx;
32	int idle_timeout_save;
33	int i;
34
35	gf100_gr_mmio(gr, gr->fuc_sw_ctx);
36
37	gf100_gr_wait_idle(gr);
38
39	idle_timeout_save = nvkm_rd32(device, 0x404154);
40	nvkm_wr32(device, 0x404154, 0x00000000);
41
42	grctx->attrib(info);
43
44	grctx->unkn(gr);
45
46	gf100_grctx_generate_tpcid(gr);
47	gf100_grctx_generate_r406028(gr);
48	gk104_grctx_generate_r418bb8(gr);
49	gf100_grctx_generate_r406800(gr);
50
51	for (i = 0; i < 8; i++)
52		nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000);
53
54	nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr);
55
56	gk104_grctx_generate_rop_active_fbps(gr);
57
58	nvkm_mask(device, 0x5044b0, 0x8000000, 0x8000000);
59
60	gf100_gr_wait_idle(gr);
61
62	nvkm_wr32(device, 0x404154, idle_timeout_save);
63	gf100_gr_wait_idle(gr);
64
65	gf100_gr_mthd(gr, gr->fuc_method);
66	gf100_gr_wait_idle(gr);
67
68	gf100_gr_icmd(gr, gr->fuc_bundle);
69	grctx->pagepool(info);
70	grctx->bundle(info);
71}
72
73const struct gf100_grctx_func
74gk20a_grctx = {
75	.main  = gk20a_grctx_generate_main,
76	.unkn  = gk104_grctx_generate_unkn,
77	.bundle = gk104_grctx_generate_bundle,
78	.bundle_size = 0x1800,
79	.bundle_min_gpm_fifo_depth = 0x62,
80	.bundle_token_limit = 0x100,
81	.pagepool = gk104_grctx_generate_pagepool,
82	.pagepool_size = 0x8000,
83	.attrib = gf117_grctx_generate_attrib,
84	.attrib_nr_max = 0x240,
85	.attrib_nr = 0x240,
86	.alpha_nr_max = 0x648 + (0x648 / 2),
87	.alpha_nr = 0x648,
88};
89