1/*
2 * Copyright (C) 2013-2014 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program.  If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "adreno_gpu.h"
21
22#if defined(DOWNSTREAM_CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF)
23#  include <mach/kgsl.h>
24#endif
25
26#define ANY_ID 0xff
27
28bool hang_debug = false;
29MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
30module_param_named(hang_debug, hang_debug, bool, 0600);
31
32struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
33struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
34
35static const struct adreno_info gpulist[] = {
36	{
37		.rev   = ADRENO_REV(3, 0, 5, ANY_ID),
38		.revn  = 305,
39		.name  = "A305",
40		.pm4fw = "a300_pm4.fw",
41		.pfpfw = "a300_pfp.fw",
42		.gmem  = SZ_256K,
43		.init  = a3xx_gpu_init,
44	}, {
45		.rev   = ADRENO_REV(3, 0, 6, 0),
46		.revn  = 307,        /* because a305c is revn==306 */
47		.name  = "A306",
48		.pm4fw = "a300_pm4.fw",
49		.pfpfw = "a300_pfp.fw",
50		.gmem  = SZ_128K,
51		.init  = a3xx_gpu_init,
52	}, {
53		.rev   = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
54		.revn  = 320,
55		.name  = "A320",
56		.pm4fw = "a300_pm4.fw",
57		.pfpfw = "a300_pfp.fw",
58		.gmem  = SZ_512K,
59		.init  = a3xx_gpu_init,
60	}, {
61		.rev   = ADRENO_REV(3, 3, 0, ANY_ID),
62		.revn  = 330,
63		.name  = "A330",
64		.pm4fw = "a330_pm4.fw",
65		.pfpfw = "a330_pfp.fw",
66		.gmem  = SZ_1M,
67		.init  = a3xx_gpu_init,
68	}, {
69		.rev   = ADRENO_REV(4, 2, 0, ANY_ID),
70		.revn  = 420,
71		.name  = "A420",
72		.pm4fw = "a420_pm4.fw",
73		.pfpfw = "a420_pfp.fw",
74		.gmem  = (SZ_1M + SZ_512K),
75		.init  = a4xx_gpu_init,
76	},
77};
78
79MODULE_FIRMWARE("a300_pm4.fw");
80MODULE_FIRMWARE("a300_pfp.fw");
81MODULE_FIRMWARE("a330_pm4.fw");
82MODULE_FIRMWARE("a330_pfp.fw");
83MODULE_FIRMWARE("a420_pm4.fw");
84MODULE_FIRMWARE("a420_pfp.fw");
85
86static inline bool _rev_match(uint8_t entry, uint8_t id)
87{
88	return (entry == ANY_ID) || (entry == id);
89}
90
91const struct adreno_info *adreno_info(struct adreno_rev rev)
92{
93	int i;
94
95	/* identify gpu: */
96	for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
97		const struct adreno_info *info = &gpulist[i];
98		if (_rev_match(info->rev.core, rev.core) &&
99				_rev_match(info->rev.major, rev.major) &&
100				_rev_match(info->rev.minor, rev.minor) &&
101				_rev_match(info->rev.patchid, rev.patchid))
102			return info;
103	}
104
105	return NULL;
106}
107
108struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
109{
110	struct msm_drm_private *priv = dev->dev_private;
111	struct platform_device *pdev = priv->gpu_pdev;
112	struct adreno_platform_config *config;
113	struct adreno_rev rev;
114	const struct adreno_info *info;
115	struct msm_gpu *gpu = NULL;
116
117	if (!pdev) {
118		dev_err(dev->dev, "no adreno device\n");
119		return NULL;
120	}
121
122	config = pdev->dev.platform_data;
123	rev = config->rev;
124	info = adreno_info(config->rev);
125
126	if (!info) {
127		dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
128				rev.core, rev.major, rev.minor, rev.patchid);
129		return NULL;
130	}
131
132	DBG("Found GPU: %u.%u.%u.%u",  rev.core, rev.major,
133			rev.minor, rev.patchid);
134
135	gpu = info->init(dev);
136	if (IS_ERR(gpu)) {
137		dev_warn(dev->dev, "failed to load adreno gpu\n");
138		gpu = NULL;
139		/* not fatal */
140	}
141
142	if (gpu) {
143		int ret;
144		mutex_lock(&dev->struct_mutex);
145		gpu->funcs->pm_resume(gpu);
146		mutex_unlock(&dev->struct_mutex);
147		ret = gpu->funcs->hw_init(gpu);
148		if (ret) {
149			dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
150			gpu->funcs->destroy(gpu);
151			gpu = NULL;
152		} else {
153			/* give inactive pm a chance to kick in: */
154			msm_gpu_retire(gpu);
155		}
156	}
157
158	return gpu;
159}
160
161static void set_gpu_pdev(struct drm_device *dev,
162		struct platform_device *pdev)
163{
164	struct msm_drm_private *priv = dev->dev_private;
165	priv->gpu_pdev = pdev;
166}
167
168static int adreno_bind(struct device *dev, struct device *master, void *data)
169{
170	static struct adreno_platform_config config = {};
171#ifdef CONFIG_OF
172	struct device_node *child, *node = dev->of_node;
173	u32 val;
174	int ret;
175
176	ret = of_property_read_u32(node, "qcom,chipid", &val);
177	if (ret) {
178		dev_err(dev, "could not find chipid: %d\n", ret);
179		return ret;
180	}
181
182	config.rev = ADRENO_REV((val >> 24) & 0xff,
183			(val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
184
185	/* find clock rates: */
186	config.fast_rate = 0;
187	config.slow_rate = ~0;
188	for_each_child_of_node(node, child) {
189		if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
190			struct device_node *pwrlvl;
191			for_each_child_of_node(child, pwrlvl) {
192				ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
193				if (ret) {
194					dev_err(dev, "could not find gpu-freq: %d\n", ret);
195					return ret;
196				}
197				config.fast_rate = max(config.fast_rate, val);
198				config.slow_rate = min(config.slow_rate, val);
199			}
200		}
201	}
202
203	if (!config.fast_rate) {
204		dev_err(dev, "could not find clk rates\n");
205		return -ENXIO;
206	}
207
208#else
209	struct kgsl_device_platform_data *pdata = dev->platform_data;
210	uint32_t version = socinfo_get_version();
211	if (cpu_is_apq8064ab()) {
212		config.fast_rate = 450000000;
213		config.slow_rate = 27000000;
214		config.bus_freq  = 4;
215		config.rev = ADRENO_REV(3, 2, 1, 0);
216	} else if (cpu_is_apq8064()) {
217		config.fast_rate = 400000000;
218		config.slow_rate = 27000000;
219		config.bus_freq  = 4;
220
221		if (SOCINFO_VERSION_MAJOR(version) == 2)
222			config.rev = ADRENO_REV(3, 2, 0, 2);
223		else if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
224				(SOCINFO_VERSION_MINOR(version) == 1))
225			config.rev = ADRENO_REV(3, 2, 0, 1);
226		else
227			config.rev = ADRENO_REV(3, 2, 0, 0);
228
229	} else if (cpu_is_msm8960ab()) {
230		config.fast_rate = 400000000;
231		config.slow_rate = 320000000;
232		config.bus_freq  = 4;
233
234		if (SOCINFO_VERSION_MINOR(version) == 0)
235			config.rev = ADRENO_REV(3, 2, 1, 0);
236		else
237			config.rev = ADRENO_REV(3, 2, 1, 1);
238
239	} else if (cpu_is_msm8930()) {
240		config.fast_rate = 400000000;
241		config.slow_rate = 27000000;
242		config.bus_freq  = 3;
243
244		if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
245			(SOCINFO_VERSION_MINOR(version) == 2))
246			config.rev = ADRENO_REV(3, 0, 5, 2);
247		else
248			config.rev = ADRENO_REV(3, 0, 5, 0);
249
250	}
251#  ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
252	config.bus_scale_table = pdata->bus_scale_table;
253#  endif
254#endif
255	dev->platform_data = &config;
256	set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
257	return 0;
258}
259
260static void adreno_unbind(struct device *dev, struct device *master,
261		void *data)
262{
263	set_gpu_pdev(dev_get_drvdata(master), NULL);
264}
265
266static const struct component_ops a3xx_ops = {
267		.bind   = adreno_bind,
268		.unbind = adreno_unbind,
269};
270
271static int adreno_probe(struct platform_device *pdev)
272{
273	return component_add(&pdev->dev, &a3xx_ops);
274}
275
276static int adreno_remove(struct platform_device *pdev)
277{
278	component_del(&pdev->dev, &a3xx_ops);
279	return 0;
280}
281
282static const struct of_device_id dt_match[] = {
283	{ .compatible = "qcom,adreno-3xx" },
284	/* for backwards compat w/ downstream kgsl DT files: */
285	{ .compatible = "qcom,kgsl-3d0" },
286	{}
287};
288
289static struct platform_driver adreno_driver = {
290	.probe = adreno_probe,
291	.remove = adreno_remove,
292	.driver = {
293		.name = "adreno",
294		.of_match_table = dt_match,
295	},
296};
297
298void __init adreno_register(void)
299{
300	platform_driver_register(&adreno_driver);
301}
302
303void __exit adreno_unregister(void)
304{
305	platform_driver_unregister(&adreno_driver);
306}
307