1#ifndef A4XX_XML 2#define A4XX_XML 3 4/* Autogenerated file, DO NOT EDIT manually! 5 6This file was generated by the rules-ng-ng headergen tool in this git repository: 7http://github.com/freedreno/envytools/ 8git clone https://github.com/freedreno/envytools.git 9 10The rules-ng-ng source files this header was generated from are: 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12) 18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) 19 20Copyright (C) 2013-2015 by the following authors: 21- Rob Clark <robdclark@gmail.com> (robclark) 22 23Permission is hereby granted, free of charge, to any person obtaining 24a copy of this software and associated documentation files (the 25"Software"), to deal in the Software without restriction, including 26without limitation the rights to use, copy, modify, merge, publish, 27distribute, sublicense, and/or sell copies of the Software, and to 28permit persons to whom the Software is furnished to do so, subject to 29the following conditions: 30 31The above copyright notice and this permission notice (including the 32next paragraph) shall be included in all copies or substantial 33portions of the Software. 34 35THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 37MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 38IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 39LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 40OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 41WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 42*/ 43 44 45enum a4xx_color_fmt { 46 RB4_A8_UNORM = 1, 47 RB4_R8_UNORM = 2, 48 RB4_R4G4B4A4_UNORM = 8, 49 RB4_R5G5B5A1_UNORM = 10, 50 RB4_R5G6R5_UNORM = 14, 51 RB4_R8G8_UNORM = 15, 52 RB4_R8G8_SNORM = 16, 53 RB4_R8G8_UINT = 17, 54 RB4_R8G8_SINT = 18, 55 RB4_R16_FLOAT = 21, 56 RB4_R16_UINT = 22, 57 RB4_R16_SINT = 23, 58 RB4_R8G8B8_UNORM = 25, 59 RB4_R8G8B8A8_UNORM = 26, 60 RB4_R8G8B8A8_SNORM = 28, 61 RB4_R8G8B8A8_UINT = 29, 62 RB4_R8G8B8A8_SINT = 30, 63 RB4_R10G10B10A2_UNORM = 31, 64 RB4_R10G10B10A2_UINT = 34, 65 RB4_R11G11B10_FLOAT = 39, 66 RB4_R16G16_FLOAT = 42, 67 RB4_R16G16_UINT = 43, 68 RB4_R16G16_SINT = 44, 69 RB4_R32_FLOAT = 45, 70 RB4_R32_UINT = 46, 71 RB4_R32_SINT = 47, 72 RB4_R16G16B16A16_FLOAT = 54, 73 RB4_R16G16B16A16_UINT = 55, 74 RB4_R16G16B16A16_SINT = 56, 75 RB4_R32G32_FLOAT = 57, 76 RB4_R32G32_UINT = 58, 77 RB4_R32G32_SINT = 59, 78 RB4_R32G32B32A32_FLOAT = 60, 79 RB4_R32G32B32A32_UINT = 61, 80 RB4_R32G32B32A32_SINT = 62, 81}; 82 83enum a4xx_tile_mode { 84 TILE4_LINEAR = 0, 85 TILE4_3 = 3, 86}; 87 88enum a4xx_rb_blend_opcode { 89 BLEND_DST_PLUS_SRC = 0, 90 BLEND_SRC_MINUS_DST = 1, 91 BLEND_DST_MINUS_SRC = 2, 92 BLEND_MIN_DST_SRC = 3, 93 BLEND_MAX_DST_SRC = 4, 94}; 95 96enum a4xx_vtx_fmt { 97 VFMT4_32_FLOAT = 1, 98 VFMT4_32_32_FLOAT = 2, 99 VFMT4_32_32_32_FLOAT = 3, 100 VFMT4_32_32_32_32_FLOAT = 4, 101 VFMT4_16_FLOAT = 5, 102 VFMT4_16_16_FLOAT = 6, 103 VFMT4_16_16_16_FLOAT = 7, 104 VFMT4_16_16_16_16_FLOAT = 8, 105 VFMT4_32_FIXED = 9, 106 VFMT4_32_32_FIXED = 10, 107 VFMT4_32_32_32_FIXED = 11, 108 VFMT4_32_32_32_32_FIXED = 12, 109 VFMT4_16_SINT = 16, 110 VFMT4_16_16_SINT = 17, 111 VFMT4_16_16_16_SINT = 18, 112 VFMT4_16_16_16_16_SINT = 19, 113 VFMT4_16_UINT = 20, 114 VFMT4_16_16_UINT = 21, 115 VFMT4_16_16_16_UINT = 22, 116 VFMT4_16_16_16_16_UINT = 23, 117 VFMT4_16_SNORM = 24, 118 VFMT4_16_16_SNORM = 25, 119 VFMT4_16_16_16_SNORM = 26, 120 VFMT4_16_16_16_16_SNORM = 27, 121 VFMT4_16_UNORM = 28, 122 VFMT4_16_16_UNORM = 29, 123 VFMT4_16_16_16_UNORM = 30, 124 VFMT4_16_16_16_16_UNORM = 31, 125 VFMT4_32_UINT = 32, 126 VFMT4_32_32_UINT = 33, 127 VFMT4_32_32_32_UINT = 34, 128 VFMT4_32_32_32_32_UINT = 35, 129 VFMT4_32_SINT = 36, 130 VFMT4_32_32_SINT = 37, 131 VFMT4_32_32_32_SINT = 38, 132 VFMT4_32_32_32_32_SINT = 39, 133 VFMT4_8_UINT = 40, 134 VFMT4_8_8_UINT = 41, 135 VFMT4_8_8_8_UINT = 42, 136 VFMT4_8_8_8_8_UINT = 43, 137 VFMT4_8_UNORM = 44, 138 VFMT4_8_8_UNORM = 45, 139 VFMT4_8_8_8_UNORM = 46, 140 VFMT4_8_8_8_8_UNORM = 47, 141 VFMT4_8_SINT = 48, 142 VFMT4_8_8_SINT = 49, 143 VFMT4_8_8_8_SINT = 50, 144 VFMT4_8_8_8_8_SINT = 51, 145 VFMT4_8_SNORM = 52, 146 VFMT4_8_8_SNORM = 53, 147 VFMT4_8_8_8_SNORM = 54, 148 VFMT4_8_8_8_8_SNORM = 55, 149 VFMT4_10_10_10_2_UINT = 60, 150 VFMT4_10_10_10_2_UNORM = 61, 151 VFMT4_10_10_10_2_SINT = 62, 152 VFMT4_10_10_10_2_SNORM = 63, 153}; 154 155enum a4xx_tex_fmt { 156 TFMT4_5_6_5_UNORM = 11, 157 TFMT4_5_5_5_1_UNORM = 10, 158 TFMT4_4_4_4_4_UNORM = 8, 159 TFMT4_X8Z24_UNORM = 71, 160 TFMT4_10_10_10_2_UNORM = 33, 161 TFMT4_A8_UNORM = 3, 162 TFMT4_L8_A8_UNORM = 13, 163 TFMT4_8_UNORM = 4, 164 TFMT4_8_8_UNORM = 14, 165 TFMT4_8_8_8_8_UNORM = 28, 166 TFMT4_8_SNORM = 5, 167 TFMT4_8_8_SNORM = 15, 168 TFMT4_8_8_8_8_SNORM = 29, 169 TFMT4_8_UINT = 6, 170 TFMT4_8_8_UINT = 16, 171 TFMT4_8_8_8_8_UINT = 30, 172 TFMT4_8_SINT = 7, 173 TFMT4_8_8_SINT = 17, 174 TFMT4_8_8_8_8_SINT = 31, 175 TFMT4_16_UINT = 21, 176 TFMT4_16_16_UINT = 41, 177 TFMT4_16_16_16_16_UINT = 54, 178 TFMT4_16_SINT = 22, 179 TFMT4_16_16_SINT = 42, 180 TFMT4_16_16_16_16_SINT = 55, 181 TFMT4_32_UINT = 44, 182 TFMT4_32_32_UINT = 57, 183 TFMT4_32_32_32_32_UINT = 64, 184 TFMT4_32_SINT = 45, 185 TFMT4_32_32_SINT = 58, 186 TFMT4_32_32_32_32_SINT = 65, 187 TFMT4_16_FLOAT = 20, 188 TFMT4_16_16_FLOAT = 40, 189 TFMT4_16_16_16_16_FLOAT = 53, 190 TFMT4_32_FLOAT = 43, 191 TFMT4_32_32_FLOAT = 56, 192 TFMT4_32_32_32_32_FLOAT = 63, 193 TFMT4_9_9_9_E5_FLOAT = 32, 194 TFMT4_11_11_10_FLOAT = 37, 195 TFMT4_ATC_RGB = 100, 196 TFMT4_ATC_RGBA_EXPLICIT = 101, 197 TFMT4_ATC_RGBA_INTERPOLATED = 102, 198 TFMT4_ETC2_RG11_UNORM = 103, 199 TFMT4_ETC2_RG11_SNORM = 104, 200 TFMT4_ETC2_R11_UNORM = 105, 201 TFMT4_ETC2_R11_SNORM = 106, 202 TFMT4_ETC1 = 107, 203 TFMT4_ETC2_RGB8 = 108, 204 TFMT4_ETC2_RGBA8 = 109, 205 TFMT4_ETC2_RGB8A1 = 110, 206 TFMT4_ASTC_4x4 = 111, 207 TFMT4_ASTC_5x4 = 112, 208 TFMT4_ASTC_5x5 = 113, 209 TFMT4_ASTC_6x5 = 114, 210 TFMT4_ASTC_6x6 = 115, 211 TFMT4_ASTC_8x5 = 116, 212 TFMT4_ASTC_8x6 = 117, 213 TFMT4_ASTC_8x8 = 118, 214 TFMT4_ASTC_10x5 = 119, 215 TFMT4_ASTC_10x6 = 120, 216 TFMT4_ASTC_10x8 = 121, 217 TFMT4_ASTC_10x10 = 122, 218 TFMT4_ASTC_12x10 = 123, 219 TFMT4_ASTC_12x12 = 124, 220}; 221 222enum a4xx_tex_fetchsize { 223 TFETCH4_1_BYTE = 0, 224 TFETCH4_2_BYTE = 1, 225 TFETCH4_4_BYTE = 2, 226 TFETCH4_8_BYTE = 3, 227 TFETCH4_16_BYTE = 4, 228}; 229 230enum a4xx_depth_format { 231 DEPTH4_NONE = 0, 232 DEPTH4_16 = 1, 233 DEPTH4_24_8 = 2, 234 DEPTH4_32 = 3, 235}; 236 237enum a4xx_tess_spacing { 238 EQUAL_SPACING = 0, 239 ODD_SPACING = 2, 240 EVEN_SPACING = 3, 241}; 242 243enum a4xx_tex_filter { 244 A4XX_TEX_NEAREST = 0, 245 A4XX_TEX_LINEAR = 1, 246 A4XX_TEX_ANISO = 2, 247}; 248 249enum a4xx_tex_clamp { 250 A4XX_TEX_REPEAT = 0, 251 A4XX_TEX_CLAMP_TO_EDGE = 1, 252 A4XX_TEX_MIRROR_REPEAT = 2, 253 A4XX_TEX_CLAMP_TO_BORDER = 3, 254 A4XX_TEX_MIRROR_CLAMP = 4, 255}; 256 257enum a4xx_tex_aniso { 258 A4XX_TEX_ANISO_1 = 0, 259 A4XX_TEX_ANISO_2 = 1, 260 A4XX_TEX_ANISO_4 = 2, 261 A4XX_TEX_ANISO_8 = 3, 262 A4XX_TEX_ANISO_16 = 4, 263}; 264 265enum a4xx_tex_swiz { 266 A4XX_TEX_X = 0, 267 A4XX_TEX_Y = 1, 268 A4XX_TEX_Z = 2, 269 A4XX_TEX_W = 3, 270 A4XX_TEX_ZERO = 4, 271 A4XX_TEX_ONE = 5, 272}; 273 274enum a4xx_tex_type { 275 A4XX_TEX_1D = 0, 276 A4XX_TEX_2D = 1, 277 A4XX_TEX_CUBE = 2, 278 A4XX_TEX_3D = 3, 279}; 280 281#define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000 282#define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20 283static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) 284{ 285 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; 286} 287#define A4XX_INT0_RBBM_GPU_IDLE 0x00000001 288#define A4XX_INT0_RBBM_AHB_ERROR 0x00000002 289#define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004 290#define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 291#define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 292#define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 293#define A4XX_INT0_VFD_ERROR 0x00000040 294#define A4XX_INT0_CP_SW_INT 0x00000080 295#define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 296#define A4XX_INT0_CP_OPCODE_ERROR 0x00000200 297#define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 298#define A4XX_INT0_CP_HW_FAULT 0x00000800 299#define A4XX_INT0_CP_DMA 0x00001000 300#define A4XX_INT0_CP_IB2_INT 0x00002000 301#define A4XX_INT0_CP_IB1_INT 0x00004000 302#define A4XX_INT0_CP_RB_INT 0x00008000 303#define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 304#define A4XX_INT0_CP_RB_DONE_TS 0x00020000 305#define A4XX_INT0_CP_VS_DONE_TS 0x00040000 306#define A4XX_INT0_CP_PS_DONE_TS 0x00080000 307#define A4XX_INT0_CACHE_FLUSH_TS 0x00100000 308#define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000 309#define A4XX_INT0_MISC_HANG_DETECT 0x01000000 310#define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000 311#define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0 312 313#define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7 314 315#define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8 316 317#define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9 318 319#define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca 320 321#define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb 322 323#define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc 324 325#define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd 326 327#define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce 328 329#define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2 330 331#define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 332#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 333#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 334static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 335{ 336 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 337} 338#define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000 339#define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16 340static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 341{ 342 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 343} 344 345#define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc 346 347#define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd 348 349#define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce 350 351#define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf 352 353#define REG_A4XX_RB_MODE_CONTROL 0x000020a0 354#define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f 355#define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0 356static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) 357{ 358 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; 359} 360#define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00 361#define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8 362static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) 363{ 364 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; 365} 366 367#define REG_A4XX_RB_RENDER_CONTROL 0x000020a1 368#define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001 369#define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020 370 371#define REG_A4XX_RB_MSAA_CONTROL 0x000020a2 372#define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000 373#define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000 374#define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13 375static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) 376{ 377 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK; 378} 379 380#define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3 381#define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001 382#define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002 383#define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004 384#define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008 385#define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010 386#define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020 387#define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040 388#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380 389#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7 390static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) 391{ 392 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK; 393} 394#define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800 395#define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000 396 397static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 398 399static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } 400#define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 401#define A4XX_RB_MRT_CONTROL_BLEND 0x00000010 402#define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020 403#define A4XX_RB_MRT_CONTROL_FASTCLEAR 0x00000400 404#define A4XX_RB_MRT_CONTROL_B11 0x00000800 405#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 406#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 407static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 408{ 409 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 410} 411 412static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } 413#define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 414#define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 415static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val) 416{ 417 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 418} 419#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 420#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 421static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val) 422{ 423 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 424} 425#define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600 426#define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9 427static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 428{ 429 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK; 430} 431#define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800 432#define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11 433static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 434{ 435 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 436} 437#define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000 438#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000 439#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14 440static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 441{ 442 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 443} 444 445static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } 446 447static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } 448#define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8 449#define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3 450static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val) 451{ 452 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK; 453} 454 455static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } 456#define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 457#define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 458static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 459{ 460 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 461} 462#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 463#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 464static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) 465{ 466 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 467} 468#define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 469#define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 470static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 471{ 472 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 473} 474#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 475#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 476static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 477{ 478 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 479} 480#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 481#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 482static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val) 483{ 484 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 485} 486#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 487#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 488static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 489{ 490 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 491} 492 493#define REG_A4XX_RB_BLEND_RED 0x000020f3 494#define A4XX_RB_BLEND_RED_UINT__MASK 0x00007fff 495#define A4XX_RB_BLEND_RED_UINT__SHIFT 0 496static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val) 497{ 498 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK; 499} 500#define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 501#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16 502static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val) 503{ 504 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK; 505} 506 507#define REG_A4XX_RB_BLEND_GREEN 0x000020f4 508#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x00007fff 509#define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0 510static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val) 511{ 512 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK; 513} 514#define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 515#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 516static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val) 517{ 518 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK; 519} 520 521#define REG_A4XX_RB_BLEND_BLUE 0x000020f5 522#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x00007fff 523#define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0 524static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val) 525{ 526 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK; 527} 528#define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 529#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 530static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val) 531{ 532 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK; 533} 534 535#define REG_A4XX_RB_BLEND_ALPHA 0x000020f6 536#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x00007fff 537#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0 538static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val) 539{ 540 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK; 541} 542#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 543#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 544static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val) 545{ 546 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK; 547} 548 549#define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8 550#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff 551#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 552static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) 553{ 554 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; 555} 556#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 557#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 558#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 559static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 560{ 561 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; 562} 563 564#define REG_A4XX_RB_FS_OUTPUT 0x000020f9 565#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff 566#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0 567static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val) 568{ 569 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK; 570} 571#define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100 572#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000 573#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16 574static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) 575{ 576 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK; 577} 578 579#define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa 580#define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 581#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc 582#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2 583static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) 584{ 585 return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK; 586} 587 588#define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb 589#define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f 590#define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 591static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) 592{ 593 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK; 594} 595#define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 596#define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 597static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) 598{ 599 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK; 600} 601#define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 602#define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 603static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) 604{ 605 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK; 606} 607#define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 608#define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 609static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) 610{ 611 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK; 612} 613#define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 614#define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 615static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) 616{ 617 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK; 618} 619#define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 620#define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 621static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) 622{ 623 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK; 624} 625#define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 626#define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 627static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) 628{ 629 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK; 630} 631#define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 632#define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 633static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) 634{ 635 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK; 636} 637 638#define REG_A4XX_RB_COPY_CONTROL 0x000020fc 639#define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 640#define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 641static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 642{ 643 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 644} 645#define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 646#define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4 647static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 648{ 649 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK; 650} 651#define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 652#define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 653static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 654{ 655 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 656} 657#define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 658#define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 659static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 660{ 661 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 662} 663 664#define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd 665#define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0 666#define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5 667static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 668{ 669 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; 670} 671 672#define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe 673#define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 674#define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 675static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 676{ 677 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; 678} 679 680#define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff 681#define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 682#define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 683static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val) 684{ 685 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK; 686} 687#define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 688#define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 689static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 690{ 691 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK; 692} 693#define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 694#define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 695static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 696{ 697 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 698} 699#define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 700#define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 701static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 702{ 703 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 704} 705#define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 706#define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 707static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 708{ 709 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 710} 711#define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000 712#define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24 713static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val) 714{ 715 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK; 716} 717 718#define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100 719#define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f 720#define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0 721static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val) 722{ 723 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK; 724} 725#define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020 726 727#define REG_A4XX_RB_DEPTH_CONTROL 0x00002101 728#define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 729#define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 730#define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 731#define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 732#define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 733static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 734{ 735 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 736} 737#define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 738#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000 739#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 740 741#define REG_A4XX_RB_DEPTH_CLEAR 0x00002102 742 743#define REG_A4XX_RB_DEPTH_INFO 0x00002103 744#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 745#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 746static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val) 747{ 748 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 749} 750#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 751#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 752static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 753{ 754 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 755} 756 757#define REG_A4XX_RB_DEPTH_PITCH 0x00002104 758#define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff 759#define A4XX_RB_DEPTH_PITCH__SHIFT 0 760static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) 761{ 762 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; 763} 764 765#define REG_A4XX_RB_DEPTH_PITCH2 0x00002105 766#define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff 767#define A4XX_RB_DEPTH_PITCH2__SHIFT 0 768static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) 769{ 770 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; 771} 772 773#define REG_A4XX_RB_STENCIL_CONTROL 0x00002106 774#define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 775#define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 776#define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 777#define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 778#define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 779static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 780{ 781 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK; 782} 783#define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 784#define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 785static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 786{ 787 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK; 788} 789#define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 790#define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 791static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 792{ 793 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK; 794} 795#define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 796#define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 797static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 798{ 799 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 800} 801#define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 802#define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 803static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 804{ 805 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 806} 807#define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 808#define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 809static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 810{ 811 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 812} 813#define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 814#define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 815static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 816{ 817 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 818} 819#define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 820#define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 821static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 822{ 823 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 824} 825 826#define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107 827#define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001 828 829#define REG_A4XX_RB_STENCIL_INFO 0x00002108 830#define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 831#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000 832#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12 833static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) 834{ 835 return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; 836} 837 838#define REG_A4XX_RB_STENCIL_PITCH 0x00002109 839#define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff 840#define A4XX_RB_STENCIL_PITCH__SHIFT 0 841static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) 842{ 843 return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK; 844} 845 846#define REG_A4XX_RB_STENCILREFMASK 0x0000210b 847#define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 848#define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 849static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 850{ 851 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK; 852} 853#define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 854#define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 855static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 856{ 857 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK; 858} 859#define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 860#define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 861static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 862{ 863 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 864} 865 866#define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c 867#define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 868#define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 869static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 870{ 871 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 872} 873#define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 874#define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 875static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 876{ 877 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 878} 879#define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 880#define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 881static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 882{ 883 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 884} 885 886#define REG_A4XX_RB_BIN_OFFSET 0x0000210d 887#define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000 888#define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff 889#define A4XX_RB_BIN_OFFSET_X__SHIFT 0 890static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val) 891{ 892 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK; 893} 894#define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000 895#define A4XX_RB_BIN_OFFSET_Y__SHIFT 16 896static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) 897{ 898 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; 899} 900 901static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } 902 903static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } 904 905static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } 906 907#define REG_A4XX_RBBM_HW_VERSION 0x00000000 908 909#define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002 910 911static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } 912 913static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } 914 915static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } 916 917static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } 918 919static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } 920 921static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } 922 923static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } 924 925static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } 926 927#define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014 928 929#define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015 930 931#define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016 932 933#define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017 934 935#define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018 936 937#define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019 938 939#define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a 940 941#define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b 942 943#define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c 944 945#define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d 946 947#define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e 948 949#define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f 950 951#define REG_A4XX_RBBM_CLOCK_CTL 0x00000020 952 953#define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021 954 955#define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022 956 957#define REG_A4XX_RBBM_AHB_CTL0 0x00000023 958 959#define REG_A4XX_RBBM_AHB_CTL1 0x00000024 960 961#define REG_A4XX_RBBM_AHB_CMD 0x00000025 962 963#define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026 964 965#define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028 966 967#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b 968 969#define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f 970 971#define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034 972 973#define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036 974 975#define REG_A4XX_RBBM_INT_0_MASK 0x00000037 976 977#define REG_A4XX_RBBM_RBBM_CTL 0x0000003e 978 979#define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f 980 981#define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041 982 983#define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042 984 985#define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 986 987#define REG_A4XX_RBBM_RESET_CYCLES 0x00000047 988 989#define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049 990 991#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a 992 993#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b 994 995#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c 996 997#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d 998 999#define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c 1000 1001static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } 1002 1003static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } 1004 1005static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } 1006 1007static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } 1008 1009static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } 1010 1011static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } 1012 1013static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } 1014 1015static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } 1016 1017static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } 1018 1019static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } 1020 1021static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } 1022 1023static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } 1024 1025static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } 1026 1027static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } 1028 1029static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } 1030 1031static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } 1032 1033#define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080 1034 1035#define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081 1036 1037#define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a 1038 1039#define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b 1040 1041#define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c 1042 1043#define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d 1044 1045static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } 1046 1047static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } 1048 1049#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168 1050 1051#define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170 1052 1053#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171 1054 1055#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172 1056 1057#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173 1058 1059#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174 1060 1061#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175 1062 1063#define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a 1064 1065#define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d 1066 1067#define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182 1068 1069#define REG_A4XX_RBBM_AHB_STATUS 0x00000189 1070 1071#define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c 1072 1073#define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d 1074 1075#define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f 1076 1077#define REG_A4XX_RBBM_STATUS 0x00000191 1078#define A4XX_RBBM_STATUS_HI_BUSY 0x00000001 1079#define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 1080#define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 1081#define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 1082#define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000 1083#define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000 1084#define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000 1085#define A4XX_RBBM_STATUS_RB_BUSY 0x00040000 1086#define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 1087#define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 1088#define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000 1089#define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000 1090#define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000 1091#define A4XX_RBBM_STATUS_SP_BUSY 0x01000000 1092#define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000 1093#define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000 1094#define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000 1095#define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000 1096#define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 1097#define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 1098#define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000 1099 1100#define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f 1101 1102#define REG_A4XX_CP_SCRATCH_UMASK 0x00000228 1103 1104#define REG_A4XX_CP_SCRATCH_ADDR 0x00000229 1105 1106#define REG_A4XX_CP_RB_BASE 0x00000200 1107 1108#define REG_A4XX_CP_RB_CNTL 0x00000201 1109 1110#define REG_A4XX_CP_RB_WPTR 0x00000205 1111 1112#define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203 1113 1114#define REG_A4XX_CP_RB_RPTR 0x00000204 1115 1116#define REG_A4XX_CP_IB1_BASE 0x00000206 1117 1118#define REG_A4XX_CP_IB1_BUFSZ 0x00000207 1119 1120#define REG_A4XX_CP_IB2_BASE 0x00000208 1121 1122#define REG_A4XX_CP_IB2_BUFSZ 0x00000209 1123 1124#define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c 1125 1126#define REG_A4XX_CP_ME_NRT_DATA 0x0000020d 1127 1128#define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217 1129 1130#define REG_A4XX_CP_QUEUE_THRESH2 0x00000219 1131 1132#define REG_A4XX_CP_MERCIU_SIZE 0x0000021b 1133 1134#define REG_A4XX_CP_ROQ_ADDR 0x0000021c 1135 1136#define REG_A4XX_CP_ROQ_DATA 0x0000021d 1137 1138#define REG_A4XX_CP_MEQ_ADDR 0x0000021e 1139 1140#define REG_A4XX_CP_MEQ_DATA 0x0000021f 1141 1142#define REG_A4XX_CP_MERCIU_ADDR 0x00000220 1143 1144#define REG_A4XX_CP_MERCIU_DATA 0x00000221 1145 1146#define REG_A4XX_CP_MERCIU_DATA2 0x00000222 1147 1148#define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223 1149 1150#define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224 1151 1152#define REG_A4XX_CP_ME_RAM_WADDR 0x00000225 1153 1154#define REG_A4XX_CP_ME_RAM_RADDR 0x00000226 1155 1156#define REG_A4XX_CP_ME_RAM_DATA 0x00000227 1157 1158#define REG_A4XX_CP_PREEMPT 0x0000022a 1159 1160#define REG_A4XX_CP_CNTL 0x0000022c 1161 1162#define REG_A4XX_CP_ME_CNTL 0x0000022d 1163 1164#define REG_A4XX_CP_DEBUG 0x0000022e 1165 1166#define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231 1167 1168#define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 1169 1170#define REG_A4XX_CP_PROTECT_REG_0 0x00000240 1171 1172static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } 1173 1174static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } 1175 1176#define REG_A4XX_CP_PROTECT_CTRL 0x00000250 1177 1178#define REG_A4XX_CP_ST_BASE 0x000004c0 1179 1180#define REG_A4XX_CP_STQ_AVAIL 0x000004ce 1181 1182#define REG_A4XX_CP_MERCIU_STAT 0x000004d0 1183 1184#define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2 1185 1186#define REG_A4XX_CP_HW_FAULT 0x000004d8 1187 1188#define REG_A4XX_CP_PROTECT_STATUS 0x000004da 1189 1190#define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd 1191 1192#define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500 1193 1194#define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b 1195 1196static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } 1197 1198static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } 1199 1200#define REG_A4XX_SP_VS_STATUS 0x00000ec0 1201 1202#define REG_A4XX_SP_MODE_CONTROL 0x00000ec3 1203 1204#define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf 1205 1206#define REG_A4XX_SP_SP_CTRL_REG 0x000022c0 1207#define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000 1208 1209#define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1 1210#define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080 1211#define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100 1212#define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400 1213 1214#define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4 1215#define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 1216#define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 1217static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1218{ 1219 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 1220} 1221#define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002 1222#define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 1223#define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1224#define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1225static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1226{ 1227 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1228} 1229#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1230#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1231static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1232{ 1233 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1234} 1235#define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1236#define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1237static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1238{ 1239 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1240} 1241#define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1242#define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 1243static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1244{ 1245 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 1246} 1247#define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1248#define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 1249 1250#define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5 1251#define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 1252#define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1253static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1254{ 1255 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 1256} 1257#define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 1258#define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 1259static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 1260{ 1261 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 1262} 1263 1264#define REG_A4XX_SP_VS_PARAM_REG 0x000022c6 1265#define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 1266#define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 1267static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 1268{ 1269 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK; 1270} 1271#define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 1272#define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 1273static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 1274{ 1275 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 1276} 1277#define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 1278#define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 1279static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 1280{ 1281 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 1282} 1283 1284static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1285 1286static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1287#define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 1288#define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 1289static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 1290{ 1291 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK; 1292} 1293#define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 1294#define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 1295static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 1296{ 1297 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 1298} 1299#define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 1300#define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 1301static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 1302{ 1303 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK; 1304} 1305#define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 1306#define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 1307static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 1308{ 1309 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 1310} 1311 1312static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 1313 1314static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } 1315#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 1316#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 1317static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 1318{ 1319 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 1320} 1321#define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 1322#define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 1323static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 1324{ 1325 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 1326} 1327#define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 1328#define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 1329static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 1330{ 1331 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 1332} 1333#define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 1334#define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 1335static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 1336{ 1337 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 1338} 1339 1340#define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0 1341#define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1342#define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1343static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1344{ 1345 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1346} 1347#define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1348#define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1349static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1350{ 1351 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1352} 1353 1354#define REG_A4XX_SP_VS_OBJ_START 0x000022e1 1355 1356#define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2 1357 1358#define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3 1359 1360#define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5 1361 1362#define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8 1363#define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 1364#define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 1365static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1366{ 1367 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 1368} 1369#define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002 1370#define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 1371#define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1372#define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1373static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1374{ 1375 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1376} 1377#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1378#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1379static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1380{ 1381 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1382} 1383#define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1384#define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1385static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1386{ 1387 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1388} 1389#define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1390#define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 1391static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1392{ 1393 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 1394} 1395#define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1396#define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 1397 1398#define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9 1399#define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff 1400#define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1401static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1402{ 1403 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 1404} 1405#define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000 1406#define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000 1407#define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000 1408 1409#define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea 1410#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1411#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1412static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1413{ 1414 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1415} 1416#define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1417#define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1418static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1419{ 1420 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1421} 1422 1423#define REG_A4XX_SP_FS_OBJ_START 0x000022eb 1424 1425#define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec 1426 1427#define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed 1428 1429#define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef 1430 1431#define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0 1432#define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f 1433#define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 1434static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) 1435{ 1436 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK; 1437} 1438#define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 1439#define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 1440#define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 1441static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 1442{ 1443 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 1444} 1445#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000 1446#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24 1447static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) 1448{ 1449 return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK; 1450} 1451 1452static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 1453 1454static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } 1455#define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 1456#define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0 1457static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val) 1458{ 1459 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK; 1460} 1461#define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 1462#define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000 1463#define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12 1464static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val) 1465{ 1466 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK; 1467} 1468#define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000 1469 1470#define REG_A4XX_SP_CS_CTRL_REG0 0x00002300 1471 1472#define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301 1473 1474#define REG_A4XX_SP_CS_OBJ_START 0x00002302 1475 1476#define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303 1477 1478#define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304 1479 1480#define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305 1481 1482#define REG_A4XX_SP_CS_LENGTH_REG 0x00002306 1483 1484#define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d 1485#define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1486#define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1487static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1488{ 1489 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1490} 1491#define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1492#define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1493static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1494{ 1495 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1496} 1497 1498#define REG_A4XX_SP_HS_OBJ_START 0x0000230e 1499 1500#define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f 1501 1502#define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310 1503 1504#define REG_A4XX_SP_HS_LENGTH_REG 0x00002312 1505 1506#define REG_A4XX_SP_DS_PARAM_REG 0x0000231a 1507#define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff 1508#define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0 1509static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val) 1510{ 1511 return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK; 1512} 1513#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 1514#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 1515static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 1516{ 1517 return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK; 1518} 1519 1520static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; } 1521 1522static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; } 1523#define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff 1524#define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 1525static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val) 1526{ 1527 return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK; 1528} 1529#define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00 1530#define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9 1531static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) 1532{ 1533 return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK; 1534} 1535#define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000 1536#define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 1537static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val) 1538{ 1539 return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK; 1540} 1541#define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000 1542#define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25 1543static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) 1544{ 1545 return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK; 1546} 1547 1548static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; } 1549 1550static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; } 1551#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 1552#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 1553static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) 1554{ 1555 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; 1556} 1557#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 1558#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 1559static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) 1560{ 1561 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; 1562} 1563#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 1564#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 1565static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) 1566{ 1567 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; 1568} 1569#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 1570#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 1571static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) 1572{ 1573 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; 1574} 1575 1576#define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334 1577#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1578#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1579static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1580{ 1581 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1582} 1583#define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1584#define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1585static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1586{ 1587 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1588} 1589 1590#define REG_A4XX_SP_DS_OBJ_START 0x00002335 1591 1592#define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336 1593 1594#define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337 1595 1596#define REG_A4XX_SP_DS_LENGTH_REG 0x00002339 1597 1598#define REG_A4XX_SP_GS_PARAM_REG 0x00002341 1599#define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff 1600#define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0 1601static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val) 1602{ 1603 return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK; 1604} 1605#define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00 1606#define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8 1607static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val) 1608{ 1609 return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK; 1610} 1611#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000 1612#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20 1613static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) 1614{ 1615 return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK; 1616} 1617 1618static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; } 1619 1620static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; } 1621#define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff 1622#define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 1623static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val) 1624{ 1625 return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK; 1626} 1627#define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00 1628#define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9 1629static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) 1630{ 1631 return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK; 1632} 1633#define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000 1634#define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 1635static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val) 1636{ 1637 return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK; 1638} 1639#define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000 1640#define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25 1641static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) 1642{ 1643 return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK; 1644} 1645 1646static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; } 1647 1648static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; } 1649#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 1650#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 1651static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) 1652{ 1653 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; 1654} 1655#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 1656#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 1657static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) 1658{ 1659 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; 1660} 1661#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 1662#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 1663static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) 1664{ 1665 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; 1666} 1667#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 1668#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 1669static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) 1670{ 1671 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; 1672} 1673 1674#define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b 1675#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1676#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1677static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1678{ 1679 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1680} 1681#define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1682#define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1683static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1684{ 1685 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1686} 1687 1688#define REG_A4XX_SP_GS_OBJ_START 0x0000235c 1689 1690#define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d 1691 1692#define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e 1693 1694#define REG_A4XX_SP_GS_LENGTH_REG 0x00002360 1695 1696#define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60 1697 1698#define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61 1699 1700#define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64 1701 1702#define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68 1703 1704#define REG_A4XX_VPC_ATTR 0x00002140 1705#define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 1706#define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0 1707static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val) 1708{ 1709 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK; 1710} 1711#define A4XX_VPC_ATTR_PSIZE 0x00000200 1712#define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000 1713#define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12 1714static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val) 1715{ 1716 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK; 1717} 1718#define A4XX_VPC_ATTR_ENABLE 0x02000000 1719 1720#define REG_A4XX_VPC_PACK 0x00002141 1721#define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff 1722#define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0 1723static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val) 1724{ 1725 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK; 1726} 1727#define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 1728#define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 1729static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 1730{ 1731 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 1732} 1733#define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 1734#define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 1735static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 1736{ 1737 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 1738} 1739 1740static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } 1741 1742static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } 1743 1744static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } 1745 1746static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } 1747 1748#define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e 1749 1750#define REG_A4XX_VSC_BIN_SIZE 0x00000c00 1751#define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 1752#define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 1753static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 1754{ 1755 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; 1756} 1757#define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 1758#define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 1759static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 1760{ 1761 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; 1762} 1763 1764#define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01 1765 1766#define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02 1767 1768#define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03 1769 1770static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 1771 1772static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } 1773#define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff 1774#define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 1775static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) 1776{ 1777 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK; 1778} 1779#define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 1780#define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 1781static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) 1782{ 1783 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK; 1784} 1785#define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000 1786#define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 1787static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) 1788{ 1789 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK; 1790} 1791#define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000 1792#define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24 1793static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) 1794{ 1795 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; 1796} 1797 1798static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 1799 1800static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } 1801 1802static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 1803 1804static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } 1805 1806#define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41 1807 1808#define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50 1809 1810#define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51 1811 1812#define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40 1813 1814#define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a 1815 1816#define REG_A4XX_VGT_CL_INITIATOR 0x000021d0 1817 1818#define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9 1819 1820#define REG_A4XX_VFD_CONTROL_0 0x00002200 1821#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff 1822#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 1823static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 1824{ 1825 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 1826} 1827#define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00 1828#define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9 1829static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val) 1830{ 1831 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK; 1832} 1833#define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000 1834#define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20 1835static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 1836{ 1837 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 1838} 1839#define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000 1840#define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26 1841static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 1842{ 1843 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 1844} 1845 1846#define REG_A4XX_VFD_CONTROL_1 0x00002201 1847#define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 1848#define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 1849static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 1850{ 1851 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 1852} 1853#define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 1854#define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 1855static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 1856{ 1857 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK; 1858} 1859#define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 1860#define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 1861static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 1862{ 1863 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK; 1864} 1865 1866#define REG_A4XX_VFD_CONTROL_2 0x00002202 1867 1868#define REG_A4XX_VFD_CONTROL_3 0x00002203 1869#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00 1870#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8 1871static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val) 1872{ 1873 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK; 1874} 1875#define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 1876#define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 1877static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) 1878{ 1879 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK; 1880} 1881#define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 1882#define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 1883static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) 1884{ 1885 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK; 1886} 1887 1888#define REG_A4XX_VFD_CONTROL_4 0x00002204 1889 1890#define REG_A4XX_VFD_INDEX_OFFSET 0x00002208 1891 1892static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } 1893 1894static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } 1895#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 1896#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 1897static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 1898{ 1899 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 1900} 1901#define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80 1902#define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 1903static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 1904{ 1905 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 1906} 1907#define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000 1908#define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000 1909 1910static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } 1911 1912static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } 1913#define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0 1914#define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4 1915static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val) 1916{ 1917 return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK; 1918} 1919 1920static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } 1921#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff 1922#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0 1923static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) 1924{ 1925 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; 1926} 1927 1928static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } 1929 1930static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } 1931#define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 1932#define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 1933static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 1934{ 1935 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 1936} 1937#define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 1938#define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 1939#define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 1940static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val) 1941{ 1942 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK; 1943} 1944#define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 1945#define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12 1946static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val) 1947{ 1948 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK; 1949} 1950#define A4XX_VFD_DECODE_INSTR_INT 0x00100000 1951#define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 1952#define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 1953static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 1954{ 1955 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK; 1956} 1957#define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 1958#define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 1959static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 1960{ 1961 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 1962} 1963#define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 1964#define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 1965 1966#define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00 1967 1968#define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03 1969 1970#define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b 1971 1972#define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380 1973 1974#define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381 1975#define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff 1976#define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0 1977static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val) 1978{ 1979 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK; 1980} 1981#define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00 1982#define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8 1983static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val) 1984{ 1985 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK; 1986} 1987#define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000 1988#define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16 1989static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val) 1990{ 1991 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK; 1992} 1993#define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000 1994#define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24 1995static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val) 1996{ 1997 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK; 1998} 1999 2000#define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384 2001 2002#define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387 2003 2004#define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a 2005 2006#define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d 2007 2008#define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0 2009 2010#define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1 2011 2012#define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4 2013 2014#define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5 2015 2016#define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6 2017 2018#define REG_A4XX_GRAS_TSE_STATUS 0x00000c80 2019 2020#define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81 2021 2022#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88 2023 2024#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b 2025 2026#define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000 2027 2028#define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003 2029#define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001 2030 2031#define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004 2032#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 2033#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 2034static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 2035{ 2036 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 2037} 2038#define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 2039#define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 2040static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 2041{ 2042 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 2043} 2044 2045#define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008 2046#define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff 2047#define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0 2048static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val) 2049{ 2050 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK; 2051} 2052 2053#define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009 2054#define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff 2055#define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0 2056static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val) 2057{ 2058 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK; 2059} 2060 2061#define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a 2062#define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff 2063#define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0 2064static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val) 2065{ 2066 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK; 2067} 2068 2069#define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b 2070#define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff 2071#define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0 2072static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val) 2073{ 2074 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK; 2075} 2076 2077#define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c 2078#define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff 2079#define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0 2080static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val) 2081{ 2082 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK; 2083} 2084 2085#define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d 2086#define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff 2087#define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0 2088static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val) 2089{ 2090 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK; 2091} 2092 2093#define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070 2094#define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 2095#define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 2096static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val) 2097{ 2098 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 2099} 2100#define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 2101#define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 2102static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val) 2103{ 2104 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 2105} 2106 2107#define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071 2108#define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 2109#define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0 2110static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val) 2111{ 2112 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK; 2113} 2114 2115#define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073 2116#define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004 2117 2118#define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074 2119#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff 2120#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 2121static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val) 2122{ 2123 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; 2124} 2125 2126#define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075 2127#define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 2128#define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 2129static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 2130{ 2131 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 2132} 2133 2134#define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076 2135#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff 2136#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0 2137static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val) 2138{ 2139 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK; 2140} 2141 2142#define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077 2143#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003 2144#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0 2145static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val) 2146{ 2147 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK; 2148} 2149 2150#define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078 2151#define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 2152#define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 2153#define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 2154#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 2155#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 2156static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 2157{ 2158 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 2159} 2160#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 2161#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000 2162 2163#define REG_A4XX_GRAS_SC_CONTROL 0x0000207b 2164#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c 2165#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2 2166static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 2167{ 2168 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 2169} 2170#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380 2171#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7 2172static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val) 2173{ 2174 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 2175} 2176#define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800 2177#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 2178#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 2179static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 2180{ 2181 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 2182} 2183 2184#define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c 2185#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 2186#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 2187#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 2188static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 2189{ 2190 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 2191} 2192#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 2193#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 2194static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 2195{ 2196 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 2197} 2198 2199#define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d 2200#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 2201#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 2202#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 2203static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 2204{ 2205 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 2206} 2207#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 2208#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 2209static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 2210{ 2211 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 2212} 2213 2214#define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c 2215#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 2216#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 2217#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 2218static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 2219{ 2220 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 2221} 2222#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 2223#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 2224static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 2225{ 2226 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 2227} 2228 2229#define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d 2230#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 2231#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 2232#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 2233static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 2234{ 2235 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 2236} 2237#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 2238#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 2239static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 2240{ 2241 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 2242} 2243 2244#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e 2245#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000 2246#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff 2247#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0 2248static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val) 2249{ 2250 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK; 2251} 2252#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000 2253#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16 2254static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val) 2255{ 2256 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK; 2257} 2258 2259#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f 2260#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000 2261#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff 2262#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0 2263static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val) 2264{ 2265 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK; 2266} 2267#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000 2268#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16 2269static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val) 2270{ 2271 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK; 2272} 2273 2274#define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80 2275 2276#define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83 2277 2278#define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84 2279 2280#define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88 2281 2282#define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a 2283 2284#define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b 2285 2286#define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c 2287 2288#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95 2289 2290#define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00 2291 2292#define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04 2293 2294#define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05 2295 2296#define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e 2297 2298#define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0 2299#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 2300#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 2301static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 2302{ 2303 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 2304} 2305#define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 2306#define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 2307#define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 2308#define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 2309#define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 2310#define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 2311static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 2312{ 2313 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 2314} 2315#define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 2316#define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 2317#define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 2318#define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 2319 2320#define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1 2321#define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 2322#define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 2323static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 2324{ 2325 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 2326} 2327#define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 2328#define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 2329#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000 2330#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16 2331static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val) 2332{ 2333 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK; 2334} 2335#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000 2336#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24 2337static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val) 2338{ 2339 return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK; 2340} 2341 2342#define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2 2343#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 2344#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 2345static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 2346{ 2347 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 2348} 2349#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc 2350#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2 2351static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) 2352{ 2353 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; 2354} 2355#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00 2356#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10 2357static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val) 2358{ 2359 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK; 2360} 2361#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000 2362#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18 2363static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val) 2364{ 2365 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK; 2366} 2367 2368#define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3 2369#define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff 2370#define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 2371static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) 2372{ 2373 return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK; 2374} 2375 2376#define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4 2377 2378#define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5 2379#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2380#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2381static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2382{ 2383 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 2384} 2385#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2386#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2387static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2388{ 2389 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2390} 2391#define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000 2392#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2393#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2394static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2395{ 2396 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2397} 2398#define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2399#define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2400static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2401{ 2402 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 2403} 2404 2405#define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6 2406#define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2407#define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2408static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2409{ 2410 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 2411} 2412#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2413#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2414static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2415{ 2416 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2417} 2418#define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000 2419#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2420#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2421static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2422{ 2423 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2424} 2425#define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2426#define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2427static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2428{ 2429 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 2430} 2431 2432#define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7 2433#define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2434#define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2435static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2436{ 2437 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK; 2438} 2439#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2440#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2441static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2442{ 2443 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2444} 2445#define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000 2446#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2447#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2448static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2449{ 2450 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2451} 2452#define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2453#define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2454static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2455{ 2456 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK; 2457} 2458 2459#define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8 2460#define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2461#define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2462static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2463{ 2464 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK; 2465} 2466#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2467#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2468static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2469{ 2470 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2471} 2472#define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000 2473#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2474#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2475static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2476{ 2477 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2478} 2479#define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2480#define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2481static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2482{ 2483 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK; 2484} 2485 2486#define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9 2487#define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff 2488#define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0 2489static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val) 2490{ 2491 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK; 2492} 2493#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00 2494#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8 2495static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val) 2496{ 2497 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK; 2498} 2499#define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000 2500#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000 2501#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17 2502static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val) 2503{ 2504 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK; 2505} 2506#define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 2507#define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24 2508static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val) 2509{ 2510 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK; 2511} 2512 2513#define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca 2514 2515#define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd 2516 2517#define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce 2518 2519#define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf 2520 2521#define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0 2522 2523#define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1 2524 2525#define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2 2526 2527#define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3 2528 2529#define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4 2530 2531#define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5 2532 2533#define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6 2534 2535#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7 2536 2537#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8 2538 2539#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9 2540 2541#define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da 2542 2543#define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db 2544 2545#define REG_A4XX_PC_BINNING_COMMAND 0x00000d00 2546#define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001 2547 2548#define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c 2549 2550#define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10 2551 2552#define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17 2553 2554#define REG_A4XX_PC_BIN_BASE 0x000021c0 2555 2556#define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4 2557#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f 2558#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0 2559static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val) 2560{ 2561 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK; 2562} 2563#define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 2564#define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 2565#define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 2566 2567#define REG_A4XX_UNKNOWN_21C5 0x000021c5 2568 2569#define REG_A4XX_PC_RESTART_INDEX 0x000021c6 2570 2571#define REG_A4XX_PC_GS_PARAM 0x000021e5 2572#define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff 2573#define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0 2574static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val) 2575{ 2576 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK; 2577} 2578#define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800 2579#define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11 2580static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val) 2581{ 2582 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK; 2583} 2584#define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000 2585#define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23 2586static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) 2587{ 2588 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK; 2589} 2590#define A4XX_PC_GS_PARAM_LAYER 0x80000000 2591 2592#define REG_A4XX_PC_HS_PARAM 0x000021e7 2593#define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f 2594#define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0 2595static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val) 2596{ 2597 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK; 2598} 2599#define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000 2600#define A4XX_PC_HS_PARAM_SPACING__SHIFT 21 2601static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val) 2602{ 2603 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK; 2604} 2605#define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000 2606#define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23 2607static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val) 2608{ 2609 return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK; 2610} 2611 2612#define REG_A4XX_VBIF_VERSION 0x00003000 2613 2614#define REG_A4XX_VBIF_CLKON 0x00003001 2615#define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001 2616 2617#define REG_A4XX_VBIF_ABIT_SORT 0x0000301c 2618 2619#define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d 2620 2621#define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2622 2623#define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 2624 2625#define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 2626 2627#define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030 2628 2629#define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031 2630 2631#define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 2632 2633#define REG_A4XX_UNKNOWN_0CC5 0x00000cc5 2634 2635#define REG_A4XX_UNKNOWN_0CC6 0x00000cc6 2636 2637#define REG_A4XX_UNKNOWN_0D01 0x00000d01 2638 2639#define REG_A4XX_UNKNOWN_0E42 0x00000e42 2640 2641#define REG_A4XX_UNKNOWN_0EC2 0x00000ec2 2642 2643#define REG_A4XX_UNKNOWN_2001 0x00002001 2644 2645#define REG_A4XX_UNKNOWN_209B 0x0000209b 2646 2647#define REG_A4XX_UNKNOWN_20EF 0x000020ef 2648 2649#define REG_A4XX_UNKNOWN_20F0 0x000020f0 2650 2651#define REG_A4XX_UNKNOWN_20F1 0x000020f1 2652 2653#define REG_A4XX_UNKNOWN_20F2 0x000020f2 2654 2655#define REG_A4XX_UNKNOWN_20F7 0x000020f7 2656#define A4XX_UNKNOWN_20F7__MASK 0xffffffff 2657#define A4XX_UNKNOWN_20F7__SHIFT 0 2658static inline uint32_t A4XX_UNKNOWN_20F7(float val) 2659{ 2660 return ((fui(val)) << A4XX_UNKNOWN_20F7__SHIFT) & A4XX_UNKNOWN_20F7__MASK; 2661} 2662 2663#define REG_A4XX_UNKNOWN_2152 0x00002152 2664 2665#define REG_A4XX_UNKNOWN_2153 0x00002153 2666 2667#define REG_A4XX_UNKNOWN_2154 0x00002154 2668 2669#define REG_A4XX_UNKNOWN_2155 0x00002155 2670 2671#define REG_A4XX_UNKNOWN_2156 0x00002156 2672 2673#define REG_A4XX_UNKNOWN_2157 0x00002157 2674 2675#define REG_A4XX_UNKNOWN_21C3 0x000021c3 2676 2677#define REG_A4XX_UNKNOWN_21E6 0x000021e6 2678 2679#define REG_A4XX_UNKNOWN_2209 0x00002209 2680 2681#define REG_A4XX_UNKNOWN_22D7 0x000022d7 2682 2683#define REG_A4XX_UNKNOWN_2352 0x00002352 2684 2685#define REG_A4XX_TEX_SAMP_0 0x00000000 2686#define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 2687#define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 2688#define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1 2689static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val) 2690{ 2691 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK; 2692} 2693#define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 2694#define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3 2695static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val) 2696{ 2697 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK; 2698} 2699#define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 2700#define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5 2701static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val) 2702{ 2703 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK; 2704} 2705#define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 2706#define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8 2707static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val) 2708{ 2709 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK; 2710} 2711#define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 2712#define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11 2713static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val) 2714{ 2715 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK; 2716} 2717#define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 2718#define A4XX_TEX_SAMP_0_ANISO__SHIFT 14 2719static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val) 2720{ 2721 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK; 2722} 2723 2724#define REG_A4XX_TEX_SAMP_1 0x00000001 2725#define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e 2726#define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 2727static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) 2728{ 2729 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK; 2730} 2731#define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 2732#define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 2733#define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 2734#define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 2735static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val) 2736{ 2737 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK; 2738} 2739#define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 2740#define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 2741static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val) 2742{ 2743 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK; 2744} 2745 2746#define REG_A4XX_TEX_CONST_0 0x00000000 2747#define A4XX_TEX_CONST_0_TILED 0x00000001 2748#define A4XX_TEX_CONST_0_SRGB 0x00000004 2749#define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 2750#define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4 2751static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val) 2752{ 2753 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK; 2754} 2755#define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 2756#define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 2757static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val) 2758{ 2759 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK; 2760} 2761#define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 2762#define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 2763static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val) 2764{ 2765 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK; 2766} 2767#define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 2768#define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13 2769static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val) 2770{ 2771 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK; 2772} 2773#define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 2774#define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16 2775static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val) 2776{ 2777 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK; 2778} 2779#define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000 2780#define A4XX_TEX_CONST_0_FMT__SHIFT 22 2781static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val) 2782{ 2783 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK; 2784} 2785#define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000 2786#define A4XX_TEX_CONST_0_TYPE__SHIFT 29 2787static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val) 2788{ 2789 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK; 2790} 2791 2792#define REG_A4XX_TEX_CONST_1 0x00000001 2793#define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff 2794#define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0 2795static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val) 2796{ 2797 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK; 2798} 2799#define A4XX_TEX_CONST_1_WIDTH__MASK 0x1fff8000 2800#define A4XX_TEX_CONST_1_WIDTH__SHIFT 15 2801static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val) 2802{ 2803 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK; 2804} 2805 2806#define REG_A4XX_TEX_CONST_2 0x00000002 2807#define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f 2808#define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0 2809static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val) 2810{ 2811 return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK; 2812} 2813#define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00 2814#define A4XX_TEX_CONST_2_PITCH__SHIFT 9 2815static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val) 2816{ 2817 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK; 2818} 2819#define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000 2820#define A4XX_TEX_CONST_2_SWAP__SHIFT 30 2821static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 2822{ 2823 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK; 2824} 2825 2826#define REG_A4XX_TEX_CONST_3 0x00000003 2827#define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff 2828#define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0 2829static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) 2830{ 2831 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; 2832} 2833#define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000 2834#define A4XX_TEX_CONST_3_DEPTH__SHIFT 18 2835static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) 2836{ 2837 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK; 2838} 2839 2840#define REG_A4XX_TEX_CONST_4 0x00000004 2841#define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f 2842#define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0 2843static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) 2844{ 2845 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; 2846} 2847#define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0 2848#define A4XX_TEX_CONST_4_BASE__SHIFT 5 2849static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) 2850{ 2851 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; 2852} 2853 2854#define REG_A4XX_TEX_CONST_5 0x00000005 2855 2856#define REG_A4XX_TEX_CONST_6 0x00000006 2857 2858#define REG_A4XX_TEX_CONST_7 0x00000007 2859 2860 2861#endif /* A4XX_XML */ 2862