1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 *          Alex Deucher
26 *          Jerome Glisse
27 */
28#include <drm/drmP.h>
29#include <drm/amdgpu_drm.h>
30#include "amdgpu.h"
31
32/*
33 * GART
34 * The GART (Graphics Aperture Remapping Table) is an aperture
35 * in the GPU's address space.  System pages can be mapped into
36 * the aperture and look like contiguous pages from the GPU's
37 * perspective.  A page table maps the pages in the aperture
38 * to the actual backing pages in system memory.
39 *
40 * Radeon GPUs support both an internal GART, as described above,
41 * and AGP.  AGP works similarly, but the GART table is configured
42 * and maintained by the northbridge rather than the driver.
43 * Radeon hw has a separate AGP aperture that is programmed to
44 * point to the AGP aperture provided by the northbridge and the
45 * requests are passed through to the northbridge aperture.
46 * Both AGP and internal GART can be used at the same time, however
47 * that is not currently supported by the driver.
48 *
49 * This file handles the common internal GART management.
50 */
51
52/*
53 * Common GART table functions.
54 */
55/**
56 * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
57 *
58 * @adev: amdgpu_device pointer
59 *
60 * Allocate system memory for GART page table
61 * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
62 * gart table to be in system memory.
63 * Returns 0 for success, -ENOMEM for failure.
64 */
65int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev)
66{
67	void *ptr;
68
69	ptr = pci_alloc_consistent(adev->pdev, adev->gart.table_size,
70				   &adev->gart.table_addr);
71	if (ptr == NULL) {
72		return -ENOMEM;
73	}
74#ifdef CONFIG_X86
75	if (0) {
76		set_memory_uc((unsigned long)ptr,
77			      adev->gart.table_size >> PAGE_SHIFT);
78	}
79#endif
80	adev->gart.ptr = ptr;
81	memset((void *)adev->gart.ptr, 0, adev->gart.table_size);
82	return 0;
83}
84
85/**
86 * amdgpu_gart_table_ram_free - free system ram for gart page table
87 *
88 * @adev: amdgpu_device pointer
89 *
90 * Free system memory for GART page table
91 * (r1xx-r3xx, non-pcie r4xx, rs400).  These asics require the
92 * gart table to be in system memory.
93 */
94void amdgpu_gart_table_ram_free(struct amdgpu_device *adev)
95{
96	if (adev->gart.ptr == NULL) {
97		return;
98	}
99#ifdef CONFIG_X86
100	if (0) {
101		set_memory_wb((unsigned long)adev->gart.ptr,
102			      adev->gart.table_size >> PAGE_SHIFT);
103	}
104#endif
105	pci_free_consistent(adev->pdev, adev->gart.table_size,
106			    (void *)adev->gart.ptr,
107			    adev->gart.table_addr);
108	adev->gart.ptr = NULL;
109	adev->gart.table_addr = 0;
110}
111
112/**
113 * amdgpu_gart_table_vram_alloc - allocate vram for gart page table
114 *
115 * @adev: amdgpu_device pointer
116 *
117 * Allocate video memory for GART page table
118 * (pcie r4xx, r5xx+).  These asics require the
119 * gart table to be in video memory.
120 * Returns 0 for success, error for failure.
121 */
122int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
123{
124	int r;
125
126	if (adev->gart.robj == NULL) {
127		r = amdgpu_bo_create(adev, adev->gart.table_size,
128				     PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
129				     AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
130				     NULL, NULL, &adev->gart.robj);
131		if (r) {
132			return r;
133		}
134	}
135	return 0;
136}
137
138/**
139 * amdgpu_gart_table_vram_pin - pin gart page table in vram
140 *
141 * @adev: amdgpu_device pointer
142 *
143 * Pin the GART page table in vram so it will not be moved
144 * by the memory manager (pcie r4xx, r5xx+).  These asics require the
145 * gart table to be in video memory.
146 * Returns 0 for success, error for failure.
147 */
148int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
149{
150	uint64_t gpu_addr;
151	int r;
152
153	r = amdgpu_bo_reserve(adev->gart.robj, false);
154	if (unlikely(r != 0))
155		return r;
156	r = amdgpu_bo_pin(adev->gart.robj,
157				AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
158	if (r) {
159		amdgpu_bo_unreserve(adev->gart.robj);
160		return r;
161	}
162	r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
163	if (r)
164		amdgpu_bo_unpin(adev->gart.robj);
165	amdgpu_bo_unreserve(adev->gart.robj);
166	adev->gart.table_addr = gpu_addr;
167	return r;
168}
169
170/**
171 * amdgpu_gart_table_vram_unpin - unpin gart page table in vram
172 *
173 * @adev: amdgpu_device pointer
174 *
175 * Unpin the GART page table in vram (pcie r4xx, r5xx+).
176 * These asics require the gart table to be in video memory.
177 */
178void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
179{
180	int r;
181
182	if (adev->gart.robj == NULL) {
183		return;
184	}
185	r = amdgpu_bo_reserve(adev->gart.robj, false);
186	if (likely(r == 0)) {
187		amdgpu_bo_kunmap(adev->gart.robj);
188		amdgpu_bo_unpin(adev->gart.robj);
189		amdgpu_bo_unreserve(adev->gart.robj);
190		adev->gart.ptr = NULL;
191	}
192}
193
194/**
195 * amdgpu_gart_table_vram_free - free gart page table vram
196 *
197 * @adev: amdgpu_device pointer
198 *
199 * Free the video memory used for the GART page table
200 * (pcie r4xx, r5xx+).  These asics require the gart table to
201 * be in video memory.
202 */
203void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
204{
205	if (adev->gart.robj == NULL) {
206		return;
207	}
208	amdgpu_bo_unref(&adev->gart.robj);
209}
210
211/*
212 * Common gart functions.
213 */
214/**
215 * amdgpu_gart_unbind - unbind pages from the gart page table
216 *
217 * @adev: amdgpu_device pointer
218 * @offset: offset into the GPU's gart aperture
219 * @pages: number of pages to unbind
220 *
221 * Unbinds the requested pages from the gart page table and
222 * replaces them with the dummy page (all asics).
223 */
224void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
225			int pages)
226{
227	unsigned t;
228	unsigned p;
229	int i, j;
230	u64 page_base;
231	uint32_t flags = AMDGPU_PTE_SYSTEM;
232
233	if (!adev->gart.ready) {
234		WARN(1, "trying to unbind memory from uninitialized GART !\n");
235		return;
236	}
237
238	t = offset / AMDGPU_GPU_PAGE_SIZE;
239	p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
240	for (i = 0; i < pages; i++, p++) {
241		if (adev->gart.pages[p]) {
242			adev->gart.pages[p] = NULL;
243			adev->gart.pages_addr[p] = adev->dummy_page.addr;
244			page_base = adev->gart.pages_addr[p];
245			if (!adev->gart.ptr)
246				continue;
247
248			for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
249				amdgpu_gart_set_pte_pde(adev, adev->gart.ptr,
250							t, page_base, flags);
251				page_base += AMDGPU_GPU_PAGE_SIZE;
252			}
253		}
254	}
255	mb();
256	amdgpu_gart_flush_gpu_tlb(adev, 0);
257}
258
259/**
260 * amdgpu_gart_bind - bind pages into the gart page table
261 *
262 * @adev: amdgpu_device pointer
263 * @offset: offset into the GPU's gart aperture
264 * @pages: number of pages to bind
265 * @pagelist: pages to bind
266 * @dma_addr: DMA addresses of pages
267 *
268 * Binds the requested pages to the gart page table
269 * (all asics).
270 * Returns 0 for success, -EINVAL for failure.
271 */
272int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
273		     int pages, struct page **pagelist, dma_addr_t *dma_addr,
274		     uint32_t flags)
275{
276	unsigned t;
277	unsigned p;
278	uint64_t page_base;
279	int i, j;
280
281	if (!adev->gart.ready) {
282		WARN(1, "trying to bind memory to uninitialized GART !\n");
283		return -EINVAL;
284	}
285
286	t = offset / AMDGPU_GPU_PAGE_SIZE;
287	p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
288
289	for (i = 0; i < pages; i++, p++) {
290		adev->gart.pages_addr[p] = dma_addr[i];
291		adev->gart.pages[p] = pagelist[i];
292		if (adev->gart.ptr) {
293			page_base = adev->gart.pages_addr[p];
294			for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) {
295				amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, t, page_base, flags);
296				page_base += AMDGPU_GPU_PAGE_SIZE;
297			}
298		}
299	}
300	mb();
301	amdgpu_gart_flush_gpu_tlb(adev, 0);
302	return 0;
303}
304
305/**
306 * amdgpu_gart_init - init the driver info for managing the gart
307 *
308 * @adev: amdgpu_device pointer
309 *
310 * Allocate the dummy page and init the gart driver info (all asics).
311 * Returns 0 for success, error for failure.
312 */
313int amdgpu_gart_init(struct amdgpu_device *adev)
314{
315	int r, i;
316
317	if (adev->gart.pages) {
318		return 0;
319	}
320	/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
321	if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
322		DRM_ERROR("Page size is smaller than GPU page size!\n");
323		return -EINVAL;
324	}
325	r = amdgpu_dummy_page_init(adev);
326	if (r)
327		return r;
328	/* Compute table size */
329	adev->gart.num_cpu_pages = adev->mc.gtt_size / PAGE_SIZE;
330	adev->gart.num_gpu_pages = adev->mc.gtt_size / AMDGPU_GPU_PAGE_SIZE;
331	DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
332		 adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
333	/* Allocate pages table */
334	adev->gart.pages = vzalloc(sizeof(void *) * adev->gart.num_cpu_pages);
335	if (adev->gart.pages == NULL) {
336		amdgpu_gart_fini(adev);
337		return -ENOMEM;
338	}
339	adev->gart.pages_addr = vzalloc(sizeof(dma_addr_t) *
340					adev->gart.num_cpu_pages);
341	if (adev->gart.pages_addr == NULL) {
342		amdgpu_gart_fini(adev);
343		return -ENOMEM;
344	}
345	/* set GART entry to point to the dummy page by default */
346	for (i = 0; i < adev->gart.num_cpu_pages; i++) {
347		adev->gart.pages_addr[i] = adev->dummy_page.addr;
348	}
349	return 0;
350}
351
352/**
353 * amdgpu_gart_fini - tear down the driver info for managing the gart
354 *
355 * @adev: amdgpu_device pointer
356 *
357 * Tear down the gart driver info and free the dummy page (all asics).
358 */
359void amdgpu_gart_fini(struct amdgpu_device *adev)
360{
361	if (adev->gart.pages && adev->gart.pages_addr && adev->gart.ready) {
362		/* unbind pages */
363		amdgpu_gart_unbind(adev, 0, adev->gart.num_cpu_pages);
364	}
365	adev->gart.ready = false;
366	vfree(adev->gart.pages);
367	vfree(adev->gart.pages_addr);
368	adev->gart.pages = NULL;
369	adev->gart.pages_addr = NULL;
370
371	amdgpu_dummy_page_fini(adev);
372}
373