1/*
2 * Allwinner SoCs hstimer driver.
3 *
4 * Copyright (C) 2013 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2.  This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/clk.h>
14#include <linux/clockchips.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/irqreturn.h>
19#include <linux/reset.h>
20#include <linux/slab.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24
25#define TIMER_IRQ_EN_REG		0x00
26#define TIMER_IRQ_EN(val)			BIT(val)
27#define TIMER_IRQ_ST_REG		0x04
28#define TIMER_CTL_REG(val)		(0x20 * (val) + 0x10)
29#define TIMER_CTL_ENABLE			BIT(0)
30#define TIMER_CTL_RELOAD			BIT(1)
31#define TIMER_CTL_CLK_PRES(val)			(((val) & 0x7) << 4)
32#define TIMER_CTL_ONESHOT			BIT(7)
33#define TIMER_INTVAL_LO_REG(val)	(0x20 * (val) + 0x14)
34#define TIMER_INTVAL_HI_REG(val)	(0x20 * (val) + 0x18)
35#define TIMER_CNTVAL_LO_REG(val)	(0x20 * (val) + 0x1c)
36#define TIMER_CNTVAL_HI_REG(val)	(0x20 * (val) + 0x20)
37
38#define TIMER_SYNC_TICKS	3
39
40struct sun5i_timer {
41	void __iomem		*base;
42	struct clk		*clk;
43	struct notifier_block	clk_rate_cb;
44	u32			ticks_per_jiffy;
45};
46
47#define to_sun5i_timer(x) \
48	container_of(x, struct sun5i_timer, clk_rate_cb)
49
50struct sun5i_timer_clksrc {
51	struct sun5i_timer	timer;
52	struct clocksource	clksrc;
53};
54
55#define to_sun5i_timer_clksrc(x) \
56	container_of(x, struct sun5i_timer_clksrc, clksrc)
57
58struct sun5i_timer_clkevt {
59	struct sun5i_timer		timer;
60	struct clock_event_device	clkevt;
61};
62
63#define to_sun5i_timer_clkevt(x) \
64	container_of(x, struct sun5i_timer_clkevt, clkevt)
65
66/*
67 * When we disable a timer, we need to wait at least for 2 cycles of
68 * the timer source clock. We will use for that the clocksource timer
69 * that is already setup and runs at the same frequency than the other
70 * timers, and we never will be disabled.
71 */
72static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce)
73{
74	u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1));
75
76	while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
77		cpu_relax();
78}
79
80static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer)
81{
82	u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
83	writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer));
84
85	sun5i_clkevt_sync(ce);
86}
87
88static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay)
89{
90	writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer));
91}
92
93static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, bool periodic)
94{
95	u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
96
97	if (periodic)
98		val &= ~TIMER_CTL_ONESHOT;
99	else
100		val |= TIMER_CTL_ONESHOT;
101
102	writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
103	       ce->timer.base + TIMER_CTL_REG(timer));
104}
105
106static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt)
107{
108	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
109
110	sun5i_clkevt_time_stop(ce, 0);
111	return 0;
112}
113
114static int sun5i_clkevt_set_oneshot(struct clock_event_device *clkevt)
115{
116	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
117
118	sun5i_clkevt_time_stop(ce, 0);
119	sun5i_clkevt_time_start(ce, 0, false);
120	return 0;
121}
122
123static int sun5i_clkevt_set_periodic(struct clock_event_device *clkevt)
124{
125	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
126
127	sun5i_clkevt_time_stop(ce, 0);
128	sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy);
129	sun5i_clkevt_time_start(ce, 0, true);
130	return 0;
131}
132
133static int sun5i_clkevt_next_event(unsigned long evt,
134				   struct clock_event_device *clkevt)
135{
136	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
137
138	sun5i_clkevt_time_stop(ce, 0);
139	sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);
140	sun5i_clkevt_time_start(ce, 0, false);
141
142	return 0;
143}
144
145static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
146{
147	struct sun5i_timer_clkevt *ce = (struct sun5i_timer_clkevt *)dev_id;
148
149	writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG);
150	ce->clkevt.event_handler(&ce->clkevt);
151
152	return IRQ_HANDLED;
153}
154
155static cycle_t sun5i_clksrc_read(struct clocksource *clksrc)
156{
157	struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc);
158
159	return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1));
160}
161
162static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
163				unsigned long event, void *data)
164{
165	struct clk_notifier_data *ndata = data;
166	struct sun5i_timer *timer = to_sun5i_timer(nb);
167	struct sun5i_timer_clksrc *cs = container_of(timer, struct sun5i_timer_clksrc, timer);
168
169	switch (event) {
170	case PRE_RATE_CHANGE:
171		clocksource_unregister(&cs->clksrc);
172		break;
173
174	case POST_RATE_CHANGE:
175		clocksource_register_hz(&cs->clksrc, ndata->new_rate);
176		break;
177
178	default:
179		break;
180	}
181
182	return NOTIFY_DONE;
183}
184
185static int __init sun5i_setup_clocksource(struct device_node *node,
186					  void __iomem *base,
187					  struct clk *clk, int irq)
188{
189	struct sun5i_timer_clksrc *cs;
190	unsigned long rate;
191	int ret;
192
193	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
194	if (!cs)
195		return -ENOMEM;
196
197	ret = clk_prepare_enable(clk);
198	if (ret) {
199		pr_err("Couldn't enable parent clock\n");
200		goto err_free;
201	}
202
203	rate = clk_get_rate(clk);
204
205	cs->timer.base = base;
206	cs->timer.clk = clk;
207	cs->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clksrc;
208	cs->timer.clk_rate_cb.next = NULL;
209
210	ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb);
211	if (ret) {
212		pr_err("Unable to register clock notifier.\n");
213		goto err_disable_clk;
214	}
215
216	writel(~0, base + TIMER_INTVAL_LO_REG(1));
217	writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
218	       base + TIMER_CTL_REG(1));
219
220	cs->clksrc.name = node->name;
221	cs->clksrc.rating = 340;
222	cs->clksrc.read = sun5i_clksrc_read;
223	cs->clksrc.mask = CLOCKSOURCE_MASK(32);
224	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
225
226	ret = clocksource_register_hz(&cs->clksrc, rate);
227	if (ret) {
228		pr_err("Couldn't register clock source.\n");
229		goto err_remove_notifier;
230	}
231
232	return 0;
233
234err_remove_notifier:
235	clk_notifier_unregister(clk, &cs->timer.clk_rate_cb);
236err_disable_clk:
237	clk_disable_unprepare(clk);
238err_free:
239	kfree(cs);
240	return ret;
241}
242
243static int sun5i_rate_cb_clkevt(struct notifier_block *nb,
244				unsigned long event, void *data)
245{
246	struct clk_notifier_data *ndata = data;
247	struct sun5i_timer *timer = to_sun5i_timer(nb);
248	struct sun5i_timer_clkevt *ce = container_of(timer, struct sun5i_timer_clkevt, timer);
249
250	if (event == POST_RATE_CHANGE) {
251		clockevents_update_freq(&ce->clkevt, ndata->new_rate);
252		ce->timer.ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ);
253	}
254
255	return NOTIFY_DONE;
256}
257
258static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem *base,
259					 struct clk *clk, int irq)
260{
261	struct sun5i_timer_clkevt *ce;
262	unsigned long rate;
263	int ret;
264	u32 val;
265
266	ce = kzalloc(sizeof(*ce), GFP_KERNEL);
267	if (!ce)
268		return -ENOMEM;
269
270	ret = clk_prepare_enable(clk);
271	if (ret) {
272		pr_err("Couldn't enable parent clock\n");
273		goto err_free;
274	}
275
276	rate = clk_get_rate(clk);
277
278	ce->timer.base = base;
279	ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
280	ce->timer.clk = clk;
281	ce->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clkevt;
282	ce->timer.clk_rate_cb.next = NULL;
283
284	ret = clk_notifier_register(clk, &ce->timer.clk_rate_cb);
285	if (ret) {
286		pr_err("Unable to register clock notifier.\n");
287		goto err_disable_clk;
288	}
289
290	ce->clkevt.name = node->name;
291	ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
292	ce->clkevt.set_next_event = sun5i_clkevt_next_event;
293	ce->clkevt.set_state_shutdown = sun5i_clkevt_shutdown;
294	ce->clkevt.set_state_periodic = sun5i_clkevt_set_periodic;
295	ce->clkevt.set_state_oneshot = sun5i_clkevt_set_oneshot;
296	ce->clkevt.tick_resume = sun5i_clkevt_shutdown;
297	ce->clkevt.rating = 340;
298	ce->clkevt.irq = irq;
299	ce->clkevt.cpumask = cpu_possible_mask;
300
301	/* Enable timer0 interrupt */
302	val = readl(base + TIMER_IRQ_EN_REG);
303	writel(val | TIMER_IRQ_EN(0), base + TIMER_IRQ_EN_REG);
304
305	clockevents_config_and_register(&ce->clkevt, rate,
306					TIMER_SYNC_TICKS, 0xffffffff);
307
308	ret = request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
309			  "sun5i_timer0", ce);
310	if (ret) {
311		pr_err("Unable to register interrupt\n");
312		goto err_remove_notifier;
313	}
314
315	return 0;
316
317err_remove_notifier:
318	clk_notifier_unregister(clk, &ce->timer.clk_rate_cb);
319err_disable_clk:
320	clk_disable_unprepare(clk);
321err_free:
322	kfree(ce);
323	return ret;
324}
325
326static void __init sun5i_timer_init(struct device_node *node)
327{
328	struct reset_control *rstc;
329	void __iomem *timer_base;
330	struct clk *clk;
331	int irq;
332
333	timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
334	if (IS_ERR(timer_base))
335		panic("Can't map registers");
336
337	irq = irq_of_parse_and_map(node, 0);
338	if (irq <= 0)
339		panic("Can't parse IRQ");
340
341	clk = of_clk_get(node, 0);
342	if (IS_ERR(clk))
343		panic("Can't get timer clock");
344
345	rstc = of_reset_control_get(node, NULL);
346	if (!IS_ERR(rstc))
347		reset_control_deassert(rstc);
348
349	sun5i_setup_clocksource(node, timer_base, clk, irq);
350	sun5i_setup_clockevent(node, timer_base, clk, irq);
351}
352CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
353		       sun5i_timer_init);
354CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
355		       sun5i_timer_init);
356