1/* 2 * OMAP4 Clock init 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * Tero Kristo (t-kristo@ti.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13#include <linux/kernel.h> 14#include <linux/list.h> 15#include <linux/clk.h> 16#include <linux/clkdev.h> 17#include <linux/clk/ti.h> 18 19#include "clock.h" 20 21/* 22 * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section 23 * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK 24 * must be set to 196.608 MHz" and hence, the DPLL locked frequency is 25 * half of this value. 26 */ 27#define OMAP4_DPLL_ABE_DEFFREQ 98304000 28 29/* 30 * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section 31 * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred 32 * locked frequency for the USB DPLL is 960MHz. 33 */ 34#define OMAP4_DPLL_USB_DEFFREQ 960000000 35 36static struct ti_dt_clk omap44xx_clks[] = { 37 DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"), 38 DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"), 39 DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"), 40 DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"), 41 DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), 42 DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"), 43 DT_CLK(NULL, "slimbus_clk", "slimbus_clk"), 44 DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), 45 DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), 46 DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), 47 DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), 48 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), 49 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), 50 DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), 51 DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), 52 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), 53 DT_CLK(NULL, "tie_low_clock_ck", "tie_low_clock_ck"), 54 DT_CLK(NULL, "utmi_phy_clkout_ck", "utmi_phy_clkout_ck"), 55 DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"), 56 DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"), 57 DT_CLK(NULL, "xclk60motg_ck", "xclk60motg_ck"), 58 DT_CLK(NULL, "abe_dpll_bypass_clk_mux_ck", "abe_dpll_bypass_clk_mux_ck"), 59 DT_CLK(NULL, "abe_dpll_refclk_mux_ck", "abe_dpll_refclk_mux_ck"), 60 DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"), 61 DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"), 62 DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"), 63 DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"), 64 DT_CLK(NULL, "abe_clk", "abe_clk"), 65 DT_CLK(NULL, "aess_fclk", "aess_fclk"), 66 DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"), 67 DT_CLK(NULL, "core_hsd_byp_clk_mux_ck", "core_hsd_byp_clk_mux_ck"), 68 DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), 69 DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), 70 DT_CLK(NULL, "dpll_core_m6x2_ck", "dpll_core_m6x2_ck"), 71 DT_CLK(NULL, "dbgclk_mux_ck", "dbgclk_mux_ck"), 72 DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"), 73 DT_CLK(NULL, "ddrphy_ck", "ddrphy_ck"), 74 DT_CLK(NULL, "dpll_core_m5x2_ck", "dpll_core_m5x2_ck"), 75 DT_CLK(NULL, "div_core_ck", "div_core_ck"), 76 DT_CLK(NULL, "div_iva_hs_clk", "div_iva_hs_clk"), 77 DT_CLK(NULL, "div_mpu_hs_clk", "div_mpu_hs_clk"), 78 DT_CLK(NULL, "dpll_core_m4x2_ck", "dpll_core_m4x2_ck"), 79 DT_CLK(NULL, "dll_clk_div_ck", "dll_clk_div_ck"), 80 DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"), 81 DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"), 82 DT_CLK(NULL, "dpll_core_m7x2_ck", "dpll_core_m7x2_ck"), 83 DT_CLK(NULL, "iva_hsd_byp_clk_mux_ck", "iva_hsd_byp_clk_mux_ck"), 84 DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"), 85 DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"), 86 DT_CLK(NULL, "dpll_iva_m4x2_ck", "dpll_iva_m4x2_ck"), 87 DT_CLK(NULL, "dpll_iva_m5x2_ck", "dpll_iva_m5x2_ck"), 88 DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), 89 DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), 90 DT_CLK(NULL, "per_hs_clk_div_ck", "per_hs_clk_div_ck"), 91 DT_CLK(NULL, "per_hsd_byp_clk_mux_ck", "per_hsd_byp_clk_mux_ck"), 92 DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"), 93 DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"), 94 DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"), 95 DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"), 96 DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"), 97 DT_CLK(NULL, "dpll_per_m4x2_ck", "dpll_per_m4x2_ck"), 98 DT_CLK(NULL, "dpll_per_m5x2_ck", "dpll_per_m5x2_ck"), 99 DT_CLK(NULL, "dpll_per_m6x2_ck", "dpll_per_m6x2_ck"), 100 DT_CLK(NULL, "dpll_per_m7x2_ck", "dpll_per_m7x2_ck"), 101 DT_CLK(NULL, "usb_hs_clk_div_ck", "usb_hs_clk_div_ck"), 102 DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"), 103 DT_CLK(NULL, "dpll_usb_clkdcoldo_ck", "dpll_usb_clkdcoldo_ck"), 104 DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"), 105 DT_CLK(NULL, "ducati_clk_mux_ck", "ducati_clk_mux_ck"), 106 DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"), 107 DT_CLK(NULL, "func_24m_clk", "func_24m_clk"), 108 DT_CLK(NULL, "func_24mc_fclk", "func_24mc_fclk"), 109 DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"), 110 DT_CLK(NULL, "func_48mc_fclk", "func_48mc_fclk"), 111 DT_CLK(NULL, "func_64m_fclk", "func_64m_fclk"), 112 DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"), 113 DT_CLK(NULL, "init_60m_fclk", "init_60m_fclk"), 114 DT_CLK(NULL, "l3_div_ck", "l3_div_ck"), 115 DT_CLK(NULL, "l4_div_ck", "l4_div_ck"), 116 DT_CLK(NULL, "lp_clk_div_ck", "lp_clk_div_ck"), 117 DT_CLK(NULL, "l4_wkup_clk_mux_ck", "l4_wkup_clk_mux_ck"), 118 DT_CLK("smp_twd", NULL, "mpu_periphclk"), 119 DT_CLK(NULL, "ocp_abe_iclk", "ocp_abe_iclk"), 120 DT_CLK(NULL, "per_abe_24m_fclk", "per_abe_24m_fclk"), 121 DT_CLK(NULL, "per_abe_nc_fclk", "per_abe_nc_fclk"), 122 DT_CLK(NULL, "syc_clk_div_ck", "syc_clk_div_ck"), 123 DT_CLK(NULL, "aes1_fck", "aes1_fck"), 124 DT_CLK(NULL, "aes2_fck", "aes2_fck"), 125 DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"), 126 DT_CLK(NULL, "func_dmic_abe_gfclk", "func_dmic_abe_gfclk"), 127 DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"), 128 DT_CLK(NULL, "dss_tv_clk", "dss_tv_clk"), 129 DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"), 130 DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"), 131 DT_CLK(NULL, "dss_fck", "dss_fck"), 132 DT_CLK("omapdss_dss", "ick", "dss_fck"), 133 DT_CLK(NULL, "fdif_fck", "fdif_fck"), 134 DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"), 135 DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"), 136 DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"), 137 DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"), 138 DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"), 139 DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"), 140 DT_CLK(NULL, "sgx_clk_mux", "sgx_clk_mux"), 141 DT_CLK(NULL, "hsi_fck", "hsi_fck"), 142 DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"), 143 DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"), 144 DT_CLK(NULL, "func_mcasp_abe_gfclk", "func_mcasp_abe_gfclk"), 145 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"), 146 DT_CLK(NULL, "func_mcbsp1_gfclk", "func_mcbsp1_gfclk"), 147 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"), 148 DT_CLK(NULL, "func_mcbsp2_gfclk", "func_mcbsp2_gfclk"), 149 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"), 150 DT_CLK(NULL, "func_mcbsp3_gfclk", "func_mcbsp3_gfclk"), 151 DT_CLK(NULL, "mcbsp4_sync_mux_ck", "mcbsp4_sync_mux_ck"), 152 DT_CLK(NULL, "per_mcbsp4_gfclk", "per_mcbsp4_gfclk"), 153 DT_CLK(NULL, "hsmmc1_fclk", "hsmmc1_fclk"), 154 DT_CLK(NULL, "hsmmc2_fclk", "hsmmc2_fclk"), 155 DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "ocp2scp_usb_phy_phy_48m"), 156 DT_CLK(NULL, "sha2md5_fck", "sha2md5_fck"), 157 DT_CLK(NULL, "slimbus1_fclk_1", "slimbus1_fclk_1"), 158 DT_CLK(NULL, "slimbus1_fclk_0", "slimbus1_fclk_0"), 159 DT_CLK(NULL, "slimbus1_fclk_2", "slimbus1_fclk_2"), 160 DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"), 161 DT_CLK(NULL, "slimbus2_fclk_1", "slimbus2_fclk_1"), 162 DT_CLK(NULL, "slimbus2_fclk_0", "slimbus2_fclk_0"), 163 DT_CLK(NULL, "slimbus2_slimbus_clk", "slimbus2_slimbus_clk"), 164 DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"), 165 DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"), 166 DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"), 167 DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"), 168 DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"), 169 DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"), 170 DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"), 171 DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"), 172 DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"), 173 DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"), 174 DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"), 175 DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"), 176 DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"), 177 DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"), 178 DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"), 179 DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"), 180 DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"), 181 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"), 182 DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"), 183 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"), 184 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"), 185 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"), 186 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"), 187 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"), 188 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"), 189 DT_CLK(NULL, "usb_host_hs_func48mclk", "usb_host_hs_func48mclk"), 190 DT_CLK(NULL, "usb_host_hs_fck", "usb_host_hs_fck"), 191 DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"), 192 DT_CLK(NULL, "otg_60m_gfclk", "otg_60m_gfclk"), 193 DT_CLK(NULL, "usb_otg_hs_xclk", "usb_otg_hs_xclk"), 194 DT_CLK(NULL, "usb_otg_hs_ick", "usb_otg_hs_ick"), 195 DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"), 196 DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"), 197 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"), 198 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"), 199 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"), 200 DT_CLK(NULL, "usb_tll_hs_ick", "usb_tll_hs_ick"), 201 DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"), 202 DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"), 203 DT_CLK(NULL, "usim_ck", "usim_ck"), 204 DT_CLK(NULL, "usim_fclk", "usim_fclk"), 205 DT_CLK(NULL, "pmd_stm_clock_mux_ck", "pmd_stm_clock_mux_ck"), 206 DT_CLK(NULL, "pmd_trace_clk_mux_ck", "pmd_trace_clk_mux_ck"), 207 DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"), 208 DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"), 209 DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"), 210 DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"), 211 DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"), 212 DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"), 213 DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"), 214 DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"), 215 DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"), 216 DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"), 217 DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"), 218 DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"), 219 DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"), 220 DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"), 221 DT_CLK(NULL, "auxclk4_src_ck", "auxclk4_src_ck"), 222 DT_CLK(NULL, "auxclk4_ck", "auxclk4_ck"), 223 DT_CLK(NULL, "auxclkreq4_ck", "auxclkreq4_ck"), 224 DT_CLK(NULL, "auxclk5_src_ck", "auxclk5_src_ck"), 225 DT_CLK(NULL, "auxclk5_ck", "auxclk5_ck"), 226 DT_CLK(NULL, "auxclkreq5_ck", "auxclkreq5_ck"), 227 DT_CLK("omap_i2c.1", "ick", "dummy_ck"), 228 DT_CLK("omap_i2c.2", "ick", "dummy_ck"), 229 DT_CLK("omap_i2c.3", "ick", "dummy_ck"), 230 DT_CLK("omap_i2c.4", "ick", "dummy_ck"), 231 DT_CLK(NULL, "mailboxes_ick", "dummy_ck"), 232 DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"), 233 DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"), 234 DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"), 235 DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"), 236 DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"), 237 DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"), 238 DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"), 239 DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"), 240 DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"), 241 DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"), 242 DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"), 243 DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"), 244 DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"), 245 DT_CLK(NULL, "uart1_ick", "dummy_ck"), 246 DT_CLK(NULL, "uart2_ick", "dummy_ck"), 247 DT_CLK(NULL, "uart3_ick", "dummy_ck"), 248 DT_CLK(NULL, "uart4_ick", "dummy_ck"), 249 DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"), 250 DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"), 251 DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"), 252 DT_CLK("omap_wdt", "ick", "dummy_ck"), 253 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), 254 DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"), 255 DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"), 256 DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"), 257 DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"), 258 DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"), 259 DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"), 260 DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"), 261 DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"), 262 DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"), 263 DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"), 264 DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"), 265 DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"), 266 DT_CLK(NULL, "bandgap_fclk", "bandgap_fclk"), 267 DT_CLK(NULL, "div_ts_ck", "div_ts_ck"), 268 DT_CLK(NULL, "bandgap_ts_fclk", "bandgap_ts_fclk"), 269 { .node_name = NULL }, 270}; 271 272int __init omap4xxx_dt_clk_init(void) 273{ 274 int rc; 275 struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll; 276 277 ti_dt_clocks_register(omap44xx_clks); 278 279 omap2_clk_disable_autoidle_all(); 280 281 /* 282 * Lock USB DPLL on OMAP4 devices so that the L3INIT power 283 * domain can transition to retention state when not in use. 284 */ 285 usb_dpll = clk_get_sys(NULL, "dpll_usb_ck"); 286 rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ); 287 if (rc) 288 pr_err("%s: failed to configure USB DPLL!\n", __func__); 289 290 /* 291 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power 292 * state when turning the ABE clock domain. Workaround this by 293 * locking the ABE DPLL on boot. 294 * Lock the ABE DPLL in any case to avoid issues with audio. 295 */ 296 abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck"); 297 sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck"); 298 rc = clk_set_parent(abe_dpll_ref, sys_32k_ck); 299 abe_dpll = clk_get_sys(NULL, "dpll_abe_ck"); 300 if (!rc) 301 rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ); 302 if (rc) 303 pr_err("%s: failed to configure ABE DPLL!\n", __func__); 304 305 return 0; 306} 307