1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/delay.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/clk/tegra.h>
24
25#include <soc/tegra/pmc.h>
26
27#include <dt-bindings/clock/tegra30-car.h>
28
29#include "clk.h"
30#include "clk-id.h"
31
32#define OSC_CTRL			0x50
33#define OSC_CTRL_OSC_FREQ_MASK		(0xF<<28)
34#define OSC_CTRL_OSC_FREQ_13MHZ		(0X0<<28)
35#define OSC_CTRL_OSC_FREQ_19_2MHZ	(0X4<<28)
36#define OSC_CTRL_OSC_FREQ_12MHZ		(0X8<<28)
37#define OSC_CTRL_OSC_FREQ_26MHZ		(0XC<<28)
38#define OSC_CTRL_OSC_FREQ_16_8MHZ	(0X1<<28)
39#define OSC_CTRL_OSC_FREQ_38_4MHZ	(0X5<<28)
40#define OSC_CTRL_OSC_FREQ_48MHZ		(0X9<<28)
41#define OSC_CTRL_MASK			(0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
42
43#define OSC_CTRL_PLL_REF_DIV_MASK	(3<<26)
44#define OSC_CTRL_PLL_REF_DIV_1		(0<<26)
45#define OSC_CTRL_PLL_REF_DIV_2		(1<<26)
46#define OSC_CTRL_PLL_REF_DIV_4		(2<<26)
47
48#define OSC_FREQ_DET			0x58
49#define OSC_FREQ_DET_TRIG		BIT(31)
50
51#define OSC_FREQ_DET_STATUS		0x5c
52#define OSC_FREQ_DET_BUSY		BIT(31)
53#define OSC_FREQ_DET_CNT_MASK		0xffff
54
55#define CCLKG_BURST_POLICY 0x368
56#define SUPER_CCLKG_DIVIDER 0x36c
57#define CCLKLP_BURST_POLICY 0x370
58#define SUPER_CCLKLP_DIVIDER 0x374
59#define SCLK_BURST_POLICY 0x028
60#define SUPER_SCLK_DIVIDER 0x02c
61
62#define SYSTEM_CLK_RATE 0x030
63
64#define TEGRA30_CLK_PERIPH_BANKS	5
65
66#define PLLC_BASE 0x80
67#define PLLC_MISC 0x8c
68#define PLLM_BASE 0x90
69#define PLLM_MISC 0x9c
70#define PLLP_BASE 0xa0
71#define PLLP_MISC 0xac
72#define PLLX_BASE 0xe0
73#define PLLX_MISC 0xe4
74#define PLLD_BASE 0xd0
75#define PLLD_MISC 0xdc
76#define PLLD2_BASE 0x4b8
77#define PLLD2_MISC 0x4bc
78#define PLLE_BASE 0xe8
79#define PLLE_MISC 0xec
80#define PLLA_BASE 0xb0
81#define PLLA_MISC 0xbc
82#define PLLU_BASE 0xc0
83#define PLLU_MISC 0xcc
84
85#define PLL_MISC_LOCK_ENABLE 18
86#define PLLDU_MISC_LOCK_ENABLE 22
87#define PLLE_MISC_LOCK_ENABLE 9
88
89#define PLL_BASE_LOCK BIT(27)
90#define PLLE_MISC_LOCK BIT(11)
91
92#define PLLE_AUX 0x48c
93#define PLLC_OUT 0x84
94#define PLLM_OUT 0x94
95#define PLLP_OUTA 0xa4
96#define PLLP_OUTB 0xa8
97#define PLLA_OUT 0xb4
98
99#define AUDIO_SYNC_CLK_I2S0 0x4a0
100#define AUDIO_SYNC_CLK_I2S1 0x4a4
101#define AUDIO_SYNC_CLK_I2S2 0x4a8
102#define AUDIO_SYNC_CLK_I2S3 0x4ac
103#define AUDIO_SYNC_CLK_I2S4 0x4b0
104#define AUDIO_SYNC_CLK_SPDIF 0x4b4
105
106#define CLK_SOURCE_SPDIF_OUT 0x108
107#define CLK_SOURCE_PWM 0x110
108#define CLK_SOURCE_D_AUDIO 0x3d0
109#define CLK_SOURCE_DAM0 0x3d8
110#define CLK_SOURCE_DAM1 0x3dc
111#define CLK_SOURCE_DAM2 0x3e0
112#define CLK_SOURCE_3D2 0x3b0
113#define CLK_SOURCE_2D 0x15c
114#define CLK_SOURCE_HDMI 0x18c
115#define CLK_SOURCE_DSIB 0xd0
116#define CLK_SOURCE_SE 0x42c
117#define CLK_SOURCE_EMC 0x19c
118
119#define AUDIO_SYNC_DOUBLER 0x49c
120
121#define UTMIP_PLL_CFG2 0x488
122#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
123#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
124#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
125#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
126#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
127
128#define UTMIP_PLL_CFG1 0x484
129#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
130#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
131#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
132#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
133#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
134
135/* Tegra CPU clock and reset control regs */
136#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX		0x4c
137#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET	0x340
138#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR	0x344
139#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR	0x34c
140#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS	0x470
141
142#define CPU_CLOCK(cpu)	(0x1 << (8 + cpu))
143#define CPU_RESET(cpu)	(0x1111ul << (cpu))
144
145#define CLK_RESET_CCLK_BURST	0x20
146#define CLK_RESET_CCLK_DIVIDER	0x24
147#define CLK_RESET_PLLX_BASE	0xe0
148#define CLK_RESET_PLLX_MISC	0xe4
149
150#define CLK_RESET_SOURCE_CSITE	0x1d4
151
152#define CLK_RESET_CCLK_BURST_POLICY_SHIFT	28
153#define CLK_RESET_CCLK_RUN_POLICY_SHIFT		4
154#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT	0
155#define CLK_RESET_CCLK_IDLE_POLICY		1
156#define CLK_RESET_CCLK_RUN_POLICY		2
157#define CLK_RESET_CCLK_BURST_POLICY_PLLX	8
158
159/* PLLM override registers */
160#define PMC_PLLM_WB0_OVERRIDE 0x1dc
161
162#ifdef CONFIG_PM_SLEEP
163static struct cpu_clk_suspend_context {
164	u32 pllx_misc;
165	u32 pllx_base;
166
167	u32 cpu_burst;
168	u32 clk_csite_src;
169	u32 cclk_divider;
170} tegra30_cpu_clk_sctx;
171#endif
172
173static void __iomem *clk_base;
174static void __iomem *pmc_base;
175static unsigned long input_freq;
176
177static DEFINE_SPINLOCK(cml_lock);
178static DEFINE_SPINLOCK(pll_d_lock);
179static DEFINE_SPINLOCK(emc_lock);
180
181#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset,	\
182			    _clk_num, _gate_flags, _clk_id)	\
183	TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,	\
184			30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
185			_clk_num, _gate_flags, _clk_id)
186
187#define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \
188			     _clk_num, _gate_flags, _clk_id)	\
189	TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,	\
190			29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
191			_clk_num, _gate_flags, _clk_id)
192
193#define TEGRA_INIT_DATA_INT(_name, _parents, _offset,	\
194			    _clk_num, _gate_flags, _clk_id)	\
195	TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,	\
196			30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT |		\
197			TEGRA_DIVIDER_ROUND_UP, _clk_num,	\
198			_gate_flags, _clk_id)
199
200#define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
201			      _mux_shift, _mux_width, _clk_num, \
202			      _gate_flags, _clk_id)			\
203	TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset,	\
204			_mux_shift, _mux_width, 0, 0, 0, 0, 0,\
205			_clk_num, _gate_flags,	\
206			_clk_id)
207
208static struct clk **clks;
209
210/*
211 * Structure defining the fields for USB UTMI clocks Parameters.
212 */
213struct utmi_clk_param {
214	/* Oscillator Frequency in KHz */
215	u32 osc_frequency;
216	/* UTMIP PLL Enable Delay Count  */
217	u8 enable_delay_count;
218	/* UTMIP PLL Stable count */
219	u8 stable_count;
220	/*  UTMIP PLL Active delay count */
221	u8 active_delay_count;
222	/* UTMIP PLL Xtal frequency count */
223	u8 xtal_freq_count;
224};
225
226static const struct utmi_clk_param utmi_parameters[] = {
227/*	OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
228	{13000000,     0x02,       0x33,       0x05,       0x7F},
229	{19200000,     0x03,       0x4B,       0x06,       0xBB},
230	{12000000,     0x02,       0x2F,       0x04,       0x76},
231	{26000000,     0x04,       0x66,       0x09,       0xFE},
232	{16800000,     0x03,       0x41,       0x0A,       0xA4},
233};
234
235static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
236	{ 12000000, 1040000000, 520,  6, 0, 8},
237	{ 13000000, 1040000000, 480,  6, 0, 8},
238	{ 16800000, 1040000000, 495,  8, 0, 8},	/* actual: 1039.5 MHz */
239	{ 19200000, 1040000000, 325,  6, 0, 6},
240	{ 26000000, 1040000000, 520, 13, 0, 8},
241
242	{ 12000000, 832000000, 416,  6, 0, 8},
243	{ 13000000, 832000000, 832, 13, 0, 8},
244	{ 16800000, 832000000, 396,  8, 0, 8},	/* actual: 831.6 MHz */
245	{ 19200000, 832000000, 260,  6, 0, 8},
246	{ 26000000, 832000000, 416, 13, 0, 8},
247
248	{ 12000000, 624000000, 624, 12, 0, 8},
249	{ 13000000, 624000000, 624, 13, 0, 8},
250	{ 16800000, 600000000, 520, 14, 0, 8},
251	{ 19200000, 624000000, 520, 16, 0, 8},
252	{ 26000000, 624000000, 624, 26, 0, 8},
253
254	{ 12000000, 600000000, 600, 12, 0, 8},
255	{ 13000000, 600000000, 600, 13, 0, 8},
256	{ 16800000, 600000000, 500, 14, 0, 8},
257	{ 19200000, 600000000, 375, 12, 0, 6},
258	{ 26000000, 600000000, 600, 26, 0, 8},
259
260	{ 12000000, 520000000, 520, 12, 0, 8},
261	{ 13000000, 520000000, 520, 13, 0, 8},
262	{ 16800000, 520000000, 495, 16, 0, 8},	/* actual: 519.75 MHz */
263	{ 19200000, 520000000, 325, 12, 0, 6},
264	{ 26000000, 520000000, 520, 26, 0, 8},
265
266	{ 12000000, 416000000, 416, 12, 0, 8},
267	{ 13000000, 416000000, 416, 13, 0, 8},
268	{ 16800000, 416000000, 396, 16, 0, 8},	/* actual: 415.8 MHz */
269	{ 19200000, 416000000, 260, 12, 0, 6},
270	{ 26000000, 416000000, 416, 26, 0, 8},
271	{ 0, 0, 0, 0, 0, 0 },
272};
273
274static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
275	{ 12000000, 666000000, 666, 12, 0, 8},
276	{ 13000000, 666000000, 666, 13, 0, 8},
277	{ 16800000, 666000000, 555, 14, 0, 8},
278	{ 19200000, 666000000, 555, 16, 0, 8},
279	{ 26000000, 666000000, 666, 26, 0, 8},
280	{ 12000000, 600000000, 600, 12, 0, 8},
281	{ 13000000, 600000000, 600, 13, 0, 8},
282	{ 16800000, 600000000, 500, 14, 0, 8},
283	{ 19200000, 600000000, 375, 12, 0, 6},
284	{ 26000000, 600000000, 600, 26, 0, 8},
285	{ 0, 0, 0, 0, 0, 0 },
286};
287
288static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
289	{ 12000000, 216000000, 432, 12, 1, 8},
290	{ 13000000, 216000000, 432, 13, 1, 8},
291	{ 16800000, 216000000, 360, 14, 1, 8},
292	{ 19200000, 216000000, 360, 16, 1, 8},
293	{ 26000000, 216000000, 432, 26, 1, 8},
294	{ 0, 0, 0, 0, 0, 0 },
295};
296
297static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
298	{ 9600000, 564480000, 294, 5, 0, 4},
299	{ 9600000, 552960000, 288, 5, 0, 4},
300	{ 9600000, 24000000,  5,   2, 0, 1},
301
302	{ 28800000, 56448000, 49, 25, 0, 1},
303	{ 28800000, 73728000, 64, 25, 0, 1},
304	{ 28800000, 24000000,  5,  6, 0, 1},
305	{ 0, 0, 0, 0, 0, 0 },
306};
307
308static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
309	{ 12000000, 216000000, 216, 12, 0, 4},
310	{ 13000000, 216000000, 216, 13, 0, 4},
311	{ 16800000, 216000000, 180, 14, 0, 4},
312	{ 19200000, 216000000, 180, 16, 0, 4},
313	{ 26000000, 216000000, 216, 26, 0, 4},
314
315	{ 12000000, 594000000, 594, 12, 0, 8},
316	{ 13000000, 594000000, 594, 13, 0, 8},
317	{ 16800000, 594000000, 495, 14, 0, 8},
318	{ 19200000, 594000000, 495, 16, 0, 8},
319	{ 26000000, 594000000, 594, 26, 0, 8},
320
321	{ 12000000, 1000000000, 1000, 12, 0, 12},
322	{ 13000000, 1000000000, 1000, 13, 0, 12},
323	{ 19200000, 1000000000, 625,  12, 0, 8},
324	{ 26000000, 1000000000, 1000, 26, 0, 12},
325
326	{ 0, 0, 0, 0, 0, 0 },
327};
328
329static struct pdiv_map pllu_p[] = {
330	{ .pdiv = 1, .hw_val = 1 },
331	{ .pdiv = 2, .hw_val = 0 },
332	{ .pdiv = 0, .hw_val = 0 },
333};
334
335static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
336	{ 12000000, 480000000, 960, 12, 0, 12},
337	{ 13000000, 480000000, 960, 13, 0, 12},
338	{ 16800000, 480000000, 400, 7,  0, 5},
339	{ 19200000, 480000000, 200, 4,  0, 3},
340	{ 26000000, 480000000, 960, 26, 0, 12},
341	{ 0, 0, 0, 0, 0, 0 },
342};
343
344static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
345	/* 1.7 GHz */
346	{ 12000000, 1700000000, 850,  6,  0, 8},
347	{ 13000000, 1700000000, 915,  7,  0, 8},	/* actual: 1699.2 MHz */
348	{ 16800000, 1700000000, 708,  7,  0, 8},	/* actual: 1699.2 MHz */
349	{ 19200000, 1700000000, 885,  10, 0, 8},	/* actual: 1699.2 MHz */
350	{ 26000000, 1700000000, 850,  13, 0, 8},
351
352	/* 1.6 GHz */
353	{ 12000000, 1600000000, 800,  6,  0, 8},
354	{ 13000000, 1600000000, 738,  6,  0, 8},	/* actual: 1599.0 MHz */
355	{ 16800000, 1600000000, 857,  9,  0, 8},	/* actual: 1599.7 MHz */
356	{ 19200000, 1600000000, 500,  6,  0, 8},
357	{ 26000000, 1600000000, 800,  13, 0, 8},
358
359	/* 1.5 GHz */
360	{ 12000000, 1500000000, 750,  6,  0, 8},
361	{ 13000000, 1500000000, 923,  8,  0, 8},	/* actual: 1499.8 MHz */
362	{ 16800000, 1500000000, 625,  7,  0, 8},
363	{ 19200000, 1500000000, 625,  8,  0, 8},
364	{ 26000000, 1500000000, 750,  13, 0, 8},
365
366	/* 1.4 GHz */
367	{ 12000000, 1400000000, 700,  6,  0, 8},
368	{ 13000000, 1400000000, 969,  9,  0, 8},	/* actual: 1399.7 MHz */
369	{ 16800000, 1400000000, 1000, 12, 0, 8},
370	{ 19200000, 1400000000, 875,  12, 0, 8},
371	{ 26000000, 1400000000, 700,  13, 0, 8},
372
373	/* 1.3 GHz */
374	{ 12000000, 1300000000, 975,  9,  0, 8},
375	{ 13000000, 1300000000, 1000, 10, 0, 8},
376	{ 16800000, 1300000000, 928,  12, 0, 8},	/* actual: 1299.2 MHz */
377	{ 19200000, 1300000000, 812,  12, 0, 8},	/* actual: 1299.2 MHz */
378	{ 26000000, 1300000000, 650,  13, 0, 8},
379
380	/* 1.2 GHz */
381	{ 12000000, 1200000000, 1000, 10, 0, 8},
382	{ 13000000, 1200000000, 923,  10, 0, 8},	/* actual: 1199.9 MHz */
383	{ 16800000, 1200000000, 1000, 14, 0, 8},
384	{ 19200000, 1200000000, 1000, 16, 0, 8},
385	{ 26000000, 1200000000, 600,  13, 0, 8},
386
387	/* 1.1 GHz */
388	{ 12000000, 1100000000, 825,  9,  0, 8},
389	{ 13000000, 1100000000, 846,  10, 0, 8},	/* actual: 1099.8 MHz */
390	{ 16800000, 1100000000, 982,  15, 0, 8},	/* actual: 1099.8 MHz */
391	{ 19200000, 1100000000, 859,  15, 0, 8},	/* actual: 1099.5 MHz */
392	{ 26000000, 1100000000, 550,  13, 0, 8},
393
394	/* 1 GHz */
395	{ 12000000, 1000000000, 1000, 12, 0, 8},
396	{ 13000000, 1000000000, 1000, 13, 0, 8},
397	{ 16800000, 1000000000, 833,  14, 0, 8},	/* actual: 999.6 MHz */
398	{ 19200000, 1000000000, 625,  12, 0, 8},
399	{ 26000000, 1000000000, 1000, 26, 0, 8},
400
401	{ 0, 0, 0, 0, 0, 0 },
402};
403
404static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
405	/* PLLE special case: use cpcon field to store cml divider value */
406	{ 12000000,  100000000, 150, 1,  18, 11},
407	{ 216000000, 100000000, 200, 18, 24, 13},
408	{ 0, 0, 0, 0, 0, 0 },
409};
410
411/* PLL parameters */
412static struct tegra_clk_pll_params pll_c_params = {
413	.input_min = 2000000,
414	.input_max = 31000000,
415	.cf_min = 1000000,
416	.cf_max = 6000000,
417	.vco_min = 20000000,
418	.vco_max = 1400000000,
419	.base_reg = PLLC_BASE,
420	.misc_reg = PLLC_MISC,
421	.lock_mask = PLL_BASE_LOCK,
422	.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
423	.lock_delay = 300,
424	.freq_table = pll_c_freq_table,
425	.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
426};
427
428static struct div_nmp pllm_nmp = {
429	.divn_shift = 8,
430	.divn_width = 10,
431	.override_divn_shift = 5,
432	.divm_shift = 0,
433	.divm_width = 5,
434	.override_divm_shift = 0,
435	.divp_shift = 20,
436	.divp_width = 3,
437	.override_divp_shift = 15,
438};
439
440static struct tegra_clk_pll_params pll_m_params = {
441	.input_min = 2000000,
442	.input_max = 31000000,
443	.cf_min = 1000000,
444	.cf_max = 6000000,
445	.vco_min = 20000000,
446	.vco_max = 1200000000,
447	.base_reg = PLLM_BASE,
448	.misc_reg = PLLM_MISC,
449	.lock_mask = PLL_BASE_LOCK,
450	.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
451	.lock_delay = 300,
452	.div_nmp = &pllm_nmp,
453	.pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
454	.pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
455	.freq_table = pll_m_freq_table,
456	.flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
457		 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK,
458};
459
460static struct tegra_clk_pll_params pll_p_params = {
461	.input_min = 2000000,
462	.input_max = 31000000,
463	.cf_min = 1000000,
464	.cf_max = 6000000,
465	.vco_min = 20000000,
466	.vco_max = 1400000000,
467	.base_reg = PLLP_BASE,
468	.misc_reg = PLLP_MISC,
469	.lock_mask = PLL_BASE_LOCK,
470	.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
471	.lock_delay = 300,
472	.freq_table = pll_p_freq_table,
473	.flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
474	.fixed_rate = 408000000,
475};
476
477static struct tegra_clk_pll_params pll_a_params = {
478	.input_min = 2000000,
479	.input_max = 31000000,
480	.cf_min = 1000000,
481	.cf_max = 6000000,
482	.vco_min = 20000000,
483	.vco_max = 1400000000,
484	.base_reg = PLLA_BASE,
485	.misc_reg = PLLA_MISC,
486	.lock_mask = PLL_BASE_LOCK,
487	.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
488	.lock_delay = 300,
489	.freq_table = pll_a_freq_table,
490	.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK,
491};
492
493static struct tegra_clk_pll_params pll_d_params = {
494	.input_min = 2000000,
495	.input_max = 40000000,
496	.cf_min = 1000000,
497	.cf_max = 6000000,
498	.vco_min = 40000000,
499	.vco_max = 1000000000,
500	.base_reg = PLLD_BASE,
501	.misc_reg = PLLD_MISC,
502	.lock_mask = PLL_BASE_LOCK,
503	.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
504	.lock_delay = 1000,
505	.freq_table = pll_d_freq_table,
506	.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
507		 TEGRA_PLL_USE_LOCK,
508
509};
510
511static struct tegra_clk_pll_params pll_d2_params = {
512	.input_min = 2000000,
513	.input_max = 40000000,
514	.cf_min = 1000000,
515	.cf_max = 6000000,
516	.vco_min = 40000000,
517	.vco_max = 1000000000,
518	.base_reg = PLLD2_BASE,
519	.misc_reg = PLLD2_MISC,
520	.lock_mask = PLL_BASE_LOCK,
521	.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
522	.lock_delay = 1000,
523	.freq_table = pll_d_freq_table,
524	.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
525		 TEGRA_PLL_USE_LOCK,
526};
527
528static struct tegra_clk_pll_params pll_u_params = {
529	.input_min = 2000000,
530	.input_max = 40000000,
531	.cf_min = 1000000,
532	.cf_max = 6000000,
533	.vco_min = 48000000,
534	.vco_max = 960000000,
535	.base_reg = PLLU_BASE,
536	.misc_reg = PLLU_MISC,
537	.lock_mask = PLL_BASE_LOCK,
538	.lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
539	.lock_delay = 1000,
540	.pdiv_tohw = pllu_p,
541	.freq_table = pll_u_freq_table,
542	.flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON,
543};
544
545static struct tegra_clk_pll_params pll_x_params = {
546	.input_min = 2000000,
547	.input_max = 31000000,
548	.cf_min = 1000000,
549	.cf_max = 6000000,
550	.vco_min = 20000000,
551	.vco_max = 1700000000,
552	.base_reg = PLLX_BASE,
553	.misc_reg = PLLX_MISC,
554	.lock_mask = PLL_BASE_LOCK,
555	.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
556	.lock_delay = 300,
557	.freq_table = pll_x_freq_table,
558	.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
559		 TEGRA_PLL_USE_LOCK,
560};
561
562static struct tegra_clk_pll_params pll_e_params = {
563	.input_min = 12000000,
564	.input_max = 216000000,
565	.cf_min = 12000000,
566	.cf_max = 12000000,
567	.vco_min = 1200000000,
568	.vco_max = 2400000000U,
569	.base_reg = PLLE_BASE,
570	.misc_reg = PLLE_MISC,
571	.lock_mask = PLLE_MISC_LOCK,
572	.lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
573	.lock_delay = 300,
574	.freq_table = pll_e_freq_table,
575	.flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED,
576	.fixed_rate = 100000000,
577};
578
579static unsigned long tegra30_input_freq[] = {
580	[0] = 13000000,
581	[1] = 16800000,
582	[4] = 19200000,
583	[5] = 38400000,
584	[8] = 12000000,
585	[9] = 48000000,
586	[12] = 260000000,
587};
588
589static struct tegra_devclk devclks[] __initdata = {
590	{ .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
591	{ .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
592	{ .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
593	{ .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },
594	{ .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },
595	{ .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },
596	{ .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },
597	{ .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },
598	{ .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },
599	{ .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },
600	{ .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 },
601	{ .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
602	{ .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D },
603	{ .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },
604	{ .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 },
605	{ .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 },
606	{ .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A },
607	{ .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },
608	{ .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
609	{ .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC },
610	{ .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC },
611	{ .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC },
612	{ .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC },
613	{ .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC },
614	{ .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC },
615	{ .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC },
616	{ .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 },
617	{ .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 },
618	{ .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 },
619	{ .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 },
620	{ .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 },
621	{ .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF },
622	{ .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X },
623	{ .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X },
624	{ .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X },
625	{ .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
626	{ .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
627	{ .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
628	{ .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 },
629	{ .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 },
630	{ .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 },
631	{ .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK },
632	{ .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
633	{ .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
634	{ .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
635	{ .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
636	{ .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
637	{ .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
638	{ .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
639	{ .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
640	{ .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
641	{ .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
642	{ .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
643	{ .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
644	{ .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
645	{ .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
646	{ .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
647	{ .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
648	{ .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
649	{ .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
650	{ .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA },
651	{ .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI },
652	{ .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
653	{ .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
654	{ .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
655	{ .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
656	{ .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
657	{ .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
658	{ .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
659	{ .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
660	{ .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
661	{ .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
662	{ .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
663	{ .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
664	{ .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
665	{ .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
666	{ .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
667	{ .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
668	{ .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
669	{ .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
670	{ .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
671	{ .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
672	{ .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
673	{ .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
674	{ .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
675	{ .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
676	{ .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
677	{ .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
678	{ .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
679	{ .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
680	{ .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
681	{ .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
682	{ .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },
683	{ .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },
684	{ .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },
685	{ .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 },
686	{ .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 },
687	{ .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 },
688	{ .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB },
689	{ .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA },
690	{ .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH },
691	{ .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED },
692	{ .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR },
693	{ .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE },
694	{ .dev_id = "la", .dt_id = TEGRA30_CLK_LA },
695	{ .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR },
696	{ .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI },
697	{ .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
698	{ .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW },
699	{ .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE },
700	{ .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI },
701	{ .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP },
702	{ .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE },
703	{ .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X },
704	{ .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D },
705	{ .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },
706	{ .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D },
707	{ .dev_id = "se", .dt_id = TEGRA30_CLK_SE },
708	{ .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT },
709	{ .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
710	{ .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
711	{ .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
712	{ .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
713	{ .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
714	{ .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE },
715	{ .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO },
716	{ .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC },
717	{ .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON },
718	{ .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR },
719	{ .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
720	{ .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
721	{ .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
722	{ .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
723	{ .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
724	{ .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA },
725	{ .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB },
726	{ .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC },
727	{ .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD },
728	{ .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE },
729	{ .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI },
730	{ .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
731	{ .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
732	{ .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
733	{ .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM },
734	{ .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 },
735	{ .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 },
736	{ .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
737};
738
739static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
740	[tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
741	[tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
742	[tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
743	[tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
744	[tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
745	[tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
746	[tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
747	[tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
748	[tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
749	[tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
750	[tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
751	[tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },
752	[tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },
753	[tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },
754	[tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },
755	[tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },
756	[tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },
757	[tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },
758	[tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },
759	[tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },
760	[tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },
761	[tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },
762	[tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },
763	[tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },
764	[tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },
765	[tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },
766	[tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },
767	[tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
768	[tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
769	[tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
770	[tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true },
771	[tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true },
772	[tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true },
773	[tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true },
774	[tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true },
775	[tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true },
776	[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true },
777	[tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
778	[tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
779	[tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
780	[tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },
781	[tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },
782	[tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },
783	[tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },
784	[tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },
785	[tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },
786	[tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },
787	[tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },
788	[tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },
789	[tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },
790	[tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },
791	[tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },
792	[tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },
793	[tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },
794	[tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },
795	[tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },
796	[tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },
797	[tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },
798	[tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },
799	[tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },
800	[tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },
801	[tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },
802	[tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },
803	[tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },
804	[tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },
805	[tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },
806	[tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },
807	[tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },
808	[tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },
809	[tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },
810	[tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },
811	[tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },
812	[tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },
813	[tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },
814	[tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },
815	[tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },
816	[tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },
817	[tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },
818	[tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },
819	[tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },
820	[tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },
821	[tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },
822	[tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },
823	[tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },
824	[tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },
825	[tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },
826	[tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },
827	[tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },
828	[tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },
829	[tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },
830	[tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
831	[tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
832	[tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
833	[tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
834	[tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
835	[tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
836	[tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
837	[tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
838	[tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
839	[tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
840	[tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
841	[tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
842	[tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
843	[tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },
844	[tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },
845	[tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },
846	[tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },
847	[tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },
848	[tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },
849	[tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },
850	[tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },
851	[tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },
852	[tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },
853	[tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },
854	[tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },
855	[tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },
856	[tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },
857	[tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
858	[tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },
859	[tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },
860	[tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },
861	[tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
862	[tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
863	[tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
864
865};
866
867static void tegra30_utmi_param_configure(void)
868{
869	u32 reg;
870	int i;
871
872	for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
873		if (input_freq == utmi_parameters[i].osc_frequency)
874			break;
875	}
876
877	if (i >= ARRAY_SIZE(utmi_parameters)) {
878		pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq);
879		return;
880	}
881
882	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
883
884	/* Program UTMIP PLL stable and active counts */
885	reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
886	reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
887			utmi_parameters[i].stable_count);
888
889	reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
890
891	reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
892			utmi_parameters[i].active_delay_count);
893
894	/* Remove power downs from UTMIP PLL control bits */
895	reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
896	reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
897	reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
898
899	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
900
901	/* Program UTMIP PLL delay and oscillator frequency counts */
902	reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
903	reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
904
905	reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
906		utmi_parameters[i].enable_delay_count);
907
908	reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
909	reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
910		utmi_parameters[i].xtal_freq_count);
911
912	/* Remove power downs from UTMIP PLL control bits */
913	reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
914	reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
915	reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
916
917	writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
918}
919
920static const char *pll_e_parents[] = {"pll_ref", "pll_p"};
921
922static void __init tegra30_pll_init(void)
923{
924	struct clk *clk;
925
926	/* PLLC */
927	clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
928				&pll_c_params, NULL);
929	clks[TEGRA30_CLK_PLL_C] = clk;
930
931	/* PLLC_OUT1 */
932	clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
933				clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
934				8, 8, 1, NULL);
935	clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
936				clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
937				0, NULL);
938	clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
939
940	/* PLLM */
941	clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
942			    CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
943			    &pll_m_params, NULL);
944	clks[TEGRA30_CLK_PLL_M] = clk;
945
946	/* PLLM_OUT1 */
947	clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
948				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
949				8, 8, 1, NULL);
950	clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
951				clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
952				CLK_SET_RATE_PARENT, 0, NULL);
953	clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
954
955	/* PLLX */
956	clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
957			    &pll_x_params, NULL);
958	clks[TEGRA30_CLK_PLL_X] = clk;
959
960	/* PLLX_OUT0 */
961	clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
962					CLK_SET_RATE_PARENT, 1, 2);
963	clks[TEGRA30_CLK_PLL_X_OUT0] = clk;
964
965	/* PLLU */
966	clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
967			    &pll_u_params, NULL);
968	clks[TEGRA30_CLK_PLL_U] = clk;
969
970	tegra30_utmi_param_configure();
971
972	/* PLLD */
973	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
974			    &pll_d_params, &pll_d_lock);
975	clks[TEGRA30_CLK_PLL_D] = clk;
976
977	/* PLLD_OUT0 */
978	clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
979					CLK_SET_RATE_PARENT, 1, 2);
980	clks[TEGRA30_CLK_PLL_D_OUT0] = clk;
981
982	/* PLLD2 */
983	clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
984			    &pll_d2_params, NULL);
985	clks[TEGRA30_CLK_PLL_D2] = clk;
986
987	/* PLLD2_OUT0 */
988	clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
989					CLK_SET_RATE_PARENT, 1, 2);
990	clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;
991
992	/* PLLE */
993	clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
994			       ARRAY_SIZE(pll_e_parents),
995			       CLK_SET_RATE_NO_REPARENT,
996			       clk_base + PLLE_AUX, 2, 1, 0, NULL);
997	clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
998			     CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
999	clks[TEGRA30_CLK_PLL_E] = clk;
1000}
1001
1002static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1003					"pll_p_cclkg", "pll_p_out4_cclkg",
1004					"pll_p_out3_cclkg", "unused", "pll_x" };
1005static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1006					 "pll_p_cclklp", "pll_p_out4_cclklp",
1007					 "pll_p_out3_cclklp", "unused", "pll_x",
1008					 "pll_x_out0" };
1009static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1010				      "pll_p_out3", "pll_p_out2", "unused",
1011				      "clk_32k", "pll_m_out1" };
1012
1013static void __init tegra30_super_clk_init(void)
1014{
1015	struct clk *clk;
1016
1017	/*
1018	 * Clock input to cclk_g divided from pll_p using
1019	 * U71 divider of cclk_g.
1020	 */
1021	clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
1022				clk_base + SUPER_CCLKG_DIVIDER, 0,
1023				TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1024	clk_register_clkdev(clk, "pll_p_cclkg", NULL);
1025
1026	/*
1027	 * Clock input to cclk_g divided from pll_p_out3 using
1028	 * U71 divider of cclk_g.
1029	 */
1030	clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
1031				clk_base + SUPER_CCLKG_DIVIDER, 0,
1032				TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1033	clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
1034
1035	/*
1036	 * Clock input to cclk_g divided from pll_p_out4 using
1037	 * U71 divider of cclk_g.
1038	 */
1039	clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
1040				clk_base + SUPER_CCLKG_DIVIDER, 0,
1041				TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1042	clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
1043
1044	/* CCLKG */
1045	clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1046				  ARRAY_SIZE(cclk_g_parents),
1047				  CLK_SET_RATE_PARENT,
1048				  clk_base + CCLKG_BURST_POLICY,
1049				  0, 4, 0, 0, NULL);
1050	clks[TEGRA30_CLK_CCLK_G] = clk;
1051
1052	/*
1053	 * Clock input to cclk_lp divided from pll_p using
1054	 * U71 divider of cclk_lp.
1055	 */
1056	clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
1057				clk_base + SUPER_CCLKLP_DIVIDER, 0,
1058				TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1059	clk_register_clkdev(clk, "pll_p_cclklp", NULL);
1060
1061	/*
1062	 * Clock input to cclk_lp divided from pll_p_out3 using
1063	 * U71 divider of cclk_lp.
1064	 */
1065	clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
1066				clk_base + SUPER_CCLKG_DIVIDER, 0,
1067				TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1068	clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
1069
1070	/*
1071	 * Clock input to cclk_lp divided from pll_p_out4 using
1072	 * U71 divider of cclk_lp.
1073	 */
1074	clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
1075				clk_base + SUPER_CCLKLP_DIVIDER, 0,
1076				TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1077	clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
1078
1079	/* CCLKLP */
1080	clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1081				  ARRAY_SIZE(cclk_lp_parents),
1082				  CLK_SET_RATE_PARENT,
1083				  clk_base + CCLKLP_BURST_POLICY,
1084				  TEGRA_DIVIDER_2, 4, 8, 9,
1085			      NULL);
1086	clks[TEGRA30_CLK_CCLK_LP] = clk;
1087
1088	/* SCLK */
1089	clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1090				  ARRAY_SIZE(sclk_parents),
1091				  CLK_SET_RATE_PARENT,
1092				  clk_base + SCLK_BURST_POLICY,
1093				  0, 4, 0, 0, NULL);
1094	clks[TEGRA30_CLK_SCLK] = clk;
1095
1096	/* twd */
1097	clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
1098					CLK_SET_RATE_PARENT, 1, 2);
1099	clks[TEGRA30_CLK_TWD] = clk;
1100
1101	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);
1102}
1103
1104static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
1105					 "clk_m" };
1106static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
1107static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
1108static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
1109					   "clk_m" };
1110static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
1111static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
1112					     "pll_a_out0", "pll_c",
1113					     "pll_d2_out0", "clk_m" };
1114static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1115						  "pll_d2_out0" };
1116static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" };
1117
1118static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1119	TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT),
1120	TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO),
1121	TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0),
1122	TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1),
1123	TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2),
1124	TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2),
1125	TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),
1126	TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI),
1127	TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM),
1128};
1129
1130static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1131	TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),
1132};
1133
1134static void __init tegra30_periph_clk_init(void)
1135{
1136	struct tegra_periph_init_data *data;
1137	struct clk *clk;
1138	int i;
1139
1140	/* dsia */
1141	clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1142				    0, 48, periph_clk_enb_refcnt);
1143	clks[TEGRA30_CLK_DSIA] = clk;
1144
1145	/* pcie */
1146	clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1147				    70, periph_clk_enb_refcnt);
1148	clks[TEGRA30_CLK_PCIE] = clk;
1149
1150	/* afi */
1151	clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1152				    periph_clk_enb_refcnt);
1153	clks[TEGRA30_CLK_AFI] = clk;
1154
1155	/* emc */
1156	clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1157			       ARRAY_SIZE(mux_pllmcp_clkm),
1158			       CLK_SET_RATE_NO_REPARENT,
1159			       clk_base + CLK_SOURCE_EMC,
1160			       30, 2, 0, &emc_lock);
1161	clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
1162				    57, periph_clk_enb_refcnt);
1163	clks[TEGRA30_CLK_EMC] = clk;
1164
1165	clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
1166				    &emc_lock);
1167	clks[TEGRA30_CLK_MC] = clk;
1168
1169	/* cml0 */
1170	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1171				0, 0, &cml_lock);
1172	clks[TEGRA30_CLK_CML0] = clk;
1173
1174	/* cml1 */
1175	clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1176				1, 0, &cml_lock);
1177	clks[TEGRA30_CLK_CML1] = clk;
1178
1179	for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1180		data = &tegra_periph_clk_list[i];
1181		clk = tegra_clk_register_periph(data->name, data->p.parent_names,
1182				data->num_parents, &data->periph,
1183				clk_base, data->offset, data->flags);
1184		clks[data->clk_id] = clk;
1185	}
1186
1187	for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1188		data = &tegra_periph_nodiv_clk_list[i];
1189		clk = tegra_clk_register_periph_nodiv(data->name,
1190					data->p.parent_names,
1191					data->num_parents, &data->periph,
1192					clk_base, data->offset);
1193		clks[data->clk_id] = clk;
1194	}
1195
1196	tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);
1197}
1198
1199/* Tegra30 CPU clock and reset control functions */
1200static void tegra30_wait_cpu_in_reset(u32 cpu)
1201{
1202	unsigned int reg;
1203
1204	do {
1205		reg = readl(clk_base +
1206			    TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1207		cpu_relax();
1208	} while (!(reg & (1 << cpu)));	/* check CPU been reset or not */
1209
1210	return;
1211}
1212
1213static void tegra30_put_cpu_in_reset(u32 cpu)
1214{
1215	writel(CPU_RESET(cpu),
1216	       clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1217	dmb();
1218}
1219
1220static void tegra30_cpu_out_of_reset(u32 cpu)
1221{
1222	writel(CPU_RESET(cpu),
1223	       clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1224	wmb();
1225}
1226
1227
1228static void tegra30_enable_cpu_clock(u32 cpu)
1229{
1230	unsigned int reg;
1231
1232	writel(CPU_CLOCK(cpu),
1233	       clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1234	reg = readl(clk_base +
1235		    TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1236}
1237
1238static void tegra30_disable_cpu_clock(u32 cpu)
1239{
1240
1241	unsigned int reg;
1242
1243	reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1244	writel(reg | CPU_CLOCK(cpu),
1245	       clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1246}
1247
1248#ifdef CONFIG_PM_SLEEP
1249static bool tegra30_cpu_rail_off_ready(void)
1250{
1251	unsigned int cpu_rst_status;
1252	int cpu_pwr_status;
1253
1254	cpu_rst_status = readl(clk_base +
1255				TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1256	cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
1257			 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
1258			 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
1259
1260	if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
1261		return false;
1262
1263	return true;
1264}
1265
1266static void tegra30_cpu_clock_suspend(void)
1267{
1268	/* switch coresite to clk_m, save off original source */
1269	tegra30_cpu_clk_sctx.clk_csite_src =
1270				readl(clk_base + CLK_RESET_SOURCE_CSITE);
1271	writel(3<<30, clk_base + CLK_RESET_SOURCE_CSITE);
1272
1273	tegra30_cpu_clk_sctx.cpu_burst =
1274				readl(clk_base + CLK_RESET_CCLK_BURST);
1275	tegra30_cpu_clk_sctx.pllx_base =
1276				readl(clk_base + CLK_RESET_PLLX_BASE);
1277	tegra30_cpu_clk_sctx.pllx_misc =
1278				readl(clk_base + CLK_RESET_PLLX_MISC);
1279	tegra30_cpu_clk_sctx.cclk_divider =
1280				readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1281}
1282
1283static void tegra30_cpu_clock_resume(void)
1284{
1285	unsigned int reg, policy;
1286
1287	/* Is CPU complex already running on PLLX? */
1288	reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1289	policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
1290
1291	if (policy == CLK_RESET_CCLK_IDLE_POLICY)
1292		reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
1293	else if (policy == CLK_RESET_CCLK_RUN_POLICY)
1294		reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
1295	else
1296		BUG();
1297
1298	if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
1299		/* restore PLLX settings if CPU is on different PLL */
1300		writel(tegra30_cpu_clk_sctx.pllx_misc,
1301					clk_base + CLK_RESET_PLLX_MISC);
1302		writel(tegra30_cpu_clk_sctx.pllx_base,
1303					clk_base + CLK_RESET_PLLX_BASE);
1304
1305		/* wait for PLL stabilization if PLLX was enabled */
1306		if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
1307			udelay(300);
1308	}
1309
1310	/*
1311	 * Restore original burst policy setting for calls resulting from CPU
1312	 * LP2 in idle or system suspend.
1313	 */
1314	writel(tegra30_cpu_clk_sctx.cclk_divider,
1315					clk_base + CLK_RESET_CCLK_DIVIDER);
1316	writel(tegra30_cpu_clk_sctx.cpu_burst,
1317					clk_base + CLK_RESET_CCLK_BURST);
1318
1319	writel(tegra30_cpu_clk_sctx.clk_csite_src,
1320					clk_base + CLK_RESET_SOURCE_CSITE);
1321}
1322#endif
1323
1324static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1325	.wait_for_reset	= tegra30_wait_cpu_in_reset,
1326	.put_in_reset	= tegra30_put_cpu_in_reset,
1327	.out_of_reset	= tegra30_cpu_out_of_reset,
1328	.enable_clock	= tegra30_enable_cpu_clock,
1329	.disable_clock	= tegra30_disable_cpu_clock,
1330#ifdef CONFIG_PM_SLEEP
1331	.rail_off_ready	= tegra30_cpu_rail_off_ready,
1332	.suspend	= tegra30_cpu_clock_suspend,
1333	.resume		= tegra30_cpu_clock_resume,
1334#endif
1335};
1336
1337static struct tegra_clk_init_table init_table[] __initdata = {
1338	{TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0},
1339	{TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0},
1340	{TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0},
1341	{TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0},
1342	{TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0},
1343	{TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1},
1344	{TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1},
1345	{TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1},
1346	{TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0},
1347	{TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1},
1348	{TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1},
1349	{TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1350	{TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1351	{TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1352	{TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1353	{TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
1354	{TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0},
1355	{TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0},
1356	{TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0},
1357	{TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1},
1358	{TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1},
1359	{TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1},
1360	{TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1},
1361	{TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1},
1362	{TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0},
1363	{TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0},
1364	{TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0},
1365	{TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0},
1366	{TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0},
1367	{TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0},
1368	{TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0},
1369	{TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0},
1370	{TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0},
1371	{TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1},
1372	{TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0},
1373	{TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0},
1374	{TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0},
1375	{TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry. */
1376};
1377
1378static void __init tegra30_clock_apply_init_table(void)
1379{
1380	tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
1381}
1382
1383/*
1384 * Some clocks may be used by different drivers depending on the board
1385 * configuration.  List those here to register them twice in the clock lookup
1386 * table under two names.
1387 */
1388static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1389	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),
1390	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),
1391	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),
1392	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),
1393	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"),
1394	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),
1395	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),
1396	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
1397	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
1398	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
1399	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
1400	TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), /* MUST be the last entry */
1401};
1402
1403static const struct of_device_id pmc_match[] __initconst = {
1404	{ .compatible = "nvidia,tegra30-pmc" },
1405	{},
1406};
1407
1408static struct tegra_audio_clk_info tegra30_audio_plls[] = {
1409	{ "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
1410};
1411
1412static void __init tegra30_clock_init(struct device_node *np)
1413{
1414	struct device_node *node;
1415
1416	clk_base = of_iomap(np, 0);
1417	if (!clk_base) {
1418		pr_err("ioremap tegra30 CAR failed\n");
1419		return;
1420	}
1421
1422	node = of_find_matching_node(NULL, pmc_match);
1423	if (!node) {
1424		pr_err("Failed to find pmc node\n");
1425		BUG();
1426	}
1427
1428	pmc_base = of_iomap(node, 0);
1429	if (!pmc_base) {
1430		pr_err("Can't map pmc registers\n");
1431		BUG();
1432	}
1433
1434	clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
1435				TEGRA30_CLK_PERIPH_BANKS);
1436	if (!clks)
1437		return;
1438
1439	if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
1440			       ARRAY_SIZE(tegra30_input_freq), 1, &input_freq,
1441			       NULL) < 0)
1442		return;
1443
1444
1445	tegra_fixed_clk_init(tegra30_clks);
1446	tegra30_pll_init();
1447	tegra30_super_clk_init();
1448	tegra30_periph_clk_init();
1449	tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
1450			     tegra30_audio_plls,
1451			     ARRAY_SIZE(tegra30_audio_plls));
1452	tegra_pmc_clk_init(pmc_base, tegra30_clks);
1453
1454	tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
1455
1456	tegra_add_of_provider(np);
1457	tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1458
1459	tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
1460
1461	tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1462}
1463CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
1464