1/* 2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#include <linux/io.h> 18#include <linux/clk-provider.h> 19#include <linux/clkdev.h> 20#include <linux/of.h> 21#include <linux/of_address.h> 22#include <linux/delay.h> 23#include <linux/export.h> 24#include <linux/clk/tegra.h> 25 26#include "clk.h" 27#include "clk-id.h" 28 29#define CLK_SOURCE_I2S0 0x1d8 30#define CLK_SOURCE_I2S1 0x100 31#define CLK_SOURCE_I2S2 0x104 32#define CLK_SOURCE_NDFLASH 0x160 33#define CLK_SOURCE_I2S3 0x3bc 34#define CLK_SOURCE_I2S4 0x3c0 35#define CLK_SOURCE_SPDIF_OUT 0x108 36#define CLK_SOURCE_SPDIF_IN 0x10c 37#define CLK_SOURCE_PWM 0x110 38#define CLK_SOURCE_ADX 0x638 39#define CLK_SOURCE_ADX1 0x670 40#define CLK_SOURCE_AMX 0x63c 41#define CLK_SOURCE_AMX1 0x674 42#define CLK_SOURCE_HDA 0x428 43#define CLK_SOURCE_HDA2CODEC_2X 0x3e4 44#define CLK_SOURCE_SBC1 0x134 45#define CLK_SOURCE_SBC2 0x118 46#define CLK_SOURCE_SBC3 0x11c 47#define CLK_SOURCE_SBC4 0x1b4 48#define CLK_SOURCE_SBC5 0x3c8 49#define CLK_SOURCE_SBC6 0x3cc 50#define CLK_SOURCE_SATA_OOB 0x420 51#define CLK_SOURCE_SATA 0x424 52#define CLK_SOURCE_NDSPEED 0x3f8 53#define CLK_SOURCE_VFIR 0x168 54#define CLK_SOURCE_SDMMC1 0x150 55#define CLK_SOURCE_SDMMC2 0x154 56#define CLK_SOURCE_SDMMC3 0x1bc 57#define CLK_SOURCE_SDMMC4 0x164 58#define CLK_SOURCE_CVE 0x140 59#define CLK_SOURCE_TVO 0x188 60#define CLK_SOURCE_TVDAC 0x194 61#define CLK_SOURCE_VDE 0x1c8 62#define CLK_SOURCE_CSITE 0x1d4 63#define CLK_SOURCE_LA 0x1f8 64#define CLK_SOURCE_TRACE 0x634 65#define CLK_SOURCE_OWR 0x1cc 66#define CLK_SOURCE_NOR 0x1d0 67#define CLK_SOURCE_MIPI 0x174 68#define CLK_SOURCE_I2C1 0x124 69#define CLK_SOURCE_I2C2 0x198 70#define CLK_SOURCE_I2C3 0x1b8 71#define CLK_SOURCE_I2C4 0x3c4 72#define CLK_SOURCE_I2C5 0x128 73#define CLK_SOURCE_I2C6 0x65c 74#define CLK_SOURCE_UARTA 0x178 75#define CLK_SOURCE_UARTB 0x17c 76#define CLK_SOURCE_UARTC 0x1a0 77#define CLK_SOURCE_UARTD 0x1c0 78#define CLK_SOURCE_UARTE 0x1c4 79#define CLK_SOURCE_3D 0x158 80#define CLK_SOURCE_2D 0x15c 81#define CLK_SOURCE_MPE 0x170 82#define CLK_SOURCE_UARTE 0x1c4 83#define CLK_SOURCE_VI_SENSOR 0x1a8 84#define CLK_SOURCE_VI 0x148 85#define CLK_SOURCE_EPP 0x16c 86#define CLK_SOURCE_MSENC 0x1f0 87#define CLK_SOURCE_TSEC 0x1f4 88#define CLK_SOURCE_HOST1X 0x180 89#define CLK_SOURCE_HDMI 0x18c 90#define CLK_SOURCE_DISP1 0x138 91#define CLK_SOURCE_DISP2 0x13c 92#define CLK_SOURCE_CILAB 0x614 93#define CLK_SOURCE_CILCD 0x618 94#define CLK_SOURCE_CILE 0x61c 95#define CLK_SOURCE_DSIALP 0x620 96#define CLK_SOURCE_DSIBLP 0x624 97#define CLK_SOURCE_TSENSOR 0x3b8 98#define CLK_SOURCE_D_AUDIO 0x3d0 99#define CLK_SOURCE_DAM0 0x3d8 100#define CLK_SOURCE_DAM1 0x3dc 101#define CLK_SOURCE_DAM2 0x3e0 102#define CLK_SOURCE_ACTMON 0x3e8 103#define CLK_SOURCE_EXTERN1 0x3ec 104#define CLK_SOURCE_EXTERN2 0x3f0 105#define CLK_SOURCE_EXTERN3 0x3f4 106#define CLK_SOURCE_I2CSLOW 0x3fc 107#define CLK_SOURCE_SE 0x42c 108#define CLK_SOURCE_MSELECT 0x3b4 109#define CLK_SOURCE_DFLL_REF 0x62c 110#define CLK_SOURCE_DFLL_SOC 0x630 111#define CLK_SOURCE_SOC_THERM 0x644 112#define CLK_SOURCE_XUSB_HOST_SRC 0x600 113#define CLK_SOURCE_XUSB_FALCON_SRC 0x604 114#define CLK_SOURCE_XUSB_FS_SRC 0x608 115#define CLK_SOURCE_XUSB_SS_SRC 0x610 116#define CLK_SOURCE_XUSB_DEV_SRC 0x60c 117#define CLK_SOURCE_ISP 0x144 118#define CLK_SOURCE_SOR0 0x414 119#define CLK_SOURCE_DPAUX 0x418 120#define CLK_SOURCE_SATA_OOB 0x420 121#define CLK_SOURCE_SATA 0x424 122#define CLK_SOURCE_ENTROPY 0x628 123#define CLK_SOURCE_VI_SENSOR2 0x658 124#define CLK_SOURCE_HDMI_AUDIO 0x668 125#define CLK_SOURCE_VIC03 0x678 126#define CLK_SOURCE_CLK72MHZ 0x66c 127 128#define MASK(x) (BIT(x) - 1) 129 130#define MUX(_name, _parents, _offset, \ 131 _clk_num, _gate_flags, _clk_id) \ 132 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 133 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 134 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\ 135 NULL) 136 137#define MUX_FLAGS(_name, _parents, _offset,\ 138 _clk_num, _gate_flags, _clk_id, flags)\ 139 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 140 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 141 _clk_num, _gate_flags, _clk_id, _parents##_idx, flags,\ 142 NULL) 143 144#define MUX8(_name, _parents, _offset, \ 145 _clk_num, _gate_flags, _clk_id) \ 146 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 147 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 148 _clk_num, _gate_flags, _clk_id, _parents##_idx, 0,\ 149 NULL) 150 151#define MUX8_NOGATE_LOCK(_name, _parents, _offset, _clk_id, _lock) \ 152 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \ 153 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 154 0, TEGRA_PERIPH_NO_GATE, _clk_id,\ 155 _parents##_idx, 0, _lock) 156 157#define INT(_name, _parents, _offset, \ 158 _clk_num, _gate_flags, _clk_id) \ 159 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 160 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 161 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ 162 _clk_id, _parents##_idx, 0, NULL) 163 164#define INT_FLAGS(_name, _parents, _offset,\ 165 _clk_num, _gate_flags, _clk_id, flags)\ 166 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 167 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 168 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ 169 _clk_id, _parents##_idx, flags, NULL) 170 171#define INT8(_name, _parents, _offset,\ 172 _clk_num, _gate_flags, _clk_id) \ 173 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 174 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 175 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ 176 _clk_id, _parents##_idx, 0, NULL) 177 178#define UART(_name, _parents, _offset,\ 179 _clk_num, _clk_id) \ 180 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 181 30, MASK(2), 0, 0, 16, 1, TEGRA_DIVIDER_UART| \ 182 TEGRA_DIVIDER_ROUND_UP, _clk_num, 0, _clk_id,\ 183 _parents##_idx, 0, NULL) 184 185#define I2C(_name, _parents, _offset,\ 186 _clk_num, _clk_id) \ 187 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 188 30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\ 189 _clk_num, 0, _clk_id, _parents##_idx, 0, NULL) 190 191#define XUSB(_name, _parents, _offset, \ 192 _clk_num, _gate_flags, _clk_id) \ 193 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \ 194 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_INT| \ 195 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags,\ 196 _clk_id, _parents##_idx, 0, NULL) 197 198#define AUDIO(_name, _offset, _clk_num,\ 199 _gate_flags, _clk_id) \ 200 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, mux_d_audio_clk, \ 201 _offset, 16, 0xE01F, 0, 0, 8, 1, \ 202 TEGRA_DIVIDER_ROUND_UP, _clk_num, _gate_flags, \ 203 _clk_id, mux_d_audio_clk_idx, 0, NULL) 204 205#define NODIV(_name, _parents, _offset, \ 206 _mux_shift, _mux_mask, _clk_num, \ 207 _gate_flags, _clk_id, _lock) \ 208 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 209 _mux_shift, _mux_mask, 0, 0, 0, 0, 0,\ 210 _clk_num, (_gate_flags) | TEGRA_PERIPH_NO_DIV,\ 211 _clk_id, _parents##_idx, 0, _lock) 212 213#define GATE(_name, _parent_name, \ 214 _clk_num, _gate_flags, _clk_id, _flags) \ 215 { \ 216 .name = _name, \ 217 .clk_id = _clk_id, \ 218 .p.parent_name = _parent_name, \ 219 .periph = TEGRA_CLK_PERIPH(0, 0, 0, 0, 0, 0, 0, \ 220 _clk_num, _gate_flags, NULL, NULL), \ 221 .flags = _flags \ 222 } 223 224#define PLLP_BASE 0xa0 225#define PLLP_MISC 0xac 226#define PLLP_OUTA 0xa4 227#define PLLP_OUTB 0xa8 228#define PLLP_OUTC 0x67c 229 230#define PLL_BASE_LOCK BIT(27) 231#define PLL_MISC_LOCK_ENABLE 18 232 233static DEFINE_SPINLOCK(PLLP_OUTA_lock); 234static DEFINE_SPINLOCK(PLLP_OUTB_lock); 235static DEFINE_SPINLOCK(PLLP_OUTC_lock); 236static DEFINE_SPINLOCK(sor0_lock); 237 238#define MUX_I2S_SPDIF(_id) \ 239static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \ 240 #_id, "pll_p",\ 241 "clk_m"}; 242MUX_I2S_SPDIF(audio0) 243MUX_I2S_SPDIF(audio1) 244MUX_I2S_SPDIF(audio2) 245MUX_I2S_SPDIF(audio3) 246MUX_I2S_SPDIF(audio4) 247MUX_I2S_SPDIF(audio) 248 249#define mux_pllaout0_audio0_2x_pllp_clkm_idx NULL 250#define mux_pllaout0_audio1_2x_pllp_clkm_idx NULL 251#define mux_pllaout0_audio2_2x_pllp_clkm_idx NULL 252#define mux_pllaout0_audio3_2x_pllp_clkm_idx NULL 253#define mux_pllaout0_audio4_2x_pllp_clkm_idx NULL 254#define mux_pllaout0_audio_2x_pllp_clkm_idx NULL 255 256static const char *mux_pllp_pllc_pllm_clkm[] = { 257 "pll_p", "pll_c", "pll_m", "clk_m" 258}; 259#define mux_pllp_pllc_pllm_clkm_idx NULL 260 261static const char *mux_pllp_pllc_pllm[] = { "pll_p", "pll_c", "pll_m" }; 262#define mux_pllp_pllc_pllm_idx NULL 263 264static const char *mux_pllp_pllc_clk32_clkm[] = { 265 "pll_p", "pll_c", "clk_32k", "clk_m" 266}; 267#define mux_pllp_pllc_clk32_clkm_idx NULL 268 269static const char *mux_plla_pllc_pllp_clkm[] = { 270 "pll_a_out0", "pll_c", "pll_p", "clk_m" 271}; 272#define mux_plla_pllc_pllp_clkm_idx mux_pllp_pllc_pllm_clkm_idx 273 274static const char *mux_pllp_pllc2_c_c3_pllm_clkm[] = { 275 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_m", "clk_m" 276}; 277static u32 mux_pllp_pllc2_c_c3_pllm_clkm_idx[] = { 278 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, 279}; 280 281static const char *mux_pllp_clkm[] = { 282 "pll_p", "clk_m" 283}; 284static u32 mux_pllp_clkm_idx[] = { 285 [0] = 0, [1] = 3, 286}; 287 288static const char *mux_pllm_pllc2_c_c3_pllp_plla[] = { 289 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0" 290}; 291#define mux_pllm_pllc2_c_c3_pllp_plla_idx mux_pllp_pllc2_c_c3_pllm_clkm_idx 292 293static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { 294 "pll_p", "pll_m", "pll_d_out0", "pll_a_out0", "pll_c", 295 "pll_d2_out0", "clk_m" 296}; 297#define mux_pllp_pllm_plld_plla_pllc_plld2_clkm_idx NULL 298 299static const char *mux_pllm_pllc_pllp_plla[] = { 300 "pll_m", "pll_c", "pll_p", "pll_a_out0" 301}; 302#define mux_pllm_pllc_pllp_plla_idx mux_pllp_pllc_pllm_clkm_idx 303 304static const char *mux_pllp_pllc_clkm[] = { 305 "pll_p", "pll_c", "pll_m" 306}; 307static u32 mux_pllp_pllc_clkm_idx[] = { 308 [0] = 0, [1] = 1, [2] = 3, 309}; 310 311static const char *mux_pllp_pllc_clkm_clk32[] = { 312 "pll_p", "pll_c", "clk_m", "clk_32k" 313}; 314#define mux_pllp_pllc_clkm_clk32_idx NULL 315 316static const char *mux_plla_clk32_pllp_clkm_plle[] = { 317 "pll_a_out0", "clk_32k", "pll_p", "clk_m", "pll_e_out0" 318}; 319#define mux_plla_clk32_pllp_clkm_plle_idx NULL 320 321static const char *mux_clkm_pllp_pllc_pllre[] = { 322 "clk_m", "pll_p", "pll_c", "pll_re_out" 323}; 324static u32 mux_clkm_pllp_pllc_pllre_idx[] = { 325 [0] = 0, [1] = 1, [2] = 3, [3] = 5, 326}; 327 328static const char *mux_clkm_48M_pllp_480M[] = { 329 "clk_m", "pll_u_48M", "pll_p", "pll_u_480M" 330}; 331static u32 mux_clkm_48M_pllp_480M_idx[] = { 332 [0] = 0, [1] = 2, [2] = 4, [3] = 6, 333}; 334 335static const char *mux_clkm_pllre_clk32_480M_pllc_ref[] = { 336 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref" 337}; 338static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = { 339 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7, 340}; 341 342static const char *mux_ss_60M[] = { 343 "xusb_ss_div2", "pll_u_60M" 344}; 345#define mux_ss_60M_idx NULL 346 347static const char *mux_d_audio_clk[] = { 348 "pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync", 349 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 350}; 351static u32 mux_d_audio_clk_idx[] = { 352 [0] = 0, [1] = 0x8000, [2] = 0xc000, [3] = 0xE000, [4] = 0xE001, 353 [5] = 0xE002, [6] = 0xE003, [7] = 0xE004, [8] = 0xE005, [9] = 0xE007, 354}; 355 356static const char *mux_pllp_plld_pllc_clkm[] = { 357 "pll_p", "pll_d_out0", "pll_c", "clk_m" 358}; 359#define mux_pllp_plld_pllc_clkm_idx NULL 360static const char *mux_pllm_pllc_pllp_plla_clkm_pllc4[] = { 361 "pll_m", "pll_c", "pll_p", "pll_a_out0", "clk_m", "pll_c4", 362}; 363static u32 mux_pllm_pllc_pllp_plla_clkm_pllc4_idx[] = { 364 [0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 6, [5] = 7, 365}; 366 367static const char *mux_pllp_clkm1[] = { 368 "pll_p", "clk_m", 369}; 370#define mux_pllp_clkm1_idx NULL 371 372static const char *mux_pllp3_pllc_clkm[] = { 373 "pll_p_out3", "pll_c", "pll_c2", "clk_m", 374}; 375#define mux_pllp3_pllc_clkm_idx NULL 376 377static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = { 378 "pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m" 379}; 380#define mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx NULL 381 382static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = { 383 "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4", 384}; 385static u32 mux_pllm_pllc2_c_c3_pllp_plla_pllc4_idx[] = { 386 [0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6, [6] = 7, 387}; 388 389static const char *mux_clkm_plldp_sor0lvds[] = { 390 "clk_m", "pll_dp", "sor0_lvds", 391}; 392#define mux_clkm_plldp_sor0lvds_idx NULL 393 394static struct tegra_periph_init_data periph_clks[] = { 395 AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio), 396 AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0), 397 AUDIO("dam1", CLK_SOURCE_DAM1, 109, TEGRA_PERIPH_ON_APB, tegra_clk_dam1), 398 AUDIO("dam2", CLK_SOURCE_DAM2, 110, TEGRA_PERIPH_ON_APB, tegra_clk_dam2), 399 I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, tegra_clk_i2c1), 400 I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, tegra_clk_i2c2), 401 I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3), 402 I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4), 403 I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5), 404 INT("vde", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde), 405 INT("vi", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi), 406 INT("epp", mux_pllm_pllc_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp), 407 INT("host1x", mux_pllm_pllc_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x), 408 INT("mpe", mux_pllm_pllc_pllp_plla, CLK_SOURCE_MPE, 60, 0, tegra_clk_mpe), 409 INT("2d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d), 410 INT("3d", mux_pllm_pllc_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d), 411 INT8("vde", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_VDE, 61, 0, tegra_clk_vde_8), 412 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_8), 413 INT8("vi", mux_pllm_pllc2_c_c3_pllp_plla_pllc4, CLK_SOURCE_VI, 20, 0, tegra_clk_vi_9), 414 INT8("epp", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_EPP, 19, 0, tegra_clk_epp_8), 415 INT8("msenc", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_MSENC, 91, TEGRA_PERIPH_WAR_1005168, tegra_clk_msenc), 416 INT8("tsec", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_TSEC, 83, 0, tegra_clk_tsec), 417 INT8("host1x", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_HOST1X, 28, 0, tegra_clk_host1x_8), 418 INT8("se", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SE, 127, TEGRA_PERIPH_ON_APB, tegra_clk_se), 419 INT8("2d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_2D, 21, 0, tegra_clk_gr2d_8), 420 INT8("3d", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_3D, 24, 0, tegra_clk_gr3d_8), 421 INT8("vic03", mux_pllm_pllc_pllp_plla_pllc2_c3_clkm, CLK_SOURCE_VIC03, 178, 0, tegra_clk_vic03), 422 INT_FLAGS("mselect", mux_pllp_clkm, CLK_SOURCE_MSELECT, 99, 0, tegra_clk_mselect, CLK_IGNORE_UNUSED), 423 MUX("i2s0", mux_pllaout0_audio0_2x_pllp_clkm, CLK_SOURCE_I2S0, 30, TEGRA_PERIPH_ON_APB, tegra_clk_i2s0), 424 MUX("i2s1", mux_pllaout0_audio1_2x_pllp_clkm, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, tegra_clk_i2s1), 425 MUX("i2s2", mux_pllaout0_audio2_2x_pllp_clkm, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, tegra_clk_i2s2), 426 MUX("i2s3", mux_pllaout0_audio3_2x_pllp_clkm, CLK_SOURCE_I2S3, 101, TEGRA_PERIPH_ON_APB, tegra_clk_i2s3), 427 MUX("i2s4", mux_pllaout0_audio4_2x_pllp_clkm, CLK_SOURCE_I2S4, 102, TEGRA_PERIPH_ON_APB, tegra_clk_i2s4), 428 MUX("spdif_out", mux_pllaout0_audio_2x_pllp_clkm, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_out), 429 MUX("spdif_in", mux_pllp_pllc_pllm, CLK_SOURCE_SPDIF_IN, 10, TEGRA_PERIPH_ON_APB, tegra_clk_spdif_in), 430 MUX("pwm", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_PWM, 17, TEGRA_PERIPH_ON_APB, tegra_clk_pwm), 431 MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx), 432 MUX("amx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX, 153, TEGRA_PERIPH_ON_APB, tegra_clk_amx), 433 MUX("hda", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA, 125, TEGRA_PERIPH_ON_APB, tegra_clk_hda), 434 MUX("hda2codec_2x", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_HDA2CODEC_2X, 111, TEGRA_PERIPH_ON_APB, tegra_clk_hda2codec_2x), 435 MUX("vfir", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_VFIR, 7, TEGRA_PERIPH_ON_APB, tegra_clk_vfir), 436 MUX("sdmmc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1), 437 MUX("sdmmc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2), 438 MUX("sdmmc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3), 439 MUX("sdmmc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4), 440 MUX("la", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_LA, 76, TEGRA_PERIPH_ON_APB, tegra_clk_la), 441 MUX("trace", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_TRACE, 77, TEGRA_PERIPH_ON_APB, tegra_clk_trace), 442 MUX("owr", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_OWR, 71, TEGRA_PERIPH_ON_APB, tegra_clk_owr), 443 MUX("nor", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NOR, 42, 0, tegra_clk_nor), 444 MUX("mipi", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_MIPI, 50, TEGRA_PERIPH_ON_APB, tegra_clk_mipi), 445 MUX("vi_sensor", mux_pllm_pllc_pllp_plla, CLK_SOURCE_VI_SENSOR, 20, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor), 446 MUX("cilab", mux_pllp_pllc_clkm, CLK_SOURCE_CILAB, 144, 0, tegra_clk_cilab), 447 MUX("cilcd", mux_pllp_pllc_clkm, CLK_SOURCE_CILCD, 145, 0, tegra_clk_cilcd), 448 MUX("cile", mux_pllp_pllc_clkm, CLK_SOURCE_CILE, 146, 0, tegra_clk_cile), 449 MUX("dsialp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIALP, 147, 0, tegra_clk_dsialp), 450 MUX("dsiblp", mux_pllp_pllc_clkm, CLK_SOURCE_DSIBLP, 148, 0, tegra_clk_dsiblp), 451 MUX("tsensor", mux_pllp_pllc_clkm_clk32, CLK_SOURCE_TSENSOR, 100, TEGRA_PERIPH_ON_APB, tegra_clk_tsensor), 452 MUX("actmon", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_ACTMON, 119, 0, tegra_clk_actmon), 453 MUX("dfll_ref", mux_pllp_clkm, CLK_SOURCE_DFLL_REF, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_ref), 454 MUX("dfll_soc", mux_pllp_clkm, CLK_SOURCE_DFLL_SOC, 155, TEGRA_PERIPH_ON_APB, tegra_clk_dfll_soc), 455 MUX("i2cslow", mux_pllp_pllc_clk32_clkm, CLK_SOURCE_I2CSLOW, 81, TEGRA_PERIPH_ON_APB, tegra_clk_i2cslow), 456 MUX("sbc1", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1), 457 MUX("sbc2", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2), 458 MUX("sbc3", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3), 459 MUX("sbc4", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4), 460 MUX("sbc5", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5), 461 MUX("sbc6", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6), 462 MUX("cve", mux_pllp_plld_pllc_clkm, CLK_SOURCE_CVE, 49, 0, tegra_clk_cve), 463 MUX("tvo", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVO, 49, 0, tegra_clk_tvo), 464 MUX("tvdac", mux_pllp_plld_pllc_clkm, CLK_SOURCE_TVDAC, 53, 0, tegra_clk_tvdac), 465 MUX("ndflash", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash), 466 MUX("ndspeed", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed), 467 MUX("sata_oob", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA_OOB, 123, TEGRA_PERIPH_ON_APB, tegra_clk_sata_oob), 468 MUX("sata", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_SATA, 124, TEGRA_PERIPH_ON_APB, tegra_clk_sata), 469 MUX("adx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX1, 180, TEGRA_PERIPH_ON_APB, tegra_clk_adx1), 470 MUX("amx1", mux_plla_pllc_pllp_clkm, CLK_SOURCE_AMX1, 185, TEGRA_PERIPH_ON_APB, tegra_clk_amx1), 471 MUX("vi_sensor2", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR2, 165, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor2), 472 MUX8("sdmmc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC1, 14, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc1_8), 473 MUX8("sdmmc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC2, 9, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc2_8), 474 MUX8("sdmmc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC3, 69, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc3_8), 475 MUX8("sdmmc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SDMMC4, 15, TEGRA_PERIPH_ON_APB, tegra_clk_sdmmc4_8), 476 MUX8("sbc1", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC1, 41, TEGRA_PERIPH_ON_APB, tegra_clk_sbc1_8), 477 MUX8("sbc2", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC2, 44, TEGRA_PERIPH_ON_APB, tegra_clk_sbc2_8), 478 MUX8("sbc3", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC3, 46, TEGRA_PERIPH_ON_APB, tegra_clk_sbc3_8), 479 MUX8("sbc4", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC4, 68, TEGRA_PERIPH_ON_APB, tegra_clk_sbc4_8), 480 MUX8("sbc5", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC5, 104, TEGRA_PERIPH_ON_APB, tegra_clk_sbc5_8), 481 MUX8("sbc6", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_SBC6, 105, TEGRA_PERIPH_ON_APB, tegra_clk_sbc6_8), 482 MUX8("ndflash", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDFLASH, 13, TEGRA_PERIPH_ON_APB, tegra_clk_ndflash_8), 483 MUX8("ndspeed", mux_pllp_pllc2_c_c3_pllm_clkm, CLK_SOURCE_NDSPEED, 80, TEGRA_PERIPH_ON_APB, tegra_clk_ndspeed_8), 484 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi), 485 MUX8("extern1", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN1, 120, 0, tegra_clk_extern1), 486 MUX8("extern2", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN2, 121, 0, tegra_clk_extern2), 487 MUX8("extern3", mux_plla_clk32_pllp_clkm_plle, CLK_SOURCE_EXTERN3, 122, 0, tegra_clk_extern3), 488 MUX8("soc_therm", mux_pllm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm), 489 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8), 490 MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8), 491 MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy), 492 MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio), 493 MUX8("clk72mhz", mux_pllp3_pllc_clkm, CLK_SOURCE_CLK72MHZ, 177, TEGRA_PERIPH_NO_RESET, tegra_clk_clk72Mhz), 494 MUX8_NOGATE_LOCK("sor0_lvds", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_SOR0, tegra_clk_sor0_lvds, &sor0_lock), 495 MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED), 496 NODIV("disp1", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP1, 29, 7, 27, 0, tegra_clk_disp1, NULL), 497 NODIV("disp2", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_DISP2, 29, 7, 26, 0, tegra_clk_disp2, NULL), 498 NODIV("sor0", mux_clkm_plldp_sor0lvds, CLK_SOURCE_SOR0, 14, 3, 182, 0, tegra_clk_sor0, &sor0_lock), 499 UART("uarta", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTA, 6, tegra_clk_uarta), 500 UART("uartb", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTB, 7, tegra_clk_uartb), 501 UART("uartc", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTC, 55, tegra_clk_uartc), 502 UART("uartd", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTD, 65, tegra_clk_uartd), 503 UART("uarte", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_UARTE, 66, tegra_clk_uarte), 504 XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_host_src), 505 XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src), 506 XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src), 507 XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src), 508 NODIV("xusb_hs_src", mux_ss_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL), 509 XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src), 510}; 511 512static struct tegra_periph_init_data gate_clks[] = { 513 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0), 514 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, 0), 515 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0), 516 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0), 517 GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0), 518 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0), 519 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0), 520 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0), 521 GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0), 522 GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0), 523 GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0), 524 GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0), 525 GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0), 526 GATE("mipi-cal", "clk_m", 56, 0, tegra_clk_mipi_cal, 0), 527 GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0), 528 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0), 529 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0), 530 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0), 531 GATE("afi", "clk_m", 72, 0, tegra_clk_afi, 0), 532 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0), 533 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0), 534 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0), 535 GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0), 536 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0), 537 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0), 538 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0), 539 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED), 540 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0), 541 GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0), 542 GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0), 543 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0), 544 GATE("dpaux", "clk_m", 181, 0, tegra_clk_dpaux, 0), 545 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0), 546}; 547 548struct pll_out_data { 549 char *div_name; 550 char *pll_out_name; 551 u32 offset; 552 int clk_id; 553 u8 div_shift; 554 u8 div_flags; 555 u8 rst_shift; 556 spinlock_t *lock; 557}; 558 559#define PLL_OUT(_num, _offset, _div_shift, _div_flags, _rst_shift, _id) \ 560 {\ 561 .div_name = "pll_p_out" #_num "_div",\ 562 .pll_out_name = "pll_p_out" #_num,\ 563 .offset = _offset,\ 564 .div_shift = _div_shift,\ 565 .div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\ 566 TEGRA_DIVIDER_ROUND_UP,\ 567 .rst_shift = _rst_shift,\ 568 .clk_id = tegra_clk_ ## _id,\ 569 .lock = &_offset ##_lock,\ 570 } 571 572static struct pll_out_data pllp_out_clks[] = { 573 PLL_OUT(1, PLLP_OUTA, 8, 0, 0, pll_p_out1), 574 PLL_OUT(2, PLLP_OUTA, 24, 0, 16, pll_p_out2), 575 PLL_OUT(2, PLLP_OUTA, 24, TEGRA_DIVIDER_INT, 16, pll_p_out2_int), 576 PLL_OUT(3, PLLP_OUTB, 8, 0, 0, pll_p_out3), 577 PLL_OUT(4, PLLP_OUTB, 24, 0, 16, pll_p_out4), 578 PLL_OUT(5, PLLP_OUTC, 24, 0, 16, pll_p_out5), 579}; 580 581static void __init periph_clk_init(void __iomem *clk_base, 582 struct tegra_clk *tegra_clks) 583{ 584 int i; 585 struct clk *clk; 586 struct clk **dt_clk; 587 588 for (i = 0; i < ARRAY_SIZE(periph_clks); i++) { 589 struct tegra_clk_periph_regs *bank; 590 struct tegra_periph_init_data *data; 591 592 data = periph_clks + i; 593 594 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); 595 if (!dt_clk) 596 continue; 597 598 bank = get_reg_bank(data->periph.gate.clk_num); 599 if (!bank) 600 continue; 601 602 data->periph.gate.regs = bank; 603 clk = tegra_clk_register_periph(data->name, 604 data->p.parent_names, data->num_parents, 605 &data->periph, clk_base, data->offset, 606 data->flags); 607 *dt_clk = clk; 608 } 609} 610 611static void __init gate_clk_init(void __iomem *clk_base, 612 struct tegra_clk *tegra_clks) 613{ 614 int i; 615 struct clk *clk; 616 struct clk **dt_clk; 617 618 for (i = 0; i < ARRAY_SIZE(gate_clks); i++) { 619 struct tegra_periph_init_data *data; 620 621 data = gate_clks + i; 622 623 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); 624 if (!dt_clk) 625 continue; 626 627 clk = tegra_clk_register_periph_gate(data->name, 628 data->p.parent_name, data->periph.gate.flags, 629 clk_base, data->flags, 630 data->periph.gate.clk_num, 631 periph_clk_enb_refcnt); 632 *dt_clk = clk; 633 } 634} 635 636static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, 637 struct tegra_clk *tegra_clks, 638 struct tegra_clk_pll_params *pll_params) 639{ 640 struct clk *clk; 641 struct clk **dt_clk; 642 int i; 643 644 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_p, tegra_clks); 645 if (dt_clk) { 646 /* PLLP */ 647 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, 648 pmc_base, 0, pll_params, NULL); 649 clk_register_clkdev(clk, "pll_p", NULL); 650 *dt_clk = clk; 651 } 652 653 for (i = 0; i < ARRAY_SIZE(pllp_out_clks); i++) { 654 struct pll_out_data *data; 655 656 data = pllp_out_clks + i; 657 658 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); 659 if (!dt_clk) 660 continue; 661 662 clk = tegra_clk_register_divider(data->div_name, "pll_p", 663 clk_base + data->offset, 0, data->div_flags, 664 data->div_shift, 8, 1, data->lock); 665 clk = tegra_clk_register_pll_out(data->pll_out_name, 666 data->div_name, clk_base + data->offset, 667 data->rst_shift + 1, data->rst_shift, 668 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0, 669 data->lock); 670 *dt_clk = clk; 671 } 672} 673 674void __init tegra_periph_clk_init(void __iomem *clk_base, 675 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 676 struct tegra_clk_pll_params *pll_params) 677{ 678 init_pllp(clk_base, pmc_base, tegra_clks, pll_params); 679 periph_clk_init(clk_base, tegra_clks); 680 gate_clk_init(clk_base, tegra_clks); 681} 682