1/* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Author: Thomas Abraham <thomas.ab@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Common Clock Framework support for Exynos5440 SoC. 10*/ 11 12#include <dt-bindings/clock/exynos5440.h> 13#include <linux/clk-provider.h> 14#include <linux/of.h> 15#include <linux/of_address.h> 16#include <linux/notifier.h> 17#include <linux/reboot.h> 18 19#include "clk.h" 20#include "clk-pll.h" 21 22#define CLKEN_OV_VAL 0xf8 23#define CPU_CLK_STATUS 0xfc 24#define MISC_DOUT1 0x558 25 26static void __iomem *reg_base; 27 28/* parent clock name list */ 29PNAME(mout_armclk_p) = { "cplla", "cpllb" }; 30PNAME(mout_spi_p) = { "div125", "div200" }; 31 32/* fixed rate clocks generated outside the soc */ 33static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = { 34 FRATE(0, "xtal", NULL, CLK_IS_ROOT, 0), 35}; 36 37/* fixed rate clocks */ 38static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = { 39 FRATE(0, "ppll", NULL, CLK_IS_ROOT, 1000000000), 40 FRATE(0, "usb_phy0", NULL, CLK_IS_ROOT, 60000000), 41 FRATE(0, "usb_phy1", NULL, CLK_IS_ROOT, 60000000), 42 FRATE(0, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000), 43 FRATE(0, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000), 44}; 45 46/* fixed factor clocks */ 47static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = { 48 FFACTOR(0, "div250", "ppll", 1, 4, 0), 49 FFACTOR(0, "div200", "ppll", 1, 5, 0), 50 FFACTOR(0, "div125", "div250", 1, 2, 0), 51}; 52 53/* mux clocks */ 54static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = { 55 MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), 56 MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p, 57 CPU_CLK_STATUS, 0, 1, "armclk"), 58}; 59 60/* divider clocks */ 61static struct samsung_div_clock exynos5440_div_clks[] __initdata = { 62 DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2), 63}; 64 65/* gate clocks */ 66static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = { 67 GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0), 68 GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0), 69 GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0), 70 GATE(CLK_B_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0), 71 GATE(CLK_B_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0), 72 GATE(CLK_B_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0), 73 GATE(CLK_SATA, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0), 74 GATE(CLK_USB, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0), 75 GATE(CLK_GMAC0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0), 76 GATE(CLK_CS250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0), 77 GATE(CLK_PB0_250_O, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0), 78 GATE(CLK_PR0_250_O, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0), 79 GATE(CLK_PR1_250_O, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0), 80 GATE(CLK_B_250_O, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0), 81 GATE(CLK_B_125_O, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0), 82 GATE(CLK_B_200_O, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0), 83 GATE(CLK_SATA_O, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0), 84 GATE(CLK_USB_O, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0), 85 GATE(CLK_GMAC0_O, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0), 86 GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0), 87}; 88 89static const struct of_device_id ext_clk_match[] __initconst = { 90 { .compatible = "samsung,clock-xtal", .data = (void *)0, }, 91 {}, 92}; 93 94static int exynos5440_clk_restart_notify(struct notifier_block *this, 95 unsigned long code, void *unused) 96{ 97 u32 val, status; 98 99 status = readl_relaxed(reg_base + 0xbc); 100 val = readl_relaxed(reg_base + 0xcc); 101 val = (val & 0xffff0000) | (status & 0xffff); 102 writel_relaxed(val, reg_base + 0xcc); 103 104 return NOTIFY_DONE; 105} 106 107/* 108 * Exynos5440 Clock restart notifier, handles restart functionality 109 */ 110static struct notifier_block exynos5440_clk_restart_handler = { 111 .notifier_call = exynos5440_clk_restart_notify, 112 .priority = 128, 113}; 114 115/* register exynos5440 clocks */ 116static void __init exynos5440_clk_init(struct device_node *np) 117{ 118 struct samsung_clk_provider *ctx; 119 120 reg_base = of_iomap(np, 0); 121 if (!reg_base) { 122 pr_err("%s: failed to map clock controller registers," 123 " aborting clock initialization\n", __func__); 124 return; 125 } 126 127 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); 128 if (!ctx) 129 panic("%s: unable to allocate context.\n", __func__); 130 131 samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks, 132 ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match); 133 134 samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10); 135 samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10); 136 137 samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks, 138 ARRAY_SIZE(exynos5440_fixed_rate_clks)); 139 samsung_clk_register_fixed_factor(ctx, exynos5440_fixed_factor_clks, 140 ARRAY_SIZE(exynos5440_fixed_factor_clks)); 141 samsung_clk_register_mux(ctx, exynos5440_mux_clks, 142 ARRAY_SIZE(exynos5440_mux_clks)); 143 samsung_clk_register_div(ctx, exynos5440_div_clks, 144 ARRAY_SIZE(exynos5440_div_clks)); 145 samsung_clk_register_gate(ctx, exynos5440_gate_clks, 146 ARRAY_SIZE(exynos5440_gate_clks)); 147 148 samsung_clk_of_add_provider(np, ctx); 149 150 if (register_restart_handler(&exynos5440_clk_restart_handler)) 151 pr_warn("exynos5440 clock can't register restart handler\n"); 152 153 pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk")); 154 pr_info("exynos5440 clock initialization complete\n"); 155} 156CLK_OF_DECLARE(exynos5440_clk, "samsung,exynos5440-clock", exynos5440_clk_init); 157