1/*
2 * Hitachi UL SolutionEngine 7722 FPGA IRQ Support.
3 *
4 * Copyright (C) 2007  Nobuhiro Iwamatsu
5 * Copyright (C) 2012  Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License.  See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#define DRV_NAME "SE7722-FPGA"
12#define pr_fmt(fmt) DRV_NAME ": " fmt
13
14#include <linux/init.h>
15#include <linux/irq.h>
16#include <linux/interrupt.h>
17#include <linux/irqdomain.h>
18#include <linux/io.h>
19#include <linux/err.h>
20#include <asm/sizes.h>
21#include <mach-se/mach/se7722.h>
22
23#define IRQ01_BASE_ADDR	0x11800000
24#define IRQ01_MODE_REG	0
25#define IRQ01_STS_REG	4
26#define IRQ01_MASK_REG	8
27
28static void __iomem *se7722_irq_regs;
29struct irq_domain *se7722_irq_domain;
30
31static void se7722_irq_demux(struct irq_desc *desc)
32{
33	struct irq_data *data = irq_desc_get_irq_data(desc);
34	struct irq_chip *chip = irq_data_get_irq_chip(data);
35	unsigned long mask;
36	int bit;
37
38	chip->irq_mask_ack(data);
39
40	mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);
41
42	for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)
43		generic_handle_irq(irq_linear_revmap(se7722_irq_domain, bit));
44
45	chip->irq_unmask(data);
46}
47
48static void __init se7722_domain_init(void)
49{
50	int i;
51
52	se7722_irq_domain = irq_domain_add_linear(NULL, SE7722_FPGA_IRQ_NR,
53						  &irq_domain_simple_ops, NULL);
54	if (unlikely(!se7722_irq_domain)) {
55		printk("Failed to get IRQ domain\n");
56		return;
57	}
58
59	for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
60		int irq = irq_create_mapping(se7722_irq_domain, i);
61
62		if (unlikely(irq == 0)) {
63			printk("Failed to allocate IRQ %d\n", i);
64			return;
65		}
66	}
67}
68
69static void __init se7722_gc_init(void)
70{
71	struct irq_chip_generic *gc;
72	struct irq_chip_type *ct;
73	unsigned int irq_base;
74
75	irq_base = irq_linear_revmap(se7722_irq_domain, 0);
76
77	gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs,
78				    handle_level_irq);
79	if (unlikely(!gc))
80		return;
81
82	ct = gc->chip_types;
83	ct->chip.irq_mask = irq_gc_mask_set_bit;
84	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
85
86	ct->regs.mask = IRQ01_MASK_REG;
87
88	irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR),
89			       IRQ_GC_INIT_MASK_CACHE,
90			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);
91
92	irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);
93	irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
94
95	irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);
96	irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
97}
98
99/*
100 * Initialize FPGA IRQs
101 */
102void __init init_se7722_IRQ(void)
103{
104	se7722_irq_regs = ioremap(IRQ01_BASE_ADDR, SZ_16);
105	if (unlikely(!se7722_irq_regs)) {
106		printk("Failed to remap IRQ01 regs\n");
107		return;
108	}
109
110	/*
111	 * All FPGA IRQs disabled by default
112	 */
113	iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG);
114
115	__raw_writew(0x2000, 0xb03fffec);  /* mrshpc irq enable */
116
117	se7722_domain_init();
118	se7722_gc_init();
119}
120