1/*
2 * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
3 *
4 * Author: Tony Li <tony.li@freescale.com>
5 *	   Jason Jin <Jason.jin@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 */
13#ifndef _POWERPC_SYSDEV_FSL_MSI_H
14#define _POWERPC_SYSDEV_FSL_MSI_H
15
16#include <linux/of.h>
17#include <asm/msi_bitmap.h>
18
19#define NR_MSI_REG_MSIIR	8  /* MSIIR can index 8 MSI registers */
20#define NR_MSI_REG_MSIIR1	16 /* MSIIR1 can index 16 MSI registers */
21#define NR_MSI_REG_MAX		NR_MSI_REG_MSIIR1
22#define IRQS_PER_MSI_REG	32
23#define NR_MSI_IRQS_MAX	(NR_MSI_REG_MAX * IRQS_PER_MSI_REG)
24
25#define FSL_PIC_IP_MASK   0x0000000F
26#define FSL_PIC_IP_MPIC   0x00000001
27#define FSL_PIC_IP_IPIC   0x00000002
28#define FSL_PIC_IP_VMPIC  0x00000003
29
30#define MSI_HW_ERRATA_ENDIAN 0x00000010
31
32struct fsl_msi_cascade_data;
33
34struct fsl_msi {
35	struct irq_domain *irqhost;
36
37	unsigned long cascade_irq;
38
39	u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
40	u32 ibs_shift; /* Shift of interrupt bit select */
41	u32 srs_shift; /* Shift of the shared interrupt register select */
42	void __iomem *msi_regs;
43	u32 feature;
44	struct fsl_msi_cascade_data *cascade_array[NR_MSI_REG_MAX];
45
46	struct msi_bitmap bitmap;
47
48	struct list_head list;          /* support multiple MSI banks */
49
50	phandle phandle;
51};
52
53#endif /* _POWERPC_SYSDEV_FSL_MSI_H */
54
55