1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2015
16 *
17 * Authors: Gavin Shan <gwshan@linux.vnet.ibm.com>
18 */
19
20#ifndef _ASM_POWERPC_EEH_H
21#define _ASM_POWERPC_EEH_H
22
23/* PE states */
24#define EEH_PE_STATE_NORMAL		0	/* Normal state		*/
25#define EEH_PE_STATE_RESET		1	/* PE reset asserted	*/
26#define EEH_PE_STATE_STOPPED_IO_DMA	2	/* Frozen PE		*/
27#define EEH_PE_STATE_STOPPED_DMA	4	/* Stopped DMA only	*/
28#define EEH_PE_STATE_UNAVAIL		5	/* Unavailable		*/
29
30/* EEH error types and functions */
31#define EEH_ERR_TYPE_32			0       /* 32-bits error	*/
32#define EEH_ERR_TYPE_64			1       /* 64-bits error	*/
33#define EEH_ERR_FUNC_MIN		0
34#define EEH_ERR_FUNC_LD_MEM_ADDR	0	/* Memory load	*/
35#define EEH_ERR_FUNC_LD_MEM_DATA	1
36#define EEH_ERR_FUNC_LD_IO_ADDR		2	/* IO load	*/
37#define EEH_ERR_FUNC_LD_IO_DATA		3
38#define EEH_ERR_FUNC_LD_CFG_ADDR	4	/* Config load	*/
39#define EEH_ERR_FUNC_LD_CFG_DATA	5
40#define EEH_ERR_FUNC_ST_MEM_ADDR	6	/* Memory store	*/
41#define EEH_ERR_FUNC_ST_MEM_DATA	7
42#define EEH_ERR_FUNC_ST_IO_ADDR		8	/* IO store	*/
43#define EEH_ERR_FUNC_ST_IO_DATA		9
44#define EEH_ERR_FUNC_ST_CFG_ADDR	10	/* Config store	*/
45#define EEH_ERR_FUNC_ST_CFG_DATA	11
46#define EEH_ERR_FUNC_DMA_RD_ADDR	12	/* DMA read	*/
47#define EEH_ERR_FUNC_DMA_RD_DATA	13
48#define EEH_ERR_FUNC_DMA_RD_MASTER	14
49#define EEH_ERR_FUNC_DMA_RD_TARGET	15
50#define EEH_ERR_FUNC_DMA_WR_ADDR	16	/* DMA write	*/
51#define EEH_ERR_FUNC_DMA_WR_DATA	17
52#define EEH_ERR_FUNC_DMA_WR_MASTER	18
53#define EEH_ERR_FUNC_DMA_WR_TARGET	19
54#define EEH_ERR_FUNC_MAX		19
55
56#endif /* _ASM_POWERPC_EEH_H */
57