1/* 2 * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation. 3 * Copyright 2001-2012 IBM Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20#ifndef _POWERPC_EEH_H 21#define _POWERPC_EEH_H 22#ifdef __KERNEL__ 23 24#include <linux/init.h> 25#include <linux/list.h> 26#include <linux/string.h> 27#include <linux/time.h> 28#include <linux/atomic.h> 29 30#include <uapi/asm/eeh.h> 31 32struct pci_dev; 33struct pci_bus; 34struct pci_dn; 35 36#ifdef CONFIG_EEH 37 38/* EEH subsystem flags */ 39#define EEH_ENABLED 0x01 /* EEH enabled */ 40#define EEH_FORCE_DISABLED 0x02 /* EEH disabled */ 41#define EEH_PROBE_MODE_DEV 0x04 /* From PCI device */ 42#define EEH_PROBE_MODE_DEVTREE 0x08 /* From device tree */ 43#define EEH_VALID_PE_ZERO 0x10 /* PE#0 is valid */ 44#define EEH_ENABLE_IO_FOR_LOG 0x20 /* Enable IO for log */ 45#define EEH_EARLY_DUMP_LOG 0x40 /* Dump log immediately */ 46 47/* 48 * Delay for PE reset, all in ms 49 * 50 * PCI specification has reset hold time of 100 milliseconds. 51 * We have 250 milliseconds here. The PCI bus settlement time 52 * is specified as 1.5 seconds and we have 1.8 seconds. 53 */ 54#define EEH_PE_RST_HOLD_TIME 250 55#define EEH_PE_RST_SETTLE_TIME 1800 56 57/* 58 * The struct is used to trace PE related EEH functionality. 59 * In theory, there will have one instance of the struct to 60 * be created against particular PE. In nature, PEs corelate 61 * to each other. the struct has to reflect that hierarchy in 62 * order to easily pick up those affected PEs when one particular 63 * PE has EEH errors. 64 * 65 * Also, one particular PE might be composed of PCI device, PCI 66 * bus and its subordinate components. The struct also need ship 67 * the information. Further more, one particular PE is only meaingful 68 * in the corresponding PHB. Therefore, the root PEs should be created 69 * against existing PHBs in on-to-one fashion. 70 */ 71#define EEH_PE_INVALID (1 << 0) /* Invalid */ 72#define EEH_PE_PHB (1 << 1) /* PHB PE */ 73#define EEH_PE_DEVICE (1 << 2) /* Device PE */ 74#define EEH_PE_BUS (1 << 3) /* Bus PE */ 75 76#define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */ 77#define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */ 78#define EEH_PE_CFG_BLOCKED (1 << 2) /* Block config access */ 79#define EEH_PE_RESET (1 << 3) /* PE reset in progress */ 80 81#define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */ 82#define EEH_PE_CFG_RESTRICTED (1 << 9) /* Block config on error */ 83#define EEH_PE_REMOVED (1 << 10) /* Removed permanently */ 84#define EEH_PE_PRI_BUS (1 << 11) /* Cached primary bus */ 85 86struct eeh_pe { 87 int type; /* PE type: PHB/Bus/Device */ 88 int state; /* PE EEH dependent mode */ 89 int config_addr; /* Traditional PCI address */ 90 int addr; /* PE configuration address */ 91 struct pci_controller *phb; /* Associated PHB */ 92 struct pci_bus *bus; /* Top PCI bus for bus PE */ 93 int check_count; /* Times of ignored error */ 94 int freeze_count; /* Times of froze up */ 95 struct timeval tstamp; /* Time on first-time freeze */ 96 int false_positives; /* Times of reported #ff's */ 97 atomic_t pass_dev_cnt; /* Count of passed through devs */ 98 struct eeh_pe *parent; /* Parent PE */ 99 void *data; /* PE auxillary data */ 100 struct list_head child_list; /* Link PE to the child list */ 101 struct list_head edevs; /* Link list of EEH devices */ 102 struct list_head child; /* Child PEs */ 103}; 104 105#define eeh_pe_for_each_dev(pe, edev, tmp) \ 106 list_for_each_entry_safe(edev, tmp, &pe->edevs, list) 107 108static inline bool eeh_pe_passed(struct eeh_pe *pe) 109{ 110 return pe ? !!atomic_read(&pe->pass_dev_cnt) : false; 111} 112 113/* 114 * The struct is used to trace EEH state for the associated 115 * PCI device node or PCI device. In future, it might 116 * represent PE as well so that the EEH device to form 117 * another tree except the currently existing tree of PCI 118 * buses and PCI devices 119 */ 120#define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */ 121#define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */ 122#define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */ 123#define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */ 124#define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */ 125 126#define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */ 127#define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */ 128#define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */ 129 130struct eeh_dev { 131 int mode; /* EEH mode */ 132 int class_code; /* Class code of the device */ 133 int config_addr; /* Config address */ 134 int pe_config_addr; /* PE config address */ 135 u32 config_space[16]; /* Saved PCI config space */ 136 int pcix_cap; /* Saved PCIx capability */ 137 int pcie_cap; /* Saved PCIe capability */ 138 int aer_cap; /* Saved AER capability */ 139 struct eeh_pe *pe; /* Associated PE */ 140 struct list_head list; /* Form link list in the PE */ 141 struct pci_controller *phb; /* Associated PHB */ 142 struct pci_dn *pdn; /* Associated PCI device node */ 143 struct pci_dev *pdev; /* Associated PCI device */ 144 struct pci_bus *bus; /* PCI bus for partial hotplug */ 145}; 146 147static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev) 148{ 149 return edev ? edev->pdn : NULL; 150} 151 152static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev) 153{ 154 return edev ? edev->pdev : NULL; 155} 156 157static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev) 158{ 159 return edev ? edev->pe : NULL; 160} 161 162/* Return values from eeh_ops::next_error */ 163enum { 164 EEH_NEXT_ERR_NONE = 0, 165 EEH_NEXT_ERR_INF, 166 EEH_NEXT_ERR_FROZEN_PE, 167 EEH_NEXT_ERR_FENCED_PHB, 168 EEH_NEXT_ERR_DEAD_PHB, 169 EEH_NEXT_ERR_DEAD_IOC 170}; 171 172/* 173 * The struct is used to trace the registered EEH operation 174 * callback functions. Actually, those operation callback 175 * functions are heavily platform dependent. That means the 176 * platform should register its own EEH operation callback 177 * functions before any EEH further operations. 178 */ 179#define EEH_OPT_DISABLE 0 /* EEH disable */ 180#define EEH_OPT_ENABLE 1 /* EEH enable */ 181#define EEH_OPT_THAW_MMIO 2 /* MMIO enable */ 182#define EEH_OPT_THAW_DMA 3 /* DMA enable */ 183#define EEH_OPT_FREEZE_PE 4 /* Freeze PE */ 184#define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */ 185#define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */ 186#define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */ 187#define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */ 188#define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */ 189#define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */ 190#define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */ 191#define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */ 192#define EEH_RESET_HOT 1 /* Hot reset */ 193#define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */ 194#define EEH_LOG_TEMP 1 /* EEH temporary error log */ 195#define EEH_LOG_PERM 2 /* EEH permanent error log */ 196 197struct eeh_ops { 198 char *name; 199 int (*init)(void); 200 int (*post_init)(void); 201 void* (*probe)(struct pci_dn *pdn, void *data); 202 int (*set_option)(struct eeh_pe *pe, int option); 203 int (*get_pe_addr)(struct eeh_pe *pe); 204 int (*get_state)(struct eeh_pe *pe, int *state); 205 int (*reset)(struct eeh_pe *pe, int option); 206 int (*wait_state)(struct eeh_pe *pe, int max_wait); 207 int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len); 208 int (*configure_bridge)(struct eeh_pe *pe); 209 int (*err_inject)(struct eeh_pe *pe, int type, int func, 210 unsigned long addr, unsigned long mask); 211 int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val); 212 int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val); 213 int (*next_error)(struct eeh_pe **pe); 214 int (*restore_config)(struct pci_dn *pdn); 215}; 216 217extern int eeh_subsystem_flags; 218extern int eeh_max_freezes; 219extern struct eeh_ops *eeh_ops; 220extern raw_spinlock_t confirm_error_lock; 221 222static inline void eeh_add_flag(int flag) 223{ 224 eeh_subsystem_flags |= flag; 225} 226 227static inline void eeh_clear_flag(int flag) 228{ 229 eeh_subsystem_flags &= ~flag; 230} 231 232static inline bool eeh_has_flag(int flag) 233{ 234 return !!(eeh_subsystem_flags & flag); 235} 236 237static inline bool eeh_enabled(void) 238{ 239 if (eeh_has_flag(EEH_FORCE_DISABLED) || 240 !eeh_has_flag(EEH_ENABLED)) 241 return false; 242 243 return true; 244} 245 246static inline void eeh_serialize_lock(unsigned long *flags) 247{ 248 raw_spin_lock_irqsave(&confirm_error_lock, *flags); 249} 250 251static inline void eeh_serialize_unlock(unsigned long flags) 252{ 253 raw_spin_unlock_irqrestore(&confirm_error_lock, flags); 254} 255 256typedef void *(*eeh_traverse_func)(void *data, void *flag); 257void eeh_set_pe_aux_size(int size); 258int eeh_phb_pe_create(struct pci_controller *phb); 259struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb); 260struct eeh_pe *eeh_pe_get(struct eeh_dev *edev); 261int eeh_add_to_parent_pe(struct eeh_dev *edev); 262int eeh_rmv_from_parent_pe(struct eeh_dev *edev); 263void eeh_pe_update_time_stamp(struct eeh_pe *pe); 264void *eeh_pe_traverse(struct eeh_pe *root, 265 eeh_traverse_func fn, void *flag); 266void *eeh_pe_dev_traverse(struct eeh_pe *root, 267 eeh_traverse_func fn, void *flag); 268void eeh_pe_restore_bars(struct eeh_pe *pe); 269const char *eeh_pe_loc_get(struct eeh_pe *pe); 270struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe); 271 272void *eeh_dev_init(struct pci_dn *pdn, void *data); 273void eeh_dev_phb_init_dynamic(struct pci_controller *phb); 274int eeh_init(void); 275int __init eeh_ops_register(struct eeh_ops *ops); 276int __exit eeh_ops_unregister(const char *name); 277int eeh_check_failure(const volatile void __iomem *token); 278int eeh_dev_check_failure(struct eeh_dev *edev); 279void eeh_addr_cache_build(void); 280void eeh_add_device_early(struct pci_dn *); 281void eeh_add_device_tree_early(struct pci_dn *); 282void eeh_add_device_late(struct pci_dev *); 283void eeh_add_device_tree_late(struct pci_bus *); 284void eeh_add_sysfs_files(struct pci_bus *); 285void eeh_remove_device(struct pci_dev *); 286int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state); 287int eeh_pe_reset_and_recover(struct eeh_pe *pe); 288int eeh_dev_open(struct pci_dev *pdev); 289void eeh_dev_release(struct pci_dev *pdev); 290struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group); 291int eeh_pe_set_option(struct eeh_pe *pe, int option); 292int eeh_pe_get_state(struct eeh_pe *pe); 293int eeh_pe_reset(struct eeh_pe *pe, int option); 294int eeh_pe_configure(struct eeh_pe *pe); 295int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func, 296 unsigned long addr, unsigned long mask); 297 298/** 299 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure. 300 * 301 * If this macro yields TRUE, the caller relays to eeh_check_failure() 302 * which does further tests out of line. 303 */ 304#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled()) 305 306/* 307 * Reads from a device which has been isolated by EEH will return 308 * all 1s. This macro gives an all-1s value of the given size (in 309 * bytes: 1, 2, or 4) for comparing with the result of a read. 310 */ 311#define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8)) 312 313#else /* !CONFIG_EEH */ 314 315static inline bool eeh_enabled(void) 316{ 317 return false; 318} 319 320static inline int eeh_init(void) 321{ 322 return 0; 323} 324 325static inline void *eeh_dev_init(struct pci_dn *pdn, void *data) 326{ 327 return NULL; 328} 329 330static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { } 331 332static inline int eeh_check_failure(const volatile void __iomem *token) 333{ 334 return 0; 335} 336 337#define eeh_dev_check_failure(x) (0) 338 339static inline void eeh_addr_cache_build(void) { } 340 341static inline void eeh_add_device_early(struct pci_dn *pdn) { } 342 343static inline void eeh_add_device_tree_early(struct pci_dn *pdn) { } 344 345static inline void eeh_add_device_late(struct pci_dev *dev) { } 346 347static inline void eeh_add_device_tree_late(struct pci_bus *bus) { } 348 349static inline void eeh_add_sysfs_files(struct pci_bus *bus) { } 350 351static inline void eeh_remove_device(struct pci_dev *dev) { } 352 353#define EEH_POSSIBLE_ERROR(val, type) (0) 354#define EEH_IO_ERROR_VALUE(size) (-1UL) 355#endif /* CONFIG_EEH */ 356 357#ifdef CONFIG_PPC64 358/* 359 * MMIO read/write operations with EEH support. 360 */ 361static inline u8 eeh_readb(const volatile void __iomem *addr) 362{ 363 u8 val = in_8(addr); 364 if (EEH_POSSIBLE_ERROR(val, u8)) 365 eeh_check_failure(addr); 366 return val; 367} 368 369static inline u16 eeh_readw(const volatile void __iomem *addr) 370{ 371 u16 val = in_le16(addr); 372 if (EEH_POSSIBLE_ERROR(val, u16)) 373 eeh_check_failure(addr); 374 return val; 375} 376 377static inline u32 eeh_readl(const volatile void __iomem *addr) 378{ 379 u32 val = in_le32(addr); 380 if (EEH_POSSIBLE_ERROR(val, u32)) 381 eeh_check_failure(addr); 382 return val; 383} 384 385static inline u64 eeh_readq(const volatile void __iomem *addr) 386{ 387 u64 val = in_le64(addr); 388 if (EEH_POSSIBLE_ERROR(val, u64)) 389 eeh_check_failure(addr); 390 return val; 391} 392 393static inline u16 eeh_readw_be(const volatile void __iomem *addr) 394{ 395 u16 val = in_be16(addr); 396 if (EEH_POSSIBLE_ERROR(val, u16)) 397 eeh_check_failure(addr); 398 return val; 399} 400 401static inline u32 eeh_readl_be(const volatile void __iomem *addr) 402{ 403 u32 val = in_be32(addr); 404 if (EEH_POSSIBLE_ERROR(val, u32)) 405 eeh_check_failure(addr); 406 return val; 407} 408 409static inline u64 eeh_readq_be(const volatile void __iomem *addr) 410{ 411 u64 val = in_be64(addr); 412 if (EEH_POSSIBLE_ERROR(val, u64)) 413 eeh_check_failure(addr); 414 return val; 415} 416 417static inline void eeh_memcpy_fromio(void *dest, const 418 volatile void __iomem *src, 419 unsigned long n) 420{ 421 _memcpy_fromio(dest, src, n); 422 423 /* Look for ffff's here at dest[n]. Assume that at least 4 bytes 424 * were copied. Check all four bytes. 425 */ 426 if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32)) 427 eeh_check_failure(src); 428} 429 430/* in-string eeh macros */ 431static inline void eeh_readsb(const volatile void __iomem *addr, void * buf, 432 int ns) 433{ 434 _insb(addr, buf, ns); 435 if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8)) 436 eeh_check_failure(addr); 437} 438 439static inline void eeh_readsw(const volatile void __iomem *addr, void * buf, 440 int ns) 441{ 442 _insw(addr, buf, ns); 443 if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16)) 444 eeh_check_failure(addr); 445} 446 447static inline void eeh_readsl(const volatile void __iomem *addr, void * buf, 448 int nl) 449{ 450 _insl(addr, buf, nl); 451 if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32)) 452 eeh_check_failure(addr); 453} 454 455#endif /* CONFIG_PPC64 */ 456#endif /* __KERNEL__ */ 457#endif /* _POWERPC_EEH_H */ 458