1/* 2 * SBC8641D Device Tree Source 3 * 4 * Copyright 2008 Wind River Systems Inc. 5 * 6 * Paul Gortmaker (see MAINTAINERS for contact information) 7 * 8 * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16/dts-v1/; 17 18/ { 19 model = "SBC8641D"; 20 compatible = "wind,sbc8641"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 24 aliases { 25 ethernet0 = &enet0; 26 ethernet1 = &enet1; 27 ethernet2 = &enet2; 28 ethernet3 = &enet3; 29 serial0 = &serial0; 30 serial1 = &serial1; 31 pci0 = &pci0; 32 pci1 = &pci1; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 PowerPC,8641@0 { 40 device_type = "cpu"; 41 reg = <0>; 42 d-cache-line-size = <32>; 43 i-cache-line-size = <32>; 44 d-cache-size = <32768>; // L1 45 i-cache-size = <32768>; // L1 46 timebase-frequency = <0>; // From uboot 47 bus-frequency = <0>; // From uboot 48 clock-frequency = <0>; // From uboot 49 }; 50 PowerPC,8641@1 { 51 device_type = "cpu"; 52 reg = <1>; 53 d-cache-line-size = <32>; 54 i-cache-line-size = <32>; 55 d-cache-size = <32768>; 56 i-cache-size = <32768>; 57 timebase-frequency = <0>; // From uboot 58 bus-frequency = <0>; // From uboot 59 clock-frequency = <0>; // From uboot 60 }; 61 }; 62 63 memory { 64 device_type = "memory"; 65 reg = <0x00000000 0x20000000>; // 512M at 0x0 66 }; 67 68 localbus@f8005000 { 69 #address-cells = <2>; 70 #size-cells = <1>; 71 compatible = "fsl,mpc8641-localbus", "simple-bus"; 72 reg = <0xf8005000 0x1000>; 73 interrupts = <19 2>; 74 interrupt-parent = <&mpic>; 75 76 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash 77 1 0 0xf0000000 0x00010000 // 64KB EEPROM 78 2 0 0xf1000000 0x00100000 // EPLD (1MB) 79 3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3) 80 4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4) 81 6 0 0xf4000000 0x00100000 // LCD display (1MB) 82 7 0 0xe8000000 0x04000000>; // 64MB OneNAND 83 84 flash@0,0 { 85 compatible = "cfi-flash"; 86 reg = <0 0 0x01000000>; 87 bank-width = <2>; 88 device-width = <2>; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 partition@0 { 92 label = "dtb"; 93 reg = <0x00000000 0x00100000>; 94 read-only; 95 }; 96 partition@300000 { 97 label = "kernel"; 98 reg = <0x00100000 0x00400000>; 99 read-only; 100 }; 101 partition@400000 { 102 label = "fs"; 103 reg = <0x00500000 0x00a00000>; 104 }; 105 partition@700000 { 106 label = "firmware"; 107 reg = <0x00f00000 0x00100000>; 108 read-only; 109 }; 110 }; 111 112 epld@2,0 { 113 compatible = "wrs,epld-localbus"; 114 #address-cells = <2>; 115 #size-cells = <1>; 116 reg = <2 0 0x100000>; 117 ranges = <0 0 5 0 1 // User switches 118 1 0 5 1 1 // Board ID/Rev 119 3 0 5 3 1>; // LEDs 120 }; 121 }; 122 123 soc@f8000000 { 124 #address-cells = <1>; 125 #size-cells = <1>; 126 device_type = "soc"; 127 compatible = "simple-bus"; 128 ranges = <0x00000000 0xf8000000 0x00100000>; 129 bus-frequency = <0>; 130 131 mcm-law@0 { 132 compatible = "fsl,mcm-law"; 133 reg = <0x0 0x1000>; 134 fsl,num-laws = <10>; 135 }; 136 137 mcm@1000 { 138 compatible = "fsl,mpc8641-mcm", "fsl,mcm"; 139 reg = <0x1000 0x1000>; 140 interrupts = <17 2>; 141 interrupt-parent = <&mpic>; 142 }; 143 144 i2c@3000 { 145 #address-cells = <1>; 146 #size-cells = <0>; 147 cell-index = <0>; 148 compatible = "fsl-i2c"; 149 reg = <0x3000 0x100>; 150 interrupts = <43 2>; 151 interrupt-parent = <&mpic>; 152 dfsrr; 153 }; 154 155 i2c@3100 { 156 #address-cells = <1>; 157 #size-cells = <0>; 158 cell-index = <1>; 159 compatible = "fsl-i2c"; 160 reg = <0x3100 0x100>; 161 interrupts = <43 2>; 162 interrupt-parent = <&mpic>; 163 dfsrr; 164 }; 165 166 dma@21300 { 167 #address-cells = <1>; 168 #size-cells = <1>; 169 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma"; 170 reg = <0x21300 0x4>; 171 ranges = <0x0 0x21100 0x200>; 172 cell-index = <0>; 173 dma-channel@0 { 174 compatible = "fsl,mpc8641-dma-channel", 175 "fsl,eloplus-dma-channel"; 176 reg = <0x0 0x80>; 177 cell-index = <0>; 178 interrupt-parent = <&mpic>; 179 interrupts = <20 2>; 180 }; 181 dma-channel@80 { 182 compatible = "fsl,mpc8641-dma-channel", 183 "fsl,eloplus-dma-channel"; 184 reg = <0x80 0x80>; 185 cell-index = <1>; 186 interrupt-parent = <&mpic>; 187 interrupts = <21 2>; 188 }; 189 dma-channel@100 { 190 compatible = "fsl,mpc8641-dma-channel", 191 "fsl,eloplus-dma-channel"; 192 reg = <0x100 0x80>; 193 cell-index = <2>; 194 interrupt-parent = <&mpic>; 195 interrupts = <22 2>; 196 }; 197 dma-channel@180 { 198 compatible = "fsl,mpc8641-dma-channel", 199 "fsl,eloplus-dma-channel"; 200 reg = <0x180 0x80>; 201 cell-index = <3>; 202 interrupt-parent = <&mpic>; 203 interrupts = <23 2>; 204 }; 205 }; 206 207 enet0: ethernet@24000 { 208 #address-cells = <1>; 209 #size-cells = <1>; 210 cell-index = <0>; 211 device_type = "network"; 212 model = "TSEC"; 213 compatible = "gianfar"; 214 reg = <0x24000 0x1000>; 215 ranges = <0x0 0x24000 0x1000>; 216 local-mac-address = [ 00 00 00 00 00 00 ]; 217 interrupts = <29 2 30 2 34 2>; 218 interrupt-parent = <&mpic>; 219 tbi-handle = <&tbi0>; 220 phy-handle = <&phy0>; 221 phy-connection-type = "rgmii-id"; 222 223 mdio@520 { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 compatible = "fsl,gianfar-mdio"; 227 reg = <0x520 0x20>; 228 229 phy0: ethernet-phy@1f { 230 reg = <0x1f>; 231 }; 232 phy1: ethernet-phy@0 { 233 reg = <0>; 234 }; 235 phy2: ethernet-phy@1 { 236 reg = <1>; 237 }; 238 phy3: ethernet-phy@2 { 239 reg = <2>; 240 }; 241 tbi0: tbi-phy@11 { 242 reg = <0x11>; 243 device_type = "tbi-phy"; 244 }; 245 }; 246 }; 247 248 enet1: ethernet@25000 { 249 #address-cells = <1>; 250 #size-cells = <1>; 251 cell-index = <1>; 252 device_type = "network"; 253 model = "TSEC"; 254 compatible = "gianfar"; 255 reg = <0x25000 0x1000>; 256 ranges = <0x0 0x25000 0x1000>; 257 local-mac-address = [ 00 00 00 00 00 00 ]; 258 interrupts = <35 2 36 2 40 2>; 259 interrupt-parent = <&mpic>; 260 tbi-handle = <&tbi1>; 261 phy-handle = <&phy1>; 262 phy-connection-type = "rgmii-id"; 263 264 mdio@520 { 265 #address-cells = <1>; 266 #size-cells = <0>; 267 compatible = "fsl,gianfar-tbi"; 268 reg = <0x520 0x20>; 269 270 tbi1: tbi-phy@11 { 271 reg = <0x11>; 272 device_type = "tbi-phy"; 273 }; 274 }; 275 }; 276 277 enet2: ethernet@26000 { 278 #address-cells = <1>; 279 #size-cells = <1>; 280 cell-index = <2>; 281 device_type = "network"; 282 model = "TSEC"; 283 compatible = "gianfar"; 284 reg = <0x26000 0x1000>; 285 ranges = <0x0 0x26000 0x1000>; 286 local-mac-address = [ 00 00 00 00 00 00 ]; 287 interrupts = <31 2 32 2 33 2>; 288 interrupt-parent = <&mpic>; 289 tbi-handle = <&tbi2>; 290 phy-handle = <&phy2>; 291 phy-connection-type = "rgmii-id"; 292 293 mdio@520 { 294 #address-cells = <1>; 295 #size-cells = <0>; 296 compatible = "fsl,gianfar-tbi"; 297 reg = <0x520 0x20>; 298 299 tbi2: tbi-phy@11 { 300 reg = <0x11>; 301 device_type = "tbi-phy"; 302 }; 303 }; 304 }; 305 306 enet3: ethernet@27000 { 307 #address-cells = <1>; 308 #size-cells = <1>; 309 cell-index = <3>; 310 device_type = "network"; 311 model = "TSEC"; 312 compatible = "gianfar"; 313 reg = <0x27000 0x1000>; 314 ranges = <0x0 0x27000 0x1000>; 315 local-mac-address = [ 00 00 00 00 00 00 ]; 316 interrupts = <37 2 38 2 39 2>; 317 interrupt-parent = <&mpic>; 318 tbi-handle = <&tbi3>; 319 phy-handle = <&phy3>; 320 phy-connection-type = "rgmii-id"; 321 322 mdio@520 { 323 #address-cells = <1>; 324 #size-cells = <0>; 325 compatible = "fsl,gianfar-tbi"; 326 reg = <0x520 0x20>; 327 328 tbi3: tbi-phy@11 { 329 reg = <0x11>; 330 device_type = "tbi-phy"; 331 }; 332 }; 333 }; 334 335 serial0: serial@4500 { 336 cell-index = <0>; 337 device_type = "serial"; 338 compatible = "fsl,ns16550", "ns16550"; 339 reg = <0x4500 0x100>; 340 clock-frequency = <0>; 341 interrupts = <42 2>; 342 interrupt-parent = <&mpic>; 343 }; 344 345 serial1: serial@4600 { 346 cell-index = <1>; 347 device_type = "serial"; 348 compatible = "fsl,ns16550", "ns16550"; 349 reg = <0x4600 0x100>; 350 clock-frequency = <0>; 351 interrupts = <28 2>; 352 interrupt-parent = <&mpic>; 353 }; 354 355 mpic: pic@40000 { 356 clock-frequency = <0>; 357 interrupt-controller; 358 #address-cells = <0>; 359 #interrupt-cells = <2>; 360 reg = <0x40000 0x40000>; 361 compatible = "chrp,open-pic"; 362 device_type = "open-pic"; 363 big-endian; 364 }; 365 366 global-utilities@e0000 { 367 compatible = "fsl,mpc8641-guts"; 368 reg = <0xe0000 0x1000>; 369 fsl,has-rstcr; 370 }; 371 }; 372 373 pci0: pcie@f8008000 { 374 compatible = "fsl,mpc8641-pcie"; 375 device_type = "pci"; 376 #interrupt-cells = <1>; 377 #size-cells = <2>; 378 #address-cells = <3>; 379 reg = <0xf8008000 0x1000>; 380 bus-range = <0x0 0xff>; 381 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000 382 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 383 clock-frequency = <33333333>; 384 interrupt-parent = <&mpic>; 385 interrupts = <24 2>; 386 interrupt-map-mask = <0xff00 0 0 7>; 387 interrupt-map = < 388 /* IDSEL 0x0 */ 389 0x0000 0 0 1 &mpic 0 1 390 0x0000 0 0 2 &mpic 1 1 391 0x0000 0 0 3 &mpic 2 1 392 0x0000 0 0 4 &mpic 3 1 393 >; 394 395 pcie@0 { 396 reg = <0 0 0 0 0>; 397 #size-cells = <2>; 398 #address-cells = <3>; 399 device_type = "pci"; 400 ranges = <0x02000000 0x0 0x80000000 401 0x02000000 0x0 0x80000000 402 0x0 0x20000000 403 404 0x01000000 0x0 0x00000000 405 0x01000000 0x0 0x00000000 406 0x0 0x00100000>; 407 }; 408 409 }; 410 411 pci1: pcie@f8009000 { 412 compatible = "fsl,mpc8641-pcie"; 413 device_type = "pci"; 414 #interrupt-cells = <1>; 415 #size-cells = <2>; 416 #address-cells = <3>; 417 reg = <0xf8009000 0x1000>; 418 bus-range = <0 0xff>; 419 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 420 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>; 421 clock-frequency = <33333333>; 422 interrupt-parent = <&mpic>; 423 interrupts = <25 2>; 424 interrupt-map-mask = <0xf800 0 0 7>; 425 interrupt-map = < 426 /* IDSEL 0x0 */ 427 0x0000 0 0 1 &mpic 4 1 428 0x0000 0 0 2 &mpic 5 1 429 0x0000 0 0 3 &mpic 6 1 430 0x0000 0 0 4 &mpic 7 1 431 >; 432 433 pcie@0 { 434 reg = <0 0 0 0 0>; 435 #size-cells = <2>; 436 #address-cells = <3>; 437 device_type = "pci"; 438 ranges = <0x02000000 0x0 0xa0000000 439 0x02000000 0x0 0xa0000000 440 0x0 0x20000000 441 442 0x01000000 0x0 0x00000000 443 0x01000000 0x0 0x00000000 444 0x0 0x00100000>; 445 }; 446 }; 447}; 448