1/* 2 * MPC8540 ADS Device Tree Source 3 * 4 * Copyright 2006, 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/include/ "e500v2_power_isa.dtsi" 15 16/ { 17 model = "MPC8540ADS"; 18 compatible = "MPC8540ADS", "MPC85xxADS"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 aliases { 23 ethernet0 = &enet0; 24 ethernet1 = &enet1; 25 ethernet2 = &enet2; 26 serial0 = &serial0; 27 serial1 = &serial1; 28 pci0 = &pci0; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 PowerPC,8540@0 { 36 device_type = "cpu"; 37 reg = <0x0>; 38 d-cache-line-size = <32>; // 32 bytes 39 i-cache-line-size = <32>; // 32 bytes 40 d-cache-size = <0x8000>; // L1, 32K 41 i-cache-size = <0x8000>; // L1, 32K 42 timebase-frequency = <0>; // 33 MHz, from uboot 43 bus-frequency = <0>; // 166 MHz 44 clock-frequency = <0>; // 825 MHz, from uboot 45 next-level-cache = <&L2>; 46 }; 47 }; 48 49 memory { 50 device_type = "memory"; 51 reg = <0x0 0x8000000>; // 128M at 0x0 52 }; 53 54 soc8540@e0000000 { 55 #address-cells = <1>; 56 #size-cells = <1>; 57 device_type = "soc"; 58 compatible = "simple-bus"; 59 ranges = <0x0 0xe0000000 0x100000>; 60 bus-frequency = <0>; 61 62 ecm-law@0 { 63 compatible = "fsl,ecm-law"; 64 reg = <0x0 0x1000>; 65 fsl,num-laws = <8>; 66 }; 67 68 ecm@1000 { 69 compatible = "fsl,mpc8540-ecm", "fsl,ecm"; 70 reg = <0x1000 0x1000>; 71 interrupts = <17 2>; 72 interrupt-parent = <&mpic>; 73 }; 74 75 memory-controller@2000 { 76 compatible = "fsl,mpc8540-memory-controller"; 77 reg = <0x2000 0x1000>; 78 interrupt-parent = <&mpic>; 79 interrupts = <18 2>; 80 }; 81 82 L2: l2-cache-controller@20000 { 83 compatible = "fsl,mpc8540-l2-cache-controller"; 84 reg = <0x20000 0x1000>; 85 cache-line-size = <32>; // 32 bytes 86 cache-size = <0x40000>; // L2, 256K 87 interrupt-parent = <&mpic>; 88 interrupts = <16 2>; 89 }; 90 91 i2c@3000 { 92 #address-cells = <1>; 93 #size-cells = <0>; 94 cell-index = <0>; 95 compatible = "fsl-i2c"; 96 reg = <0x3000 0x100>; 97 interrupts = <43 2>; 98 interrupt-parent = <&mpic>; 99 dfsrr; 100 }; 101 102 dma@21300 { 103 #address-cells = <1>; 104 #size-cells = <1>; 105 compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; 106 reg = <0x21300 0x4>; 107 ranges = <0x0 0x21100 0x200>; 108 cell-index = <0>; 109 dma-channel@0 { 110 compatible = "fsl,mpc8540-dma-channel", 111 "fsl,eloplus-dma-channel"; 112 reg = <0x0 0x80>; 113 cell-index = <0>; 114 interrupt-parent = <&mpic>; 115 interrupts = <20 2>; 116 }; 117 dma-channel@80 { 118 compatible = "fsl,mpc8540-dma-channel", 119 "fsl,eloplus-dma-channel"; 120 reg = <0x80 0x80>; 121 cell-index = <1>; 122 interrupt-parent = <&mpic>; 123 interrupts = <21 2>; 124 }; 125 dma-channel@100 { 126 compatible = "fsl,mpc8540-dma-channel", 127 "fsl,eloplus-dma-channel"; 128 reg = <0x100 0x80>; 129 cell-index = <2>; 130 interrupt-parent = <&mpic>; 131 interrupts = <22 2>; 132 }; 133 dma-channel@180 { 134 compatible = "fsl,mpc8540-dma-channel", 135 "fsl,eloplus-dma-channel"; 136 reg = <0x180 0x80>; 137 cell-index = <3>; 138 interrupt-parent = <&mpic>; 139 interrupts = <23 2>; 140 }; 141 }; 142 143 enet0: ethernet@24000 { 144 #address-cells = <1>; 145 #size-cells = <1>; 146 cell-index = <0>; 147 device_type = "network"; 148 model = "TSEC"; 149 compatible = "gianfar"; 150 reg = <0x24000 0x1000>; 151 ranges = <0x0 0x24000 0x1000>; 152 local-mac-address = [ 00 00 00 00 00 00 ]; 153 interrupts = <29 2 30 2 34 2>; 154 interrupt-parent = <&mpic>; 155 tbi-handle = <&tbi0>; 156 phy-handle = <&phy0>; 157 158 mdio@520 { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 compatible = "fsl,gianfar-mdio"; 162 reg = <0x520 0x20>; 163 164 phy0: ethernet-phy@0 { 165 interrupt-parent = <&mpic>; 166 interrupts = <5 1>; 167 reg = <0x0>; 168 }; 169 phy1: ethernet-phy@1 { 170 interrupt-parent = <&mpic>; 171 interrupts = <5 1>; 172 reg = <0x1>; 173 }; 174 phy3: ethernet-phy@3 { 175 interrupt-parent = <&mpic>; 176 interrupts = <7 1>; 177 reg = <0x3>; 178 }; 179 tbi0: tbi-phy@11 { 180 reg = <0x11>; 181 device_type = "tbi-phy"; 182 }; 183 }; 184 }; 185 186 enet1: ethernet@25000 { 187 #address-cells = <1>; 188 #size-cells = <1>; 189 cell-index = <1>; 190 device_type = "network"; 191 model = "TSEC"; 192 compatible = "gianfar"; 193 reg = <0x25000 0x1000>; 194 ranges = <0x0 0x25000 0x1000>; 195 local-mac-address = [ 00 00 00 00 00 00 ]; 196 interrupts = <35 2 36 2 40 2>; 197 interrupt-parent = <&mpic>; 198 tbi-handle = <&tbi1>; 199 phy-handle = <&phy1>; 200 201 mdio@520 { 202 #address-cells = <1>; 203 #size-cells = <0>; 204 compatible = "fsl,gianfar-tbi"; 205 reg = <0x520 0x20>; 206 207 tbi1: tbi-phy@11 { 208 reg = <0x11>; 209 device_type = "tbi-phy"; 210 }; 211 }; 212 }; 213 214 enet2: ethernet@26000 { 215 #address-cells = <1>; 216 #size-cells = <1>; 217 cell-index = <2>; 218 device_type = "network"; 219 model = "FEC"; 220 compatible = "gianfar"; 221 reg = <0x26000 0x1000>; 222 ranges = <0x0 0x26000 0x1000>; 223 local-mac-address = [ 00 00 00 00 00 00 ]; 224 interrupts = <41 2>; 225 interrupt-parent = <&mpic>; 226 tbi-handle = <&tbi2>; 227 phy-handle = <&phy3>; 228 229 mdio@520 { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 compatible = "fsl,gianfar-tbi"; 233 reg = <0x520 0x20>; 234 235 tbi2: tbi-phy@11 { 236 reg = <0x11>; 237 device_type = "tbi-phy"; 238 }; 239 }; 240 }; 241 242 serial0: serial@4500 { 243 cell-index = <0>; 244 device_type = "serial"; 245 compatible = "fsl,ns16550", "ns16550"; 246 reg = <0x4500 0x100>; // reg base, size 247 clock-frequency = <0>; // should we fill in in uboot? 248 interrupts = <42 2>; 249 interrupt-parent = <&mpic>; 250 }; 251 252 serial1: serial@4600 { 253 cell-index = <1>; 254 device_type = "serial"; 255 compatible = "fsl,ns16550", "ns16550"; 256 reg = <0x4600 0x100>; // reg base, size 257 clock-frequency = <0>; // should we fill in in uboot? 258 interrupts = <42 2>; 259 interrupt-parent = <&mpic>; 260 }; 261 mpic: pic@40000 { 262 interrupt-controller; 263 #address-cells = <0>; 264 #interrupt-cells = <2>; 265 reg = <0x40000 0x40000>; 266 compatible = "chrp,open-pic"; 267 device_type = "open-pic"; 268 }; 269 }; 270 271 pci0: pci@e0008000 { 272 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 273 interrupt-map = < 274 275 /* IDSEL 0x02 */ 276 0x1000 0x0 0x0 0x1 &mpic 0x1 0x1 277 0x1000 0x0 0x0 0x2 &mpic 0x2 0x1 278 0x1000 0x0 0x0 0x3 &mpic 0x3 0x1 279 0x1000 0x0 0x0 0x4 &mpic 0x4 0x1 280 281 /* IDSEL 0x03 */ 282 0x1800 0x0 0x0 0x1 &mpic 0x4 0x1 283 0x1800 0x0 0x0 0x2 &mpic 0x1 0x1 284 0x1800 0x0 0x0 0x3 &mpic 0x2 0x1 285 0x1800 0x0 0x0 0x4 &mpic 0x3 0x1 286 287 /* IDSEL 0x04 */ 288 0x2000 0x0 0x0 0x1 &mpic 0x3 0x1 289 0x2000 0x0 0x0 0x2 &mpic 0x4 0x1 290 0x2000 0x0 0x0 0x3 &mpic 0x1 0x1 291 0x2000 0x0 0x0 0x4 &mpic 0x2 0x1 292 293 /* IDSEL 0x05 */ 294 0x2800 0x0 0x0 0x1 &mpic 0x2 0x1 295 0x2800 0x0 0x0 0x2 &mpic 0x3 0x1 296 0x2800 0x0 0x0 0x3 &mpic 0x4 0x1 297 0x2800 0x0 0x0 0x4 &mpic 0x1 0x1 298 299 /* IDSEL 0x0c */ 300 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1 301 0x6000 0x0 0x0 0x2 &mpic 0x2 0x1 302 0x6000 0x0 0x0 0x3 &mpic 0x3 0x1 303 0x6000 0x0 0x0 0x4 &mpic 0x4 0x1 304 305 /* IDSEL 0x0d */ 306 0x6800 0x0 0x0 0x1 &mpic 0x4 0x1 307 0x6800 0x0 0x0 0x2 &mpic 0x1 0x1 308 0x6800 0x0 0x0 0x3 &mpic 0x2 0x1 309 0x6800 0x0 0x0 0x4 &mpic 0x3 0x1 310 311 /* IDSEL 0x0e */ 312 0x7000 0x0 0x0 0x1 &mpic 0x3 0x1 313 0x7000 0x0 0x0 0x2 &mpic 0x4 0x1 314 0x7000 0x0 0x0 0x3 &mpic 0x1 0x1 315 0x7000 0x0 0x0 0x4 &mpic 0x2 0x1 316 317 /* IDSEL 0x0f */ 318 0x7800 0x0 0x0 0x1 &mpic 0x2 0x1 319 0x7800 0x0 0x0 0x2 &mpic 0x3 0x1 320 0x7800 0x0 0x0 0x3 &mpic 0x4 0x1 321 0x7800 0x0 0x0 0x4 &mpic 0x1 0x1 322 323 /* IDSEL 0x12 */ 324 0x9000 0x0 0x0 0x1 &mpic 0x1 0x1 325 0x9000 0x0 0x0 0x2 &mpic 0x2 0x1 326 0x9000 0x0 0x0 0x3 &mpic 0x3 0x1 327 0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 328 329 /* IDSEL 0x13 */ 330 0x9800 0x0 0x0 0x1 &mpic 0x4 0x1 331 0x9800 0x0 0x0 0x2 &mpic 0x1 0x1 332 0x9800 0x0 0x0 0x3 &mpic 0x2 0x1 333 0x9800 0x0 0x0 0x4 &mpic 0x3 0x1 334 335 /* IDSEL 0x14 */ 336 0xa000 0x0 0x0 0x1 &mpic 0x3 0x1 337 0xa000 0x0 0x0 0x2 &mpic 0x4 0x1 338 0xa000 0x0 0x0 0x3 &mpic 0x1 0x1 339 0xa000 0x0 0x0 0x4 &mpic 0x2 0x1 340 341 /* IDSEL 0x15 */ 342 0xa800 0x0 0x0 0x1 &mpic 0x2 0x1 343 0xa800 0x0 0x0 0x2 &mpic 0x3 0x1 344 0xa800 0x0 0x0 0x3 &mpic 0x4 0x1 345 0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>; 346 interrupt-parent = <&mpic>; 347 interrupts = <24 2>; 348 bus-range = <0 0>; 349 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 350 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; 351 clock-frequency = <66666666>; 352 #interrupt-cells = <1>; 353 #size-cells = <2>; 354 #address-cells = <3>; 355 reg = <0xe0008000 0x1000>; 356 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 357 device_type = "pci"; 358 }; 359}; 360