1/* 2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> 3 * 4 * Loongson 1 Clock Register Definitions. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12#ifndef __ASM_MACH_LOONGSON32_REGS_CLK_H 13#define __ASM_MACH_LOONGSON32_REGS_CLK_H 14 15#define LS1X_CLK_REG(x) \ 16 ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x))) 17 18#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0) 19#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4) 20 21/* Clock PLL Divisor Register Bits */ 22#define DIV_DC_EN (0x1 << 31) 23#define DIV_DC_RST (0x1 << 30) 24#define DIV_CPU_EN (0x1 << 25) 25#define DIV_CPU_RST (0x1 << 24) 26#define DIV_DDR_EN (0x1 << 19) 27#define DIV_DDR_RST (0x1 << 18) 28#define RST_DC_EN (0x1 << 5) 29#define RST_DC (0x1 << 4) 30#define RST_DDR_EN (0x1 << 3) 31#define RST_DDR (0x1 << 2) 32#define RST_CPU_EN (0x1 << 1) 33#define RST_CPU 0x1 34 35#define DIV_DC_SHIFT 26 36#define DIV_CPU_SHIFT 20 37#define DIV_DDR_SHIFT 14 38 39#define DIV_DC_WIDTH 4 40#define DIV_CPU_WIDTH 4 41#define DIV_DDR_WIDTH 4 42 43#define BYPASS_DC_SHIFT 12 44#define BYPASS_DDR_SHIFT 10 45#define BYPASS_CPU_SHIFT 8 46 47#define BYPASS_DC_WIDTH 1 48#define BYPASS_DDR_WIDTH 1 49#define BYPASS_CPU_WIDTH 1 50 51#endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */ 52