1#ifndef _LINUX_FDREG_H
2#define _LINUX_FDREG_H
3
4/*
5** WD1772 stuff
6 */
7
8/* register codes */
9
10#define FDCSELREG_STP   (0x80)   /* command/status register */
11#define FDCSELREG_TRA   (0x82)   /* track register */
12#define FDCSELREG_SEC   (0x84)   /* sector register */
13#define FDCSELREG_DTA   (0x86)   /* data register */
14
15/* register names for FDC_READ/WRITE macros */
16
17#define FDCREG_CMD		0
18#define FDCREG_STATUS	0
19#define FDCREG_TRACK	2
20#define FDCREG_SECTOR	4
21#define FDCREG_DATA		6
22
23/* command opcodes */
24
25#define FDCCMD_RESTORE  (0x00)   /*  -                   */
26#define FDCCMD_SEEK     (0x10)   /*   |                  */
27#define FDCCMD_STEP     (0x20)   /*   |  TYP 1 Commands  */
28#define FDCCMD_STIN     (0x40)   /*   |                  */
29#define FDCCMD_STOT     (0x60)   /*  -                   */
30#define FDCCMD_RDSEC    (0x80)   /*  -   TYP 2 Commands  */
31#define FDCCMD_WRSEC    (0xa0)   /*  -          "        */
32#define FDCCMD_RDADR    (0xc0)   /*  -                   */
33#define FDCCMD_RDTRA    (0xe0)   /*   |  TYP 3 Commands  */
34#define FDCCMD_WRTRA    (0xf0)   /*  -                   */
35#define FDCCMD_FORCI    (0xd0)   /*  -   TYP 4 Command   */
36
37/* command modifier bits */
38
39#define FDCCMDADD_SR6   (0x00)   /* step rate settings */
40#define FDCCMDADD_SR12  (0x01)
41#define FDCCMDADD_SR2   (0x02)
42#define FDCCMDADD_SR3   (0x03)
43#define FDCCMDADD_V     (0x04)   /* verify */
44#define FDCCMDADD_H     (0x08)   /* wait for spin-up */
45#define FDCCMDADD_U     (0x10)   /* update track register */
46#define FDCCMDADD_M     (0x10)   /* multiple sector access */
47#define FDCCMDADD_E     (0x04)   /* head settling flag */
48#define FDCCMDADD_P     (0x02)   /* precompensation off */
49#define FDCCMDADD_A0    (0x01)   /* DAM flag */
50
51/* status register bits */
52
53#define	FDCSTAT_MOTORON	(0x80)   /* motor on */
54#define	FDCSTAT_WPROT	(0x40)   /* write protected (FDCCMD_WR*) */
55#define	FDCSTAT_SPINUP	(0x20)   /* motor speed stable (Type I) */
56#define	FDCSTAT_DELDAM	(0x20)   /* sector has deleted DAM (Type II+III) */
57#define	FDCSTAT_RECNF	(0x10)   /* record not found */
58#define	FDCSTAT_CRC		(0x08)   /* CRC error */
59#define	FDCSTAT_TR00	(0x04)   /* Track 00 flag (Type I) */
60#define	FDCSTAT_LOST	(0x04)   /* Lost Data (Type II+III) */
61#define	FDCSTAT_IDX		(0x02)   /* Index status (Type I) */
62#define	FDCSTAT_DRQ		(0x02)   /* DRQ status (Type II+III) */
63#define	FDCSTAT_BUSY	(0x01)   /* FDC is busy */
64
65
66/* PSG Port A Bit Nr 0 .. Side Sel .. 0 -> Side 1  1 -> Side 2 */
67#define DSKSIDE     (0x01)
68
69#define DSKDRVNONE  (0x06)
70#define DSKDRV0     (0x02)
71#define DSKDRV1     (0x04)
72
73/* step rates */
74#define	FDCSTEP_6	0x00
75#define	FDCSTEP_12	0x01
76#define	FDCSTEP_2	0x02
77#define	FDCSTEP_3	0x03
78
79#endif
80