1/dts-v1/; 2/ { 3 compatible = "gnu,gdbsim"; 4 #address-cells = <1>; 5 #size-cells = <1>; 6 interrupt-parent = <&h8intc>; 7 8 chosen { 9 bootargs = "earlyprintk=h8300-sim"; 10 stdout-path = <&sci0>; 11 }; 12 aliases { 13 serial0 = &sci0; 14 serial1 = &sci1; 15 }; 16 17 xclk: oscillator { 18 #clock-cells = <0>; 19 compatible = "fixed-clock"; 20 clock-frequency = <20000000>; 21 clock-output-names = "xtal"; 22 }; 23 core_clk: core_clk { 24 compatible = "renesas,h8300-div-clock"; 25 clocks = <&xclk>; 26 #clock-cells = <0>; 27 reg = <0xfee01b 2>; 28 renesas,width = <2>; 29 }; 30 fclk: fclk { 31 compatible = "fixed-factor-clock"; 32 clocks = <&core_clk>; 33 #clock-cells = <0>; 34 clock-div = <1>; 35 clock-mult = <1>; 36 }; 37 38 memory@400000 { 39 device_type = "memory"; 40 reg = <0x400000 0x400000>; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 cpu@0 { 47 compatible = "renesas,h8300"; 48 clock-frequency = <20000000>; 49 }; 50 }; 51 52 h8intc: interrupt-controller@fee012 { 53 compatible = "renesas,h8300h-intc", "renesas,h8300-intc"; 54 #interrupt-cells = <2>; 55 interrupt-controller; 56 reg = <0xfee012 7>; 57 }; 58 59 bsc: memory-controller@fee01e { 60 compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc"; 61 reg = <0xfee01e 8>; 62 }; 63 64 timer8: timer@ffff80 { 65 compatible = "renesas,8bit-timer"; 66 reg = <0xffff80 10>; 67 interrupts = <36 0>; 68 clocks = <&fclk>; 69 clock-names = "fck"; 70 }; 71 72 timer16: timer@ffff68 { 73 compatible = "renesas,16bit-timer"; 74 reg = <0xffff68 8>, <0xffff60 8>; 75 interrupts = <24 0>; 76 renesas,channel = <0>; 77 clocks = <&fclk>; 78 clock-names = "fck"; 79 }; 80 81 sci0: serial@ffffb0 { 82 compatible = "renesas,sci"; 83 reg = <0xffffb0 8>; 84 interrupts = <52 0>, <53 0>, <54 0>, <55 0>; 85 clocks = <&fclk>; 86 clock-names = "sci_ick"; 87 }; 88 89 sci1: serial@ffffb8 { 90 compatible = "renesas,sci"; 91 reg = <0xffffb8 8>; 92 interrupts = <56 0>, <57 0>, <58 0>, <59 0>; 93 clocks = <&fclk>; 94 clock-names = "sci_ick"; 95 }; 96}; 97