1/*
2 * Blackfin cache control code (simpler control-style functions)
3 *
4 * Copyright 2004-2009 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <asm/blackfin.h>
10#include <asm/cplbinit.h>
11
12/* Invalidate the Entire Data cache by
13 * clearing DMC[1:0] bits
14 */
15void blackfin_invalidate_entire_dcache(void)
16{
17	u32 dmem = bfin_read_DMEM_CONTROL();
18	bfin_write_DMEM_CONTROL(dmem & ~0xc);
19	SSYNC();
20	bfin_write_DMEM_CONTROL(dmem);
21	SSYNC();
22}
23
24/* Invalidate the Entire Instruction cache by
25 * clearing IMC bit
26 */
27void blackfin_invalidate_entire_icache(void)
28{
29	u32 imem = bfin_read_IMEM_CONTROL();
30	bfin_write_IMEM_CONTROL(imem & ~0x4);
31	SSYNC();
32	bfin_write_IMEM_CONTROL(imem);
33	SSYNC();
34}
35
36#if defined(CONFIG_BFIN_ICACHE) || defined(CONFIG_BFIN_DCACHE)
37
38static void
39bfin_cache_init(struct cplb_entry *cplb_tbl, unsigned long cplb_addr,
40                unsigned long cplb_data, unsigned long mem_control,
41                unsigned long mem_mask)
42{
43	int i;
44#ifdef CONFIG_L1_PARITY_CHECK
45	u32 ctrl;
46
47	if (cplb_addr == DCPLB_ADDR0) {
48		ctrl = bfin_read32(mem_control) | (1 << RDCHK);
49		CSYNC();
50		bfin_write32(mem_control, ctrl);
51		SSYNC();
52	}
53#endif
54
55	for (i = 0; i < MAX_CPLBS; i++) {
56		bfin_write32(cplb_addr + i * 4, cplb_tbl[i].addr);
57		bfin_write32(cplb_data + i * 4, cplb_tbl[i].data);
58	}
59
60	_enable_cplb(mem_control, mem_mask);
61}
62
63#ifdef CONFIG_BFIN_ICACHE
64void bfin_icache_init(struct cplb_entry *icplb_tbl)
65{
66	bfin_cache_init(icplb_tbl, ICPLB_ADDR0, ICPLB_DATA0, IMEM_CONTROL,
67		(IMC | ENICPLB));
68}
69#endif
70
71#ifdef CONFIG_BFIN_DCACHE
72void bfin_dcache_init(struct cplb_entry *dcplb_tbl)
73{
74	/*
75	 *  Anomaly notes:
76	 *  05000287 - We implement workaround #2 - Change the DMEM_CONTROL
77	 *  register, so that the port preferences for DAG0 and DAG1 are set
78	 *  to port B
79	 */
80	bfin_cache_init(dcplb_tbl, DCPLB_ADDR0, DCPLB_DATA0, DMEM_CONTROL,
81		(DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0)));
82}
83#endif
84
85#endif
86