1/* 2 * Copyright 2008-2010 Analog Devices Inc. 3 * 4 * Licensed under the Clear BSD license or the GPL-2 (or later) 5 */ 6 7#ifndef _DEF_BF539_H 8#define _DEF_BF539_H 9 10#include "defBF538.h" 11 12/* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */ 13 14#define MXVR_CONFIG 0xFFC02700 /* MXVR Configuration Register */ 15#define MXVR_PLL_CTL_0 0xFFC02704 /* MXVR Phase Lock Loop Control Register 0 */ 16 17#define MXVR_STATE_0 0xFFC02708 /* MXVR State Register 0 */ 18#define MXVR_STATE_1 0xFFC0270C /* MXVR State Register 1 */ 19 20#define MXVR_INT_STAT_0 0xFFC02710 /* MXVR Interrupt Status Register 0 */ 21#define MXVR_INT_STAT_1 0xFFC02714 /* MXVR Interrupt Status Register 1 */ 22 23#define MXVR_INT_EN_0 0xFFC02718 /* MXVR Interrupt Enable Register 0 */ 24#define MXVR_INT_EN_1 0xFFC0271C /* MXVR Interrupt Enable Register 1 */ 25 26#define MXVR_POSITION 0xFFC02720 /* MXVR Node Position Register */ 27#define MXVR_MAX_POSITION 0xFFC02724 /* MXVR Maximum Node Position Register */ 28 29#define MXVR_DELAY 0xFFC02728 /* MXVR Node Frame Delay Register */ 30#define MXVR_MAX_DELAY 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */ 31 32#define MXVR_LADDR 0xFFC02730 /* MXVR Logical Address Register */ 33#define MXVR_GADDR 0xFFC02734 /* MXVR Group Address Register */ 34#define MXVR_AADDR 0xFFC02738 /* MXVR Alternate Address Register */ 35 36#define MXVR_ALLOC_0 0xFFC0273C /* MXVR Allocation Table Register 0 */ 37#define MXVR_ALLOC_1 0xFFC02740 /* MXVR Allocation Table Register 1 */ 38#define MXVR_ALLOC_2 0xFFC02744 /* MXVR Allocation Table Register 2 */ 39#define MXVR_ALLOC_3 0xFFC02748 /* MXVR Allocation Table Register 3 */ 40#define MXVR_ALLOC_4 0xFFC0274C /* MXVR Allocation Table Register 4 */ 41#define MXVR_ALLOC_5 0xFFC02750 /* MXVR Allocation Table Register 5 */ 42#define MXVR_ALLOC_6 0xFFC02754 /* MXVR Allocation Table Register 6 */ 43#define MXVR_ALLOC_7 0xFFC02758 /* MXVR Allocation Table Register 7 */ 44#define MXVR_ALLOC_8 0xFFC0275C /* MXVR Allocation Table Register 8 */ 45#define MXVR_ALLOC_9 0xFFC02760 /* MXVR Allocation Table Register 9 */ 46#define MXVR_ALLOC_10 0xFFC02764 /* MXVR Allocation Table Register 10 */ 47#define MXVR_ALLOC_11 0xFFC02768 /* MXVR Allocation Table Register 11 */ 48#define MXVR_ALLOC_12 0xFFC0276C /* MXVR Allocation Table Register 12 */ 49#define MXVR_ALLOC_13 0xFFC02770 /* MXVR Allocation Table Register 13 */ 50#define MXVR_ALLOC_14 0xFFC02774 /* MXVR Allocation Table Register 14 */ 51 52#define MXVR_SYNC_LCHAN_0 0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */ 53#define MXVR_SYNC_LCHAN_1 0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */ 54#define MXVR_SYNC_LCHAN_2 0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */ 55#define MXVR_SYNC_LCHAN_3 0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */ 56#define MXVR_SYNC_LCHAN_4 0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */ 57#define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */ 58#define MXVR_SYNC_LCHAN_6 0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */ 59#define MXVR_SYNC_LCHAN_7 0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */ 60 61#define MXVR_DMA0_CONFIG 0xFFC02798 /* MXVR Sync Data DMA0 Config Register */ 62#define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address Register */ 63#define MXVR_DMA0_COUNT 0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */ 64#define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address Register */ 65#define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count Register */ 66 67#define MXVR_DMA1_CONFIG 0xFFC027AC /* MXVR Sync Data DMA1 Config Register */ 68#define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address Register */ 69#define MXVR_DMA1_COUNT 0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */ 70#define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address Register */ 71#define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count Register */ 72 73#define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */ 74#define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address Register */ 75#define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */ 76#define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address Register */ 77#define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count Register */ 78 79#define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */ 80#define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address Register */ 81#define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */ 82#define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address Register */ 83#define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count Register */ 84 85#define MXVR_DMA4_CONFIG 0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */ 86#define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address Register */ 87#define MXVR_DMA4_COUNT 0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */ 88#define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address Register */ 89#define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count Register */ 90 91#define MXVR_DMA5_CONFIG 0xFFC027FC /* MXVR Sync Data DMA5 Config Register */ 92#define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address Register */ 93#define MXVR_DMA5_COUNT 0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */ 94#define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address Register */ 95#define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count Register */ 96 97#define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */ 98#define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address Register */ 99#define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */ 100#define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address Register */ 101#define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count Register */ 102 103#define MXVR_DMA7_CONFIG 0xFFC02824 /* MXVR Sync Data DMA7 Config Register */ 104#define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address Register */ 105#define MXVR_DMA7_COUNT 0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */ 106#define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address Register */ 107#define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count Register */ 108 109#define MXVR_AP_CTL 0xFFC02838 /* MXVR Async Packet Control Register */ 110#define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */ 111#define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */ 112#define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */ 113#define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */ 114 115#define MXVR_CM_CTL 0xFFC0284C /* MXVR Control Message Control Register */ 116#define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */ 117#define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */ 118#define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */ 119#define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */ 120 121#define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */ 122#define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */ 123 124#define MXVR_PAT_DATA_0 0xFFC02868 /* MXVR Pattern Data Register 0 */ 125#define MXVR_PAT_EN_0 0xFFC0286C /* MXVR Pattern Enable Register 0 */ 126#define MXVR_PAT_DATA_1 0xFFC02870 /* MXVR Pattern Data Register 1 */ 127#define MXVR_PAT_EN_1 0xFFC02874 /* MXVR Pattern Enable Register 1 */ 128 129#define MXVR_FRAME_CNT_0 0xFFC02878 /* MXVR Frame Counter 0 */ 130#define MXVR_FRAME_CNT_1 0xFFC0287C /* MXVR Frame Counter 1 */ 131 132#define MXVR_ROUTING_0 0xFFC02880 /* MXVR Routing Table Register 0 */ 133#define MXVR_ROUTING_1 0xFFC02884 /* MXVR Routing Table Register 1 */ 134#define MXVR_ROUTING_2 0xFFC02888 /* MXVR Routing Table Register 2 */ 135#define MXVR_ROUTING_3 0xFFC0288C /* MXVR Routing Table Register 3 */ 136#define MXVR_ROUTING_4 0xFFC02890 /* MXVR Routing Table Register 4 */ 137#define MXVR_ROUTING_5 0xFFC02894 /* MXVR Routing Table Register 5 */ 138#define MXVR_ROUTING_6 0xFFC02898 /* MXVR Routing Table Register 6 */ 139#define MXVR_ROUTING_7 0xFFC0289C /* MXVR Routing Table Register 7 */ 140#define MXVR_ROUTING_8 0xFFC028A0 /* MXVR Routing Table Register 8 */ 141#define MXVR_ROUTING_9 0xFFC028A4 /* MXVR Routing Table Register 9 */ 142#define MXVR_ROUTING_10 0xFFC028A8 /* MXVR Routing Table Register 10 */ 143#define MXVR_ROUTING_11 0xFFC028AC /* MXVR Routing Table Register 11 */ 144#define MXVR_ROUTING_12 0xFFC028B0 /* MXVR Routing Table Register 12 */ 145#define MXVR_ROUTING_13 0xFFC028B4 /* MXVR Routing Table Register 13 */ 146#define MXVR_ROUTING_14 0xFFC028B8 /* MXVR Routing Table Register 14 */ 147 148#define MXVR_PLL_CTL_1 0xFFC028BC /* MXVR Phase Lock Loop Control Register 1 */ 149#define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */ 150#define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */ 151 152#endif /* _DEF_BF539_H */ 153