1/*
2 * ARM Juno Platform motherboard peripherals
3 *
4 * Copyright (c) 2013-2014 ARM Ltd
5 *
6 * This file is licensed under a dual GPLv2 or BSD license.
7 *
8 */
9
10		mb_clk24mhz: clk24mhz {
11			compatible = "fixed-clock";
12			#clock-cells = <0>;
13			clock-frequency = <24000000>;
14			clock-output-names = "juno_mb:clk24mhz";
15		};
16
17		mb_clk25mhz: clk25mhz {
18			compatible = "fixed-clock";
19			#clock-cells = <0>;
20			clock-frequency = <25000000>;
21			clock-output-names = "juno_mb:clk25mhz";
22		};
23
24		v2m_refclk1mhz: refclk1mhz {
25			compatible = "fixed-clock";
26			#clock-cells = <0>;
27			clock-frequency = <1000000>;
28			clock-output-names = "juno_mb:refclk1mhz";
29		};
30
31		v2m_refclk32khz: refclk32khz {
32			compatible = "fixed-clock";
33			#clock-cells = <0>;
34			clock-frequency = <32768>;
35			clock-output-names = "juno_mb:refclk32khz";
36		};
37
38		motherboard {
39			compatible = "arm,vexpress,v2p-p1", "simple-bus";
40			#address-cells = <2>;  /* SMB chipselect number and offset */
41			#size-cells = <1>;
42			#interrupt-cells = <1>;
43			ranges;
44			model = "V2M-Juno";
45			arm,hbi = <0x252>;
46			arm,vexpress,site = <0>;
47			arm,v2m-memory-map = "rs1";
48
49			mb_fixed_3v3: fixedregulator@0 {
50				compatible = "regulator-fixed";
51				regulator-name = "MCC_SB_3V3";
52				regulator-min-microvolt = <3300000>;
53				regulator-max-microvolt = <3300000>;
54				regulator-always-on;
55			};
56
57			gpio_keys {
58				compatible = "gpio-keys";
59				#address-cells = <1>;
60				#size-cells = <0>;
61
62				button@1 {
63					debounce_interval = <50>;
64					wakeup-source;
65					linux,code = <116>;
66					label = "POWER";
67					gpios = <&iofpga_gpio0 0 0x4>;
68				};
69				button@2 {
70					debounce_interval = <50>;
71					wakeup-source;
72					linux,code = <102>;
73					label = "HOME";
74					gpios = <&iofpga_gpio0 1 0x4>;
75				};
76				button@3 {
77					debounce_interval = <50>;
78					wakeup-source;
79					linux,code = <152>;
80					label = "RLOCK";
81					gpios = <&iofpga_gpio0 2 0x4>;
82				};
83				button@4 {
84					debounce_interval = <50>;
85					wakeup-source;
86					linux,code = <115>;
87					label = "VOL+";
88					gpios = <&iofpga_gpio0 3 0x4>;
89				};
90				button@5 {
91					debounce_interval = <50>;
92					wakeup-source;
93					linux,code = <114>;
94					label = "VOL-";
95					gpios = <&iofpga_gpio0 4 0x4>;
96				};
97				button@6 {
98					debounce_interval = <50>;
99					wakeup-source;
100					linux,code = <99>;
101					label = "NMI";
102					gpios = <&iofpga_gpio0 5 0x4>;
103				};
104			};
105
106			flash@0,00000000 {
107				/* 2 * 32MiB NOR Flash memory mounted on CS0 */
108				compatible = "arm,vexpress-flash", "cfi-flash";
109				linux,part-probe = "afs";
110				reg = <0 0x00000000 0x04000000>;
111				bank-width = <4>;
112				/*
113				 * Unfortunately, accessing the flash disturbs
114				 * the CPU idle states (suspend) and CPU
115				 * hotplug of the platform. For this reason,
116				 * flash hardware access is disabled by default.
117				 */
118				status = "disabled";
119			};
120
121			ethernet@2,00000000 {
122				compatible = "smsc,lan9118", "smsc,lan9115";
123				reg = <2 0x00000000 0x10000>;
124				interrupts = <3>;
125				phy-mode = "mii";
126				reg-io-width = <4>;
127				smsc,irq-active-high;
128				smsc,irq-push-pull;
129				clocks = <&mb_clk25mhz>;
130				vdd33a-supply = <&mb_fixed_3v3>;
131				vddvario-supply = <&mb_fixed_3v3>;
132			};
133
134			usb@5,00000000 {
135				compatible = "nxp,usb-isp1763";
136				reg = <5 0x00000000 0x20000>;
137				bus-width = <16>;
138				interrupts = <4>;
139			};
140
141			iofpga@3,00000000 {
142				compatible = "arm,amba-bus", "simple-bus";
143				#address-cells = <1>;
144				#size-cells = <1>;
145				ranges = <0 3 0 0x200000>;
146
147				v2m_sysctl: sysctl@020000 {
148					compatible = "arm,sp810", "arm,primecell";
149					reg = <0x020000 0x1000>;
150					clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
151					clock-names = "refclk", "timclk", "apb_pclk";
152					#clock-cells = <1>;
153					clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
154					assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
155					assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
156				};
157
158				apbregs@010000 {
159					compatible = "syscon", "simple-mfd";
160					reg = <0x010000 0x1000>;
161
162					led@08.0 {
163						compatible = "register-bit-led";
164						offset = <0x08>;
165						mask = <0x01>;
166						label = "vexpress:0";
167						linux,default-trigger = "heartbeat";
168						default-state = "on";
169					};
170					led@08.1 {
171						compatible = "register-bit-led";
172						offset = <0x08>;
173						mask = <0x02>;
174						label = "vexpress:1";
175						linux,default-trigger = "mmc0";
176						default-state = "off";
177					};
178					led@08.2 {
179						compatible = "register-bit-led";
180						offset = <0x08>;
181						mask = <0x04>;
182						label = "vexpress:2";
183						linux,default-trigger = "cpu0";
184						default-state = "off";
185					};
186					led@08.3 {
187						compatible = "register-bit-led";
188						offset = <0x08>;
189						mask = <0x08>;
190						label = "vexpress:3";
191						linux,default-trigger = "cpu1";
192						default-state = "off";
193					};
194					led@08.4 {
195						compatible = "register-bit-led";
196						offset = <0x08>;
197						mask = <0x10>;
198						label = "vexpress:4";
199						linux,default-trigger = "cpu2";
200						default-state = "off";
201					};
202					led@08.5 {
203						compatible = "register-bit-led";
204						offset = <0x08>;
205						mask = <0x20>;
206						label = "vexpress:5";
207						linux,default-trigger = "cpu3";
208						default-state = "off";
209					};
210					led@08.6 {
211						compatible = "register-bit-led";
212						offset = <0x08>;
213						mask = <0x40>;
214						label = "vexpress:6";
215						default-state = "off";
216					};
217					led@08.7 {
218						compatible = "register-bit-led";
219						offset = <0x08>;
220						mask = <0x80>;
221						label = "vexpress:7";
222						default-state = "off";
223					};
224				};
225
226				mmci@050000 {
227					compatible = "arm,pl180", "arm,primecell";
228					reg = <0x050000 0x1000>;
229					interrupts = <5>;
230					/* cd-gpios = <&v2m_mmc_gpios 0 0>;
231					wp-gpios = <&v2m_mmc_gpios 1 0>; */
232					max-frequency = <12000000>;
233					vmmc-supply = <&mb_fixed_3v3>;
234					clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
235					clock-names = "mclk", "apb_pclk";
236				};
237
238				kmi@060000 {
239					compatible = "arm,pl050", "arm,primecell";
240					reg = <0x060000 0x1000>;
241					interrupts = <8>;
242					clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
243					clock-names = "KMIREFCLK", "apb_pclk";
244				};
245
246				kmi@070000 {
247					compatible = "arm,pl050", "arm,primecell";
248					reg = <0x070000 0x1000>;
249					interrupts = <8>;
250					clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
251					clock-names = "KMIREFCLK", "apb_pclk";
252				};
253
254				wdt@0f0000 {
255					compatible = "arm,sp805", "arm,primecell";
256					reg = <0x0f0000 0x10000>;
257					interrupts = <7>;
258					clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
259					clock-names = "wdogclk", "apb_pclk";
260				};
261
262				v2m_timer01: timer@110000 {
263					compatible = "arm,sp804", "arm,primecell";
264					reg = <0x110000 0x10000>;
265					interrupts = <9>;
266					clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
267					clock-names = "timclken1", "timclken2", "apb_pclk";
268				};
269
270				v2m_timer23: timer@120000 {
271					compatible = "arm,sp804", "arm,primecell";
272					reg = <0x120000 0x10000>;
273					interrupts = <9>;
274					clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
275					clock-names = "timclken1", "timclken2", "apb_pclk";
276				};
277
278				rtc@170000 {
279					compatible = "arm,pl031", "arm,primecell";
280					reg = <0x170000 0x10000>;
281					interrupts = <0>;
282					clocks = <&soc_smc50mhz>;
283					clock-names = "apb_pclk";
284				};
285
286				iofpga_gpio0: gpio@1d0000 {
287					compatible = "arm,pl061", "arm,primecell";
288					reg = <0x1d0000 0x1000>;
289					interrupts = <6>;
290					clocks = <&soc_smc50mhz>;
291					clock-names = "apb_pclk";
292					gpio-controller;
293					#gpio-cells = <2>;
294					interrupt-controller;
295					#interrupt-cells = <2>;
296				};
297			};
298		};
299