1# arch/arm/plat-samsung/Kconfig 2# 3# Copyright 2009 Simtec Electronics 4# 5# Licensed under GPLv2 6 7config PLAT_SAMSUNG 8 bool 9 depends on PLAT_S3C24XX || ARCH_S3C64XX || ARCH_EXYNOS || ARCH_S5PV210 10 default y 11 select GENERIC_IRQ_CHIP 12 select NO_IOPORT_MAP 13 help 14 Base platform code for all Samsung SoC based systems 15 16config SAMSUNG_PM 17 bool 18 depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX) 19 default y 20 help 21 Base platform power management code for samsung code 22 23if PLAT_SAMSUNG 24menu "Samsung Common options" 25 26# boot configurations 27 28comment "Boot options" 29 30config S3C_LOWLEVEL_UART_PORT 31 int "S3C UART to use for low-level messages" 32 depends on ARCH_S3C64XX 33 default 0 34 help 35 Choice of which UART port to use for the low-level messages, 36 such as the `Uncompressing...` at start time. The value of 37 this configuration should be between zero and two. The port 38 must have been initialised by the boot-loader before use. 39 40config SAMSUNG_ATAGS 41 def_bool n 42 depends on !ARCH_MULTIPLATFORM 43 depends on ATAGS 44 help 45 This option enables ATAGS based boot support code for 46 Samsung platforms, including static platform devices, legacy 47 clock, timer and interrupt initialization, etc. 48 49 Platforms that support only DT based boot need not to select 50 this option. 51 52if SAMSUNG_ATAGS 53 54config S3C_GPIO_SPACE 55 int "Space between gpio banks" 56 default 0 57 help 58 Add a number of spare GPIO entries between each bank for debugging 59 purposes. This allows any problems where an counter overflows from 60 one bank to another to be caught, at the expense of using a little 61 more memory. 62 63config S3C_GPIO_TRACK 64 bool 65 help 66 Internal configuration option to enable the s3c specific gpio 67 chip tracking if the platform requires it. 68 69# ADC driver 70 71config S3C_ADC 72 bool "ADC common driver support" 73 help 74 Core support for the ADC block found in the Samsung SoC systems 75 for drivers such as the touchscreen and hwmon to use to share 76 this resource. 77 78# device definitions to compile in 79 80config S3C_DEV_HSMMC 81 bool 82 help 83 Compile in platform device definitions for HSMMC code 84 85config S3C_DEV_HSMMC1 86 bool 87 help 88 Compile in platform device definitions for HSMMC channel 1 89 90config S3C_DEV_HSMMC2 91 bool 92 help 93 Compile in platform device definitions for HSMMC channel 2 94 95config S3C_DEV_HSMMC3 96 bool 97 help 98 Compile in platform device definitions for HSMMC channel 3 99 100config S3C_DEV_HWMON 101 bool 102 help 103 Compile in platform device definitions for HWMON 104 105config S3C_DEV_I2C1 106 bool 107 help 108 Compile in platform device definitions for I2C channel 1 109 110config S3C_DEV_I2C2 111 bool 112 help 113 Compile in platform device definitions for I2C channel 2 114 115config S3C_DEV_I2C3 116 bool 117 help 118 Compile in platform device definition for I2C controller 3 119 120config S3C_DEV_I2C4 121 bool 122 help 123 Compile in platform device definition for I2C controller 4 124 125config S3C_DEV_I2C5 126 bool 127 help 128 Compile in platform device definition for I2C controller 5 129 130config S3C_DEV_I2C6 131 bool 132 help 133 Compile in platform device definition for I2C controller 6 134 135config S3C_DEV_I2C7 136 bool 137 help 138 Compile in platform device definition for I2C controller 7 139 140config S3C_DEV_FB 141 bool 142 help 143 Compile in platform device definition for framebuffer 144 145config S3C_DEV_USB_HOST 146 bool 147 help 148 Compile in platform device definition for USB host. 149 150config S3C_DEV_USB_HSOTG 151 bool 152 help 153 Compile in platform device definition for USB high-speed OtG 154 155config S3C_DEV_WDT 156 bool 157 default y if ARCH_S3C24XX 158 help 159 Complie in platform device definition for Watchdog Timer 160 161config S3C_DEV_NAND 162 bool 163 help 164 Compile in platform device definition for NAND controller 165 166config S3C_DEV_ONENAND 167 bool 168 help 169 Compile in platform device definition for OneNAND controller 170 171config S3C_DEV_RTC 172 bool 173 help 174 Complie in platform device definition for RTC 175 176config SAMSUNG_DEV_ADC 177 bool 178 help 179 Compile in platform device definition for ADC controller 180 181config SAMSUNG_DEV_IDE 182 bool 183 help 184 Compile in platform device definitions for IDE 185 186config S3C64XX_DEV_SPI0 187 bool 188 help 189 Compile in platform device definitions for S3C64XX's type 190 SPI controller 0 191 192config S3C64XX_DEV_SPI1 193 bool 194 help 195 Compile in platform device definitions for S3C64XX's type 196 SPI controller 1 197 198config S3C64XX_DEV_SPI2 199 bool 200 help 201 Compile in platform device definitions for S3C64XX's type 202 SPI controller 2 203 204config SAMSUNG_DEV_TS 205 bool 206 help 207 Common in platform device definitions for touchscreen device 208 209config SAMSUNG_DEV_KEYPAD 210 bool 211 help 212 Compile in platform device definitions for keypad 213 214config SAMSUNG_DEV_PWM 215 bool 216 default y if ARCH_S3C24XX 217 help 218 Compile in platform device definition for PWM Timer 219 220config S3C24XX_PWM 221 bool "PWM device support" 222 select PWM 223 select PWM_SAMSUNG 224 help 225 Support for exporting the PWM timer blocks via the pwm device 226 system 227 228config SAMSUNG_PM_GPIO 229 bool 230 default y if GPIO_SAMSUNG && PM 231 help 232 Include legacy GPIO power management code for platforms not using 233 pinctrl-samsung driver. 234endif 235 236comment "Power management" 237 238config SAMSUNG_PM_DEBUG 239 bool "Samsung PM Suspend debug" 240 depends on PM && DEBUG_KERNEL 241 depends on DEBUG_EXYNOS_UART || DEBUG_S3C24XX_UART || DEBUG_S3C2410_UART 242 help 243 Say Y here if you want verbose debugging from the PM Suspend and 244 Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> 245 for more information. 246 247config S3C_PM_DEBUG_LED_SMDK 248 bool "SMDK LED suspend/resume debugging" 249 depends on PM && (MACH_SMDK6410) 250 help 251 Say Y here to enable the use of the SMDK LEDs on the baseboard 252 for debugging of the state of the suspend and resume process. 253 254 Note, this currently only works for S3C64XX based SMDK boards. 255 256config SAMSUNG_PM_CHECK 257 bool "S3C2410 PM Suspend Memory CRC" 258 depends on PM 259 select CRC32 260 help 261 Enable the PM code's memory area checksum over sleep. This option 262 will generate CRCs of all blocks of memory, and store them before 263 going to sleep. The blocks are then checked on resume for any 264 errors. 265 266 Note, this can take several seconds depending on memory size 267 and CPU speed. 268 269 See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> 270 271config SAMSUNG_PM_CHECK_CHUNKSIZE 272 int "S3C2410 PM Suspend CRC Chunksize (KiB)" 273 depends on PM && SAMSUNG_PM_CHECK 274 default 64 275 help 276 Set the chunksize in Kilobytes of the CRC for checking memory 277 corruption over suspend and resume. A smaller value will mean that 278 the CRC data block will take more memory, but wil identify any 279 faults with better precision. 280 281 See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> 282 283config SAMSUNG_WAKEMASK 284 bool 285 depends on PM 286 help 287 Compile support for wakeup-mask controls found on the S3C6400 288 and above. This code allows a set of interrupt to wakeup-mask 289 mappings. See <plat/wakeup-mask.h> 290 291config SAMSUNG_WDT_RESET 292 bool 293 help 294 Compile support for system restart by triggering watchdog reset. 295 Used on SoCs that do not provide dedicated reset control. 296 297config DEBUG_S3C_UART 298 depends on PLAT_SAMSUNG 299 int 300 default "0" if DEBUG_S3C_UART0 301 default "1" if DEBUG_S3C_UART1 302 default "2" if DEBUG_S3C_UART2 303 default "3" if DEBUG_S3C_UART3 304 305endmenu 306endif 307