1/*
2 * Copyright 2008 Openmoko, Inc.
3 * Copyright 2008 Simtec Electronics
4 *      http://armlinux.simtec.co.uk/
5 *      Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C64XX - syscon power and sleep control registers
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __MACH_S3C64XX_REGS_SYSCON_POWER_H
15#define __MACH_S3C64XX_REGS_SYSCON_POWER_H __FILE__
16
17#define S3C64XX_PWR_CFG				S3C_SYSREG(0x804)
18
19#define S3C64XX_PWRCFG_OSC_OTG_DISABLE		(1 << 17)
20#define S3C64XX_PWRCFG_MMC2_DISABLE		(1 << 16)
21#define S3C64XX_PWRCFG_MMC1_DISABLE		(1 << 15)
22#define S3C64XX_PWRCFG_MMC0_DISABLE		(1 << 14)
23#define S3C64XX_PWRCFG_HSI_DISABLE		(1 << 13)
24#define S3C64XX_PWRCFG_TS_DISABLE		(1 << 12)
25#define S3C64XX_PWRCFG_RTC_TICK_DISABLE		(1 << 11)
26#define S3C64XX_PWRCFG_RTC_ALARM_DISABLE	(1 << 10)
27#define S3C64XX_PWRCFG_MSM_DISABLE		(1 << 9)
28#define S3C64XX_PWRCFG_KEY_DISABLE		(1 << 8)
29#define S3C64XX_PWRCFG_BATF_DISABLE		(1 << 7)
30
31#define S3C64XX_PWRCFG_CFG_WFI_MASK		(0x3 << 5)
32#define S3C64XX_PWRCFG_CFG_WFI_SHIFT		(5)
33#define S3C64XX_PWRCFG_CFG_WFI_IGNORE		(0x0 << 5)
34#define S3C64XX_PWRCFG_CFG_WFI_IDLE		(0x1 << 5)
35#define S3C64XX_PWRCFG_CFG_WFI_STOP		(0x2 << 5)
36#define S3C64XX_PWRCFG_CFG_WFI_SLEEP		(0x3 << 5)
37
38#define S3C64XX_PWRCFG_CFG_BATFLT_MASK		(0x3 << 3)
39#define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT		(3)
40#define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE	(0x0 << 3)
41#define S3C64XX_PWRCFG_CFG_BATFLT_IRQ		(0x1 << 3)
42#define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP		(0x3 << 3)
43
44#define S3C64XX_PWRCFG_CFG_BAT_WAKE		(1 << 2)
45#define S3C64XX_PWRCFG_OSC27_EN			(1 << 0)
46
47#define S3C64XX_EINT_MASK			S3C_SYSREG(0x808)
48
49#define S3C64XX_NORMAL_CFG			S3C_SYSREG(0x810)
50
51#define S3C64XX_NORMALCFG_IROM_ON		(1 << 30)
52#define S3C64XX_NORMALCFG_DOMAIN_ETM_ON		(1 << 16)
53#define S3C64XX_NORMALCFG_DOMAIN_S_ON		(1 << 15)
54#define S3C64XX_NORMALCFG_DOMAIN_F_ON		(1 << 14)
55#define S3C64XX_NORMALCFG_DOMAIN_P_ON		(1 << 13)
56#define S3C64XX_NORMALCFG_DOMAIN_I_ON		(1 << 12)
57#define S3C64XX_NORMALCFG_DOMAIN_G_ON		(1 << 10)
58#define S3C64XX_NORMALCFG_DOMAIN_V_ON		(1 << 9)
59
60#define S3C64XX_STOP_CFG			S3C_SYSREG(0x814)
61
62#define S3C64XX_STOPCFG_MEMORY_ARM_ON		(1 << 29)
63#define S3C64XX_STOPCFG_TOP_MEMORY_ON		(1 << 20)
64#define S3C64XX_STOPCFG_ARM_LOGIC_ON		(1 << 17)
65#define S3C64XX_STOPCFG_TOP_LOGIC_ON		(1 << 8)
66#define S3C64XX_STOPCFG_OSC_EN			(1 << 0)
67
68#define S3C64XX_SLEEP_CFG			S3C_SYSREG(0x818)
69
70#define S3C64XX_SLEEPCFG_OSC_EN			(1 << 0)
71
72#define S3C64XX_STOP_MEM_CFG			S3C_SYSREG(0x81c)
73
74#define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN	(1 << 6)
75#define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN	(1 << 5)
76#define S3C64XX_STOPMEMCFG_OTG_RETAIN		(1 << 4)
77#define S3C64XX_STOPMEMCFG_HSMCC_RETAIN		(1 << 3)
78#define S3C64XX_STOPMEMCFG_IROM_RETAIN		(1 << 2)
79#define S3C64XX_STOPMEMCFG_IRDA_RETAIN		(1 << 1)
80#define S3C64XX_STOPMEMCFG_NFCON_RETAIN		(1 << 0)
81
82#define S3C64XX_OSC_STABLE			S3C_SYSREG(0x824)
83#define S3C64XX_PWR_STABLE			S3C_SYSREG(0x828)
84
85#define S3C64XX_WAKEUP_STAT			S3C_SYSREG(0x908)
86
87#define S3C64XX_WAKEUPSTAT_MMC2			(1 << 11)
88#define S3C64XX_WAKEUPSTAT_MMC1			(1 << 10)
89#define S3C64XX_WAKEUPSTAT_MMC0			(1 << 9)
90#define S3C64XX_WAKEUPSTAT_HSI			(1 << 8)
91#define S3C64XX_WAKEUPSTAT_BATFLT		(1 << 6)
92#define S3C64XX_WAKEUPSTAT_MSM			(1 << 5)
93#define S3C64XX_WAKEUPSTAT_KEY			(1 << 4)
94#define S3C64XX_WAKEUPSTAT_TS			(1 << 3)
95#define S3C64XX_WAKEUPSTAT_RTC_TICK		(1 << 2)
96#define S3C64XX_WAKEUPSTAT_RTC_ALARM		(1 << 1)
97#define S3C64XX_WAKEUPSTAT_EINT			(1 << 0)
98
99#define S3C64XX_BLK_PWR_STAT			S3C_SYSREG(0x90c)
100
101#define S3C64XX_BLKPWRSTAT_G			(1 << 7)
102#define S3C64XX_BLKPWRSTAT_ETM			(1 << 6)
103#define S3C64XX_BLKPWRSTAT_S			(1 << 5)
104#define S3C64XX_BLKPWRSTAT_F			(1 << 4)
105#define S3C64XX_BLKPWRSTAT_P			(1 << 3)
106#define S3C64XX_BLKPWRSTAT_I			(1 << 2)
107#define S3C64XX_BLKPWRSTAT_V			(1 << 1)
108#define S3C64XX_BLKPWRSTAT_TOP			(1 << 0)
109
110#define S3C64XX_INFORM0				S3C_SYSREG(0xA00)
111#define S3C64XX_INFORM1				S3C_SYSREG(0xA04)
112#define S3C64XX_INFORM2				S3C_SYSREG(0xA08)
113#define S3C64XX_INFORM3				S3C_SYSREG(0xA0C)
114
115#endif /* __MACH_S3C64XX_REGS_SYSCON_POWER_H */
116