1/*
2 * OMAP WakeupGen Source file
3 *
4 * OMAP WakeupGen is the interrupt controller extension used along
5 * with ARM GIC to wake the CPU out from low power states on
6 * external interrupts. It is responsible for generating wakeup
7 * event from the incoming interrupts and enable bits. It is
8 * implemented in MPU always ON power domain. During normal operation,
9 * WakeupGen delivers external interrupts directly to the GIC.
10 *
11 * Copyright (C) 2011 Texas Instruments, Inc.
12 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/irq.h>
23#include <linux/irqchip.h>
24#include <linux/irqdomain.h>
25#include <linux/of_address.h>
26#include <linux/platform_device.h>
27#include <linux/cpu.h>
28#include <linux/notifier.h>
29#include <linux/cpu_pm.h>
30
31#include "omap-wakeupgen.h"
32#include "omap-secure.h"
33
34#include "soc.h"
35#include "omap4-sar-layout.h"
36#include "common.h"
37#include "pm.h"
38
39#define AM43XX_NR_REG_BANKS	7
40#define AM43XX_IRQS		224
41#define MAX_NR_REG_BANKS	AM43XX_NR_REG_BANKS
42#define MAX_IRQS		AM43XX_IRQS
43#define DEFAULT_NR_REG_BANKS	5
44#define DEFAULT_IRQS		160
45#define WKG_MASK_ALL		0x00000000
46#define WKG_UNMASK_ALL		0xffffffff
47#define CPU_ENA_OFFSET		0x400
48#define CPU0_ID			0x0
49#define CPU1_ID			0x1
50#define OMAP4_NR_BANKS		4
51#define OMAP4_NR_IRQS		128
52
53static void __iomem *wakeupgen_base;
54static void __iomem *sar_base;
55static DEFINE_RAW_SPINLOCK(wakeupgen_lock);
56static unsigned int irq_target_cpu[MAX_IRQS];
57static unsigned int irq_banks = DEFAULT_NR_REG_BANKS;
58static unsigned int max_irqs = DEFAULT_IRQS;
59static unsigned int omap_secure_apis;
60
61/*
62 * Static helper functions.
63 */
64static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
65{
66	return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
67				(cpu * CPU_ENA_OFFSET) + (idx * 4));
68}
69
70static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
71{
72	writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
73				(cpu * CPU_ENA_OFFSET) + (idx * 4));
74}
75
76static inline void sar_writel(u32 val, u32 offset, u8 idx)
77{
78	writel_relaxed(val, sar_base + offset + (idx * 4));
79}
80
81static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
82{
83	/*
84	 * Each WakeupGen register controls 32 interrupt.
85	 * i.e. 1 bit per SPI IRQ
86	 */
87	*reg_index = irq >> 5;
88	*bit_posn = irq %= 32;
89
90	return 0;
91}
92
93static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
94{
95	u32 val, bit_number;
96	u8 i;
97
98	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
99		return;
100
101	val = wakeupgen_readl(i, cpu);
102	val &= ~BIT(bit_number);
103	wakeupgen_writel(val, i, cpu);
104}
105
106static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
107{
108	u32 val, bit_number;
109	u8 i;
110
111	if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
112		return;
113
114	val = wakeupgen_readl(i, cpu);
115	val |= BIT(bit_number);
116	wakeupgen_writel(val, i, cpu);
117}
118
119/*
120 * Architecture specific Mask extension
121 */
122static void wakeupgen_mask(struct irq_data *d)
123{
124	unsigned long flags;
125
126	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
127	_wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
128	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
129	irq_chip_mask_parent(d);
130}
131
132/*
133 * Architecture specific Unmask extension
134 */
135static void wakeupgen_unmask(struct irq_data *d)
136{
137	unsigned long flags;
138
139	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
140	_wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
141	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
142	irq_chip_unmask_parent(d);
143}
144
145#ifdef CONFIG_HOTPLUG_CPU
146static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
147
148static void _wakeupgen_save_masks(unsigned int cpu)
149{
150	u8 i;
151
152	for (i = 0; i < irq_banks; i++)
153		per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
154}
155
156static void _wakeupgen_restore_masks(unsigned int cpu)
157{
158	u8 i;
159
160	for (i = 0; i < irq_banks; i++)
161		wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
162}
163
164static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
165{
166	u8 i;
167
168	for (i = 0; i < irq_banks; i++)
169		wakeupgen_writel(reg, i, cpu);
170}
171
172/*
173 * Mask or unmask all interrupts on given CPU.
174 *	0 = Mask all interrupts on the 'cpu'
175 *	1 = Unmask all interrupts on the 'cpu'
176 * Ensure that the initial mask is maintained. This is faster than
177 * iterating through GIC registers to arrive at the correct masks.
178 */
179static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
180{
181	unsigned long flags;
182
183	raw_spin_lock_irqsave(&wakeupgen_lock, flags);
184	if (set) {
185		_wakeupgen_save_masks(cpu);
186		_wakeupgen_set_all(cpu, WKG_MASK_ALL);
187	} else {
188		_wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
189		_wakeupgen_restore_masks(cpu);
190	}
191	raw_spin_unlock_irqrestore(&wakeupgen_lock, flags);
192}
193#endif
194
195#ifdef CONFIG_CPU_PM
196static inline void omap4_irq_save_context(void)
197{
198	u32 i, val;
199
200	if (omap_rev() == OMAP4430_REV_ES1_0)
201		return;
202
203	for (i = 0; i < irq_banks; i++) {
204		/* Save the CPUx interrupt mask for IRQ 0 to 127 */
205		val = wakeupgen_readl(i, 0);
206		sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
207		val = wakeupgen_readl(i, 1);
208		sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
209
210		/*
211		 * Disable the secure interrupts for CPUx. The restore
212		 * code blindly restores secure and non-secure interrupt
213		 * masks from SAR RAM. Secure interrupts are not suppose
214		 * to be enabled from HLOS. So overwrite the SAR location
215		 * so that the secure interrupt remains disabled.
216		 */
217		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
218		sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
219	}
220
221	/* Save AuxBoot* registers */
222	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
223	writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
224	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
225	writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);
226
227	/* Save SyncReq generation logic */
228	val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
229	writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
230	val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
231	writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);
232
233	/* Set the Backup Bit Mask status */
234	val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
235	val |= SAR_BACKUP_STATUS_WAKEUPGEN;
236	writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
237
238}
239
240static inline void omap5_irq_save_context(void)
241{
242	u32 i, val;
243
244	for (i = 0; i < irq_banks; i++) {
245		/* Save the CPUx interrupt mask for IRQ 0 to 159 */
246		val = wakeupgen_readl(i, 0);
247		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
248		val = wakeupgen_readl(i, 1);
249		sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
250		sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
251		sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
252	}
253
254	/* Save AuxBoot* registers */
255	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
256	writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
257	val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
258	writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
259
260	/* Set the Backup Bit Mask status */
261	val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
262	val |= SAR_BACKUP_STATUS_WAKEUPGEN;
263	writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
264
265}
266
267/*
268 * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
269 * ROM code. WakeupGen IP is integrated along with GIC to manage the
270 * interrupt wakeups from CPU low power states. It manages
271 * masking/unmasking of Shared peripheral interrupts(SPI). So the
272 * interrupt enable/disable control should be in sync and consistent
273 * at WakeupGen and GIC so that interrupts are not lost.
274 */
275static void irq_save_context(void)
276{
277	if (!sar_base)
278		sar_base = omap4_get_sar_ram_base();
279
280	if (soc_is_omap54xx())
281		omap5_irq_save_context();
282	else
283		omap4_irq_save_context();
284}
285
286/*
287 * Clear WakeupGen SAR backup status.
288 */
289static void irq_sar_clear(void)
290{
291	u32 val;
292	u32 offset = SAR_BACKUP_STATUS_OFFSET;
293
294	if (soc_is_omap54xx())
295		offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
296
297	val = readl_relaxed(sar_base + offset);
298	val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
299	writel_relaxed(val, sar_base + offset);
300}
301
302/*
303 * Save GIC and Wakeupgen interrupt context using secure API
304 * for HS/EMU devices.
305 */
306static void irq_save_secure_context(void)
307{
308	u32 ret;
309	ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
310				FLAG_START_CRITICAL,
311				0, 0, 0, 0, 0);
312	if (ret != API_HAL_RET_VALUE_OK)
313		pr_err("GIC and Wakeupgen context save failed\n");
314}
315#endif
316
317#ifdef CONFIG_HOTPLUG_CPU
318static int irq_cpu_hotplug_notify(struct notifier_block *self,
319				  unsigned long action, void *hcpu)
320{
321	unsigned int cpu = (unsigned int)hcpu;
322
323	switch (action) {
324	case CPU_ONLINE:
325		wakeupgen_irqmask_all(cpu, 0);
326		break;
327	case CPU_DEAD:
328		wakeupgen_irqmask_all(cpu, 1);
329		break;
330	}
331	return NOTIFY_OK;
332}
333
334static struct notifier_block irq_hotplug_notifier = {
335	.notifier_call = irq_cpu_hotplug_notify,
336};
337
338static void __init irq_hotplug_init(void)
339{
340	register_hotcpu_notifier(&irq_hotplug_notifier);
341}
342#else
343static void __init irq_hotplug_init(void)
344{}
345#endif
346
347#ifdef CONFIG_CPU_PM
348static int irq_notifier(struct notifier_block *self, unsigned long cmd,	void *v)
349{
350	switch (cmd) {
351	case CPU_CLUSTER_PM_ENTER:
352		if (omap_type() == OMAP2_DEVICE_TYPE_GP)
353			irq_save_context();
354		else
355			irq_save_secure_context();
356		break;
357	case CPU_CLUSTER_PM_EXIT:
358		if (omap_type() == OMAP2_DEVICE_TYPE_GP)
359			irq_sar_clear();
360		break;
361	}
362	return NOTIFY_OK;
363}
364
365static struct notifier_block irq_notifier_block = {
366	.notifier_call = irq_notifier,
367};
368
369static void __init irq_pm_init(void)
370{
371	/* FIXME: Remove this when MPU OSWR support is added */
372	if (!IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
373		cpu_pm_register_notifier(&irq_notifier_block);
374}
375#else
376static void __init irq_pm_init(void)
377{}
378#endif
379
380void __iomem *omap_get_wakeupgen_base(void)
381{
382	return wakeupgen_base;
383}
384
385int omap_secure_apis_support(void)
386{
387	return omap_secure_apis;
388}
389
390static struct irq_chip wakeupgen_chip = {
391	.name			= "WUGEN",
392	.irq_eoi		= irq_chip_eoi_parent,
393	.irq_mask		= wakeupgen_mask,
394	.irq_unmask		= wakeupgen_unmask,
395	.irq_retrigger		= irq_chip_retrigger_hierarchy,
396	.irq_set_type		= irq_chip_set_type_parent,
397	.flags			= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
398#ifdef CONFIG_SMP
399	.irq_set_affinity	= irq_chip_set_affinity_parent,
400#endif
401};
402
403static int wakeupgen_domain_translate(struct irq_domain *d,
404				      struct irq_fwspec *fwspec,
405				      unsigned long *hwirq,
406				      unsigned int *type)
407{
408	if (is_of_node(fwspec->fwnode)) {
409		if (fwspec->param_count != 3)
410			return -EINVAL;
411
412		/* No PPI should point to this domain */
413		if (fwspec->param[0] != 0)
414			return -EINVAL;
415
416		*hwirq = fwspec->param[1];
417		*type = fwspec->param[2];
418		return 0;
419	}
420
421	return -EINVAL;
422}
423
424static int wakeupgen_domain_alloc(struct irq_domain *domain,
425				  unsigned int virq,
426				  unsigned int nr_irqs, void *data)
427{
428	struct irq_fwspec *fwspec = data;
429	struct irq_fwspec parent_fwspec;
430	irq_hw_number_t hwirq;
431	int i;
432
433	if (fwspec->param_count != 3)
434		return -EINVAL;	/* Not GIC compliant */
435	if (fwspec->param[0] != 0)
436		return -EINVAL;	/* No PPI should point to this domain */
437
438	hwirq = fwspec->param[1];
439	if (hwirq >= MAX_IRQS)
440		return -EINVAL;	/* Can't deal with this */
441
442	for (i = 0; i < nr_irqs; i++)
443		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
444					      &wakeupgen_chip, NULL);
445
446	parent_fwspec = *fwspec;
447	parent_fwspec.fwnode = domain->parent->fwnode;
448	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
449					    &parent_fwspec);
450}
451
452static const struct irq_domain_ops wakeupgen_domain_ops = {
453	.translate	= wakeupgen_domain_translate,
454	.alloc		= wakeupgen_domain_alloc,
455	.free		= irq_domain_free_irqs_common,
456};
457
458/*
459 * Initialise the wakeupgen module.
460 */
461static int __init wakeupgen_init(struct device_node *node,
462				 struct device_node *parent)
463{
464	struct irq_domain *parent_domain, *domain;
465	int i;
466	unsigned int boot_cpu = smp_processor_id();
467	u32 val;
468
469	if (!parent) {
470		pr_err("%s: no parent, giving up\n", node->full_name);
471		return -ENODEV;
472	}
473
474	parent_domain = irq_find_host(parent);
475	if (!parent_domain) {
476		pr_err("%s: unable to obtain parent domain\n", node->full_name);
477		return -ENXIO;
478	}
479	/* Not supported on OMAP4 ES1.0 silicon */
480	if (omap_rev() == OMAP4430_REV_ES1_0) {
481		WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
482		return -EPERM;
483	}
484
485	/* Static mapping, never released */
486	wakeupgen_base = of_iomap(node, 0);
487	if (WARN_ON(!wakeupgen_base))
488		return -ENOMEM;
489
490	if (cpu_is_omap44xx()) {
491		irq_banks = OMAP4_NR_BANKS;
492		max_irqs = OMAP4_NR_IRQS;
493		omap_secure_apis = 1;
494	} else if (soc_is_am43xx()) {
495		irq_banks = AM43XX_NR_REG_BANKS;
496		max_irqs = AM43XX_IRQS;
497	}
498
499	domain = irq_domain_add_hierarchy(parent_domain, 0, max_irqs,
500					  node, &wakeupgen_domain_ops,
501					  NULL);
502	if (!domain) {
503		iounmap(wakeupgen_base);
504		return -ENOMEM;
505	}
506
507	/* Clear all IRQ bitmasks at wakeupGen level */
508	for (i = 0; i < irq_banks; i++) {
509		wakeupgen_writel(0, i, CPU0_ID);
510		if (!soc_is_am43xx())
511			wakeupgen_writel(0, i, CPU1_ID);
512	}
513
514	/*
515	 * FIXME: Add support to set_smp_affinity() once the core
516	 * GIC code has necessary hooks in place.
517	 */
518
519	/* Associate all the IRQs to boot CPU like GIC init does. */
520	for (i = 0; i < max_irqs; i++)
521		irq_target_cpu[i] = boot_cpu;
522
523	/*
524	 * Enables OMAP5 ES2 PM Mode using ES2_PM_MODE in AMBA_IF_MODE
525	 * 0x0:	ES1 behavior, CPU cores would enter and exit OFF mode together.
526	 * 0x1:	ES2 behavior, CPU cores are allowed to enter/exit OFF mode
527	 * independently.
528	 * This needs to be set one time thanks to always ON domain.
529	 *
530	 * We do not support ES1 behavior anymore. OMAP5 is assumed to be
531	 * ES2.0, and the same is applicable for DRA7.
532	 */
533	if (soc_is_omap54xx() || soc_is_dra7xx()) {
534		val = __raw_readl(wakeupgen_base + OMAP_AMBA_IF_MODE);
535		val |= BIT(5);
536		omap_smc1(OMAP5_MON_AMBA_IF_INDEX, val);
537	}
538
539	irq_hotplug_init();
540	irq_pm_init();
541
542	return 0;
543}
544IRQCHIP_DECLARE(ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);
545