1/*
2 * Device Tree support for Armada 370 and XP platforms.
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2.  This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/of_address.h>
18#include <linux/of_fdt.h>
19#include <linux/of_platform.h>
20#include <linux/io.h>
21#include <linux/clocksource.h>
22#include <linux/dma-mapping.h>
23#include <linux/memblock.h>
24#include <linux/mbus.h>
25#include <linux/slab.h>
26#include <linux/irqchip.h>
27#include <asm/hardware/cache-l2x0.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/time.h>
31#include <asm/smp_scu.h>
32#include "armada-370-xp.h"
33#include "common.h"
34#include "coherency.h"
35#include "mvebu-soc-id.h"
36
37static void __iomem *scu_base;
38
39/*
40 * Enables the SCU when available. Obviously, this is only useful on
41 * Cortex-A based SOCs, not on PJ4B based ones.
42 */
43static void __init mvebu_scu_enable(void)
44{
45	struct device_node *np =
46		of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
47	if (np) {
48		scu_base = of_iomap(np, 0);
49		scu_enable(scu_base);
50		of_node_put(np);
51	}
52}
53
54void __iomem *mvebu_get_scu_base(void)
55{
56	return scu_base;
57}
58
59/*
60 * When returning from suspend, the platform goes through the
61 * bootloader, which executes its DDR3 training code. This code has
62 * the unfortunate idea of using the first 10 KB of each DRAM bank to
63 * exercise the RAM and calculate the optimal timings. Therefore, this
64 * area of RAM is overwritten, and shouldn't be used by the kernel if
65 * suspend/resume is supported.
66 */
67
68#ifdef CONFIG_SUSPEND
69#define MVEBU_DDR_TRAINING_AREA_SZ (10 * SZ_1K)
70static int __init mvebu_scan_mem(unsigned long node, const char *uname,
71				 int depth, void *data)
72{
73	const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
74	const __be32 *reg, *endp;
75	int l;
76
77	if (type == NULL || strcmp(type, "memory"))
78		return 0;
79
80	reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
81	if (reg == NULL)
82		reg = of_get_flat_dt_prop(node, "reg", &l);
83	if (reg == NULL)
84		return 0;
85
86	endp = reg + (l / sizeof(__be32));
87	while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
88		u64 base, size;
89
90		base = dt_mem_next_cell(dt_root_addr_cells, &reg);
91		size = dt_mem_next_cell(dt_root_size_cells, &reg);
92
93		memblock_reserve(base, MVEBU_DDR_TRAINING_AREA_SZ);
94	}
95
96	return 0;
97}
98
99static void __init mvebu_memblock_reserve(void)
100{
101	of_scan_flat_dt(mvebu_scan_mem, NULL);
102}
103#else
104static void __init mvebu_memblock_reserve(void) {}
105#endif
106
107static void __init mvebu_init_irq(void)
108{
109	irqchip_init();
110	mvebu_scu_enable();
111	coherency_init();
112	BUG_ON(mvebu_mbus_dt_init(coherency_available()));
113}
114
115static void __init i2c_quirk(void)
116{
117	struct device_node *np;
118	u32 dev, rev;
119
120	/*
121	 * Only revisons more recent than A0 support the offload
122	 * mechanism. We can exit only if we are sure that we can
123	 * get the SoC revision and it is more recent than A0.
124	 */
125	if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > MV78XX0_A0_REV)
126		return;
127
128	for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") {
129		struct property *new_compat;
130
131		new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL);
132
133		new_compat->name = kstrdup("compatible", GFP_KERNEL);
134		new_compat->length = sizeof("marvell,mv78230-a0-i2c");
135		new_compat->value = kstrdup("marvell,mv78230-a0-i2c",
136						GFP_KERNEL);
137
138		of_update_property(np, new_compat);
139	}
140	return;
141}
142
143static void __init mvebu_dt_init(void)
144{
145	if (of_machine_is_compatible("marvell,armadaxp"))
146		i2c_quirk();
147
148	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
149}
150
151static const char * const armada_370_xp_dt_compat[] __initconst = {
152	"marvell,armada-370-xp",
153	NULL,
154};
155
156DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
157	.l2c_aux_val	= 0,
158	.l2c_aux_mask	= ~0,
159/*
160 * The following field (.smp) is still needed to ensure backward
161 * compatibility with old Device Trees that were not specifying the
162 * cpus enable-method property.
163 */
164	.smp		= smp_ops(armada_xp_smp_ops),
165	.init_machine	= mvebu_dt_init,
166	.init_irq       = mvebu_init_irq,
167	.restart	= mvebu_restart,
168	.reserve        = mvebu_memblock_reserve,
169	.dt_compat	= armada_370_xp_dt_compat,
170MACHINE_END
171
172static const char * const armada_375_dt_compat[] __initconst = {
173	"marvell,armada375",
174	NULL,
175};
176
177DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
178	.l2c_aux_val	= 0,
179	.l2c_aux_mask	= ~0,
180	.init_irq       = mvebu_init_irq,
181	.init_machine	= mvebu_dt_init,
182	.restart	= mvebu_restart,
183	.dt_compat	= armada_375_dt_compat,
184MACHINE_END
185
186static const char * const armada_38x_dt_compat[] __initconst = {
187	"marvell,armada380",
188	"marvell,armada385",
189	NULL,
190};
191
192DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
193	.l2c_aux_val	= 0,
194	.l2c_aux_mask	= ~0,
195	.init_irq       = mvebu_init_irq,
196	.restart	= mvebu_restart,
197	.dt_compat	= armada_38x_dt_compat,
198MACHINE_END
199
200static const char * const armada_39x_dt_compat[] __initconst = {
201	"marvell,armada390",
202	"marvell,armada398",
203	NULL,
204};
205
206DT_MACHINE_START(ARMADA_39X_DT, "Marvell Armada 39x (Device Tree)")
207	.l2c_aux_val	= 0,
208	.l2c_aux_mask	= ~0,
209	.init_irq       = mvebu_init_irq,
210	.restart	= mvebu_restart,
211	.dt_compat	= armada_39x_dt_compat,
212MACHINE_END
213