1/* 2 * iop13xx PCI support 3 * Copyright (c) 2005-2006, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple 16 * Place - Suite 330, Boston, MA 02111-1307 USA. 17 * 18 */ 19 20#include <linux/pci.h> 21#include <linux/slab.h> 22#include <linux/delay.h> 23#include <linux/jiffies.h> 24#include <linux/export.h> 25#include <asm/irq.h> 26#include <mach/hardware.h> 27#include <asm/sizes.h> 28#include <asm/signal.h> 29#include <asm/mach/pci.h> 30#include <mach/pci.h> 31 32#define IOP13XX_PCI_DEBUG 0 33#define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x))) 34 35u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */ 36u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */ 37static struct pci_bus *pci_bus_atux = 0; 38static struct pci_bus *pci_bus_atue = 0; 39void __iomem *iop13xx_atue_mem_base; 40void __iomem *iop13xx_atux_mem_base; 41size_t iop13xx_atue_mem_size; 42size_t iop13xx_atux_mem_size; 43 44EXPORT_SYMBOL(iop13xx_atue_mem_base); 45EXPORT_SYMBOL(iop13xx_atux_mem_base); 46EXPORT_SYMBOL(iop13xx_atue_mem_size); 47EXPORT_SYMBOL(iop13xx_atux_mem_size); 48 49int init_atu = 0; /* Flag to select which ATU(s) to initialize / disable */ 50static unsigned long atux_trhfa_timeout = 0; /* Trhfa = RST# high to first 51 access */ 52 53/* Scan the initialized busses and ioremap the requested memory range 54 */ 55void iop13xx_map_pci_memory(void) 56{ 57 int atu; 58 struct pci_bus *bus; 59 struct pci_dev *dev; 60 resource_size_t end = 0; 61 62 for (atu = 0; atu < 2; atu++) { 63 bus = atu ? pci_bus_atue : pci_bus_atux; 64 if (bus) { 65 list_for_each_entry(dev, &bus->devices, bus_list) { 66 int i; 67 int max = 7; 68 69 if (dev->subordinate) 70 max = DEVICE_COUNT_RESOURCE; 71 72 for (i = 0; i < max; i++) { 73 struct resource *res = &dev->resource[i]; 74 if (res->flags & IORESOURCE_MEM) 75 end = max(res->end, end); 76 } 77 } 78 79 switch(atu) { 80 case 0: 81 iop13xx_atux_mem_size = 82 (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1; 83 84 /* 16MB align the request */ 85 if (iop13xx_atux_mem_size & (SZ_16M - 1)) { 86 iop13xx_atux_mem_size &= ~(SZ_16M - 1); 87 iop13xx_atux_mem_size += SZ_16M; 88 } 89 90 if (end) { 91 iop13xx_atux_mem_base = __arm_ioremap_pfn( 92 __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA) 93 , 0, iop13xx_atux_mem_size, MT_DEVICE); 94 if (!iop13xx_atux_mem_base) { 95 printk("%s: atux allocation " 96 "failed\n", __func__); 97 BUG(); 98 } 99 } else 100 iop13xx_atux_mem_size = 0; 101 PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n", 102 __func__, atu, iop13xx_atux_mem_size, 103 iop13xx_atux_mem_base); 104 break; 105 case 1: 106 iop13xx_atue_mem_size = 107 (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1; 108 109 /* 16MB align the request */ 110 if (iop13xx_atue_mem_size & (SZ_16M - 1)) { 111 iop13xx_atue_mem_size &= ~(SZ_16M - 1); 112 iop13xx_atue_mem_size += SZ_16M; 113 } 114 115 if (end) { 116 iop13xx_atue_mem_base = __arm_ioremap_pfn( 117 __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA) 118 , 0, iop13xx_atue_mem_size, MT_DEVICE); 119 if (!iop13xx_atue_mem_base) { 120 printk("%s: atue allocation " 121 "failed\n", __func__); 122 BUG(); 123 } 124 } else 125 iop13xx_atue_mem_size = 0; 126 PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n", 127 __func__, atu, iop13xx_atue_mem_size, 128 iop13xx_atue_mem_base); 129 break; 130 } 131 132 printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n", 133 atu ? "ATUE" : "ATUX", 134 (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) / 135 SZ_1M, 136 atu ? IOP13XX_PCIE_LOWER_MEM_RA : 137 IOP13XX_PCIX_LOWER_MEM_RA, 138 atu ? iop13xx_atue_mem_base : 139 iop13xx_atux_mem_base); 140 end = 0; 141 } 142 143 } 144} 145 146static int iop13xx_atu_function(int atu) 147{ 148 int func = 0; 149 /* the function number depends on the value of the 150 * IOP13XX_INTERFACE_SEL_PCIX reset strap 151 * see C-Spec section 3.17 152 */ 153 switch(atu) { 154 case IOP13XX_INIT_ATU_ATUX: 155 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) 156 func = 5; 157 else 158 func = 0; 159 break; 160 case IOP13XX_INIT_ATU_ATUE: 161 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) 162 func = 0; 163 else 164 func = 5; 165 break; 166 default: 167 BUG(); 168 } 169 170 return func; 171} 172 173/* iop13xx_atux_cfg_address - format a configuration address for atux 174 * @bus: Target bus to access 175 * @devfn: Combined device number and function number 176 * @where: Desired register's address offset 177 * 178 * Convert the parameters to a configuration address formatted 179 * according the PCI-X 2.0 specification 180 */ 181static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where) 182{ 183 struct pci_sys_data *sys = bus->sysdata; 184 u32 addr; 185 186 if (sys->busnr == bus->number) 187 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); 188 else 189 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; 190 191 addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3); 192 addr |= ((where & 0xf00) >> 8) << 24; /* upper register number */ 193 194 return addr; 195} 196 197/* iop13xx_atue_cfg_address - format a configuration address for atue 198 * @bus: Target bus to access 199 * @devfn: Combined device number and function number 200 * @where: Desired register's address offset 201 * 202 * Convert the parameters to an address usable by the ATUE_OCCAR 203 */ 204static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where) 205{ 206 struct pci_sys_data *sys = bus->sysdata; 207 u32 addr; 208 209 PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d", 210 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); 211 addr = ((u32) bus->number) << IOP13XX_ATUE_OCCAR_BUS_NUM | 212 ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM | 213 ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM | 214 (where & ~0x3); 215 216 if (sys->busnr != bus->number) 217 addr |= 1; /* type 1 access */ 218 219 return addr; 220} 221 222/* This routine checks the status of the last configuration cycle. If an error 223 * was detected it returns >0, else it returns a 0. The errors being checked 224 * are parity, master abort, target abort (master and target). These types of 225 * errors occur during a config cycle where there is no device, like during 226 * the discovery stage. 227 */ 228static int iop13xx_atux_pci_status(int clear) 229{ 230 unsigned int status; 231 int err = 0; 232 233 /* 234 * Check the status registers. 235 */ 236 status = __raw_readw(IOP13XX_ATUX_ATUSR); 237 if (status & IOP_PCI_STATUS_ERROR) 238 { 239 PRINTK("\t\t\tPCI error: ATUSR %#08x", status); 240 if(clear) 241 __raw_writew(status & IOP_PCI_STATUS_ERROR, 242 IOP13XX_ATUX_ATUSR); 243 err = 1; 244 } 245 status = __raw_readl(IOP13XX_ATUX_ATUISR); 246 if (status & IOP13XX_ATUX_ATUISR_ERROR) 247 { 248 PRINTK("\t\t\tPCI error interrupt: ATUISR %#08x", status); 249 if(clear) 250 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR, 251 IOP13XX_ATUX_ATUISR); 252 err = 1; 253 } 254 return err; 255} 256 257/* Simply write the address register and read the configuration 258 * data. Note that the data dependency on %0 encourages an abort 259 * to be detected before we return. 260 */ 261static u32 iop13xx_atux_read(unsigned long addr) 262{ 263 u32 val; 264 265 __asm__ __volatile__( 266 "str %1, [%2]\n\t" 267 "ldr %0, [%3]\n\t" 268 "mov %0, %0\n\t" 269 : "=r" (val) 270 : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR)); 271 272 return val; 273} 274 275/* The read routines must check the error status of the last configuration 276 * cycle. If there was an error, the routine returns all hex f's. 277 */ 278static int 279iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where, 280 int size, u32 *value) 281{ 282 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where); 283 u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8); 284 285 if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) { 286 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, 287 IOP13XX_XBG_BECSR); 288 val = 0xffffffff; 289 } 290 291 *value = val; 292 293 return PCIBIOS_SUCCESSFUL; 294} 295 296static int 297iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where, 298 int size, u32 value) 299{ 300 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where); 301 u32 val; 302 303 if (size != 4) { 304 val = iop13xx_atux_read(addr); 305 if (!iop13xx_atux_pci_status(1) == 0) 306 return PCIBIOS_SUCCESSFUL; 307 308 where = (where & 3) * 8; 309 310 if (size == 1) 311 val &= ~(0xff << where); 312 else 313 val &= ~(0xffff << where); 314 315 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR); 316 } else { 317 __raw_writel(addr, IOP13XX_ATUX_OCCAR); 318 __raw_writel(value, IOP13XX_ATUX_OCCDR); 319 } 320 321 return PCIBIOS_SUCCESSFUL; 322} 323 324static struct pci_ops iop13xx_atux_ops = { 325 .read = iop13xx_atux_read_config, 326 .write = iop13xx_atux_write_config, 327}; 328 329/* This routine checks the status of the last configuration cycle. If an error 330 * was detected it returns >0, else it returns a 0. The errors being checked 331 * are parity, master abort, target abort (master and target). These types of 332 * errors occur during a config cycle where there is no device, like during 333 * the discovery stage. 334 */ 335static int iop13xx_atue_pci_status(int clear) 336{ 337 unsigned int status; 338 int err = 0; 339 340 /* 341 * Check the status registers. 342 */ 343 344 /* standard pci status register */ 345 status = __raw_readw(IOP13XX_ATUE_ATUSR); 346 if (status & IOP_PCI_STATUS_ERROR) { 347 PRINTK("\t\t\tPCI error: ATUSR %#08x", status); 348 if(clear) 349 __raw_writew(status & IOP_PCI_STATUS_ERROR, 350 IOP13XX_ATUE_ATUSR); 351 err++; 352 } 353 354 /* check the normal status bits in the ATUISR */ 355 status = __raw_readl(IOP13XX_ATUE_ATUISR); 356 if (status & IOP13XX_ATUE_ATUISR_ERROR) { 357 PRINTK("\t\t\tPCI error: ATUISR %#08x", status); 358 if (clear) 359 __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR, 360 IOP13XX_ATUE_ATUISR); 361 err++; 362 363 /* check the PCI-E status if the ATUISR reports an interface error */ 364 if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) { 365 /* get the unmasked errors */ 366 status = __raw_readl(IOP13XX_ATUE_PIE_STS) & 367 ~(__raw_readl(IOP13XX_ATUE_PIE_MSK)); 368 369 if (status) { 370 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x", 371 __raw_readl(IOP13XX_ATUE_PIE_STS)); 372 err++; 373 } else { 374 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x", 375 __raw_readl(IOP13XX_ATUE_PIE_STS)); 376 PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x", 377 __raw_readl(IOP13XX_ATUE_PIE_MSK)); 378 BUG(); 379 } 380 381 if(clear) 382 __raw_writel(status, IOP13XX_ATUE_PIE_STS); 383 } 384 } 385 386 return err; 387} 388 389static int 390iop13xx_pcie_map_irq(const struct pci_dev *dev, u8 idsel, u8 pin) 391{ 392 WARN_ON(idsel != 0); 393 394 switch (pin) { 395 case 1: return ATUE_INTA; 396 case 2: return ATUE_INTB; 397 case 3: return ATUE_INTC; 398 case 4: return ATUE_INTD; 399 default: return -1; 400 } 401} 402 403static u32 iop13xx_atue_read(unsigned long addr) 404{ 405 u32 val; 406 407 __raw_writel(addr, IOP13XX_ATUE_OCCAR); 408 val = __raw_readl(IOP13XX_ATUE_OCCDR); 409 410 rmb(); 411 412 return val; 413} 414 415/* The read routines must check the error status of the last configuration 416 * cycle. If there was an error, the routine returns all hex f's. 417 */ 418static int 419iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where, 420 int size, u32 *value) 421{ 422 u32 val; 423 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where); 424 425 /* Hide device numbers > 0 on the local PCI-E bus (Type 0 access) */ 426 if (!PCI_SLOT(devfn) || (addr & 1)) { 427 val = iop13xx_atue_read(addr) >> ((where & 3) * 8); 428 if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) { 429 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, 430 IOP13XX_XBG_BECSR); 431 val = 0xffffffff; 432 } 433 434 PRINTK("addr=%#0lx, val=%#010x", addr, val); 435 } else 436 val = 0xffffffff; 437 438 *value = val; 439 440 return PCIBIOS_SUCCESSFUL; 441} 442 443static int 444iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where, 445 int size, u32 value) 446{ 447 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where); 448 u32 val; 449 450 if (size != 4) { 451 val = iop13xx_atue_read(addr); 452 if (!iop13xx_atue_pci_status(1) == 0) 453 return PCIBIOS_SUCCESSFUL; 454 455 where = (where & 3) * 8; 456 457 if (size == 1) 458 val &= ~(0xff << where); 459 else 460 val &= ~(0xffff << where); 461 462 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR); 463 } else { 464 __raw_writel(addr, IOP13XX_ATUE_OCCAR); 465 __raw_writel(value, IOP13XX_ATUE_OCCDR); 466 } 467 468 return PCIBIOS_SUCCESSFUL; 469} 470 471static struct pci_ops iop13xx_atue_ops = { 472 .read = iop13xx_atue_read_config, 473 .write = iop13xx_atue_write_config, 474}; 475 476/* When a PCI device does not exist during config cycles, the XScale gets a 477 * bus error instead of returning 0xffffffff. We can't rely on the ATU status 478 * bits to tell us that it was indeed a configuration cycle that caused this 479 * error especially in the case when the ATUE link is down. Instead we rely 480 * on data from the south XSI bridge to validate the abort 481 */ 482int 483iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) 484{ 485 PRINTK("Data abort: address = 0x%08lx " 486 "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx", 487 addr, fsr, regs->ARM_pc, regs->ARM_lr); 488 489 PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR)); 490 PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR)); 491 PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR)); 492 493 /* If it was an imprecise abort, then we need to correct the 494 * return address to be _after_ the instruction. 495 */ 496 if (fsr & (1 << 10)) 497 regs->ARM_pc += 4; 498 499 if (is_atue_occdr_error() || is_atux_occdr_error()) 500 return 0; 501 else 502 return 1; 503} 504 505/* Scan an IOP13XX PCI bus. nr selects which ATU we use. 506 */ 507struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys) 508{ 509 int which_atu; 510 struct pci_bus *bus = NULL; 511 512 switch (init_atu) { 513 case IOP13XX_INIT_ATU_ATUX: 514 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX; 515 break; 516 case IOP13XX_INIT_ATU_ATUE: 517 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE; 518 break; 519 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE): 520 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX; 521 break; 522 default: 523 which_atu = 0; 524 } 525 526 if (!which_atu) { 527 BUG(); 528 return NULL; 529 } 530 531 switch (which_atu) { 532 case IOP13XX_INIT_ATU_ATUX: 533 if (time_after_eq(jiffies + msecs_to_jiffies(1000), 534 atux_trhfa_timeout)) /* ensure not wrap */ 535 while(time_before(jiffies, atux_trhfa_timeout)) 536 udelay(100); 537 538 bus = pci_bus_atux = pci_scan_root_bus(NULL, sys->busnr, 539 &iop13xx_atux_ops, 540 sys, &sys->resources); 541 break; 542 case IOP13XX_INIT_ATU_ATUE: 543 bus = pci_bus_atue = pci_scan_root_bus(NULL, sys->busnr, 544 &iop13xx_atue_ops, 545 sys, &sys->resources); 546 break; 547 } 548 549 return bus; 550} 551 552/* This function is called from iop13xx_pci_init() after assigning valid 553 * values to iop13xx_atue_pmmr_offset. This is the location for common 554 * setup of ATUE for all IOP13XX implementations. 555 */ 556void __init iop13xx_atue_setup(void) 557{ 558 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE); 559 u32 reg_val; 560 561#ifdef CONFIG_PCI_MSI 562 /* BAR 0 (inbound msi window) */ 563 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); 564 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0); 565 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0); 566 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0); 567#endif 568 569 /* BAR 1 (1:1 mapping with Physical RAM) */ 570 /* Set limit and enable */ 571 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, 572 IOP13XX_ATUE_IALR1); 573 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1); 574 575 /* Set base at the top of the reserved address space */ 576 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 | 577 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1); 578 579 /* 1:1 mapping with physical ram 580 * (leave big endian byte swap disabled) 581 */ 582 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1); 583 __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1); 584 585 /* Outbound window 1 (PCIX/PCIE memory window) */ 586 /* 32 bit Address Space */ 587 __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1); 588 /* PA[35:32] */ 589 __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE | 590 (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32), 591 IOP13XX_ATUE_OUMBAR1); 592 593 /* Setup the I/O Bar 594 * A[35-16] in 31-12 595 */ 596 __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000), 597 IOP13XX_ATUE_OIOBAR); 598 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR); 599 600 /* clear startup errors */ 601 iop13xx_atue_pci_status(1); 602 603 /* OIOBAR function number 604 */ 605 reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR); 606 reg_val &= ~0x7; 607 reg_val |= func; 608 __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR); 609 610 /* OUMBAR function numbers 611 */ 612 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0); 613 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 614 IOP13XX_ATU_OUMBAR_FUNC_NUM); 615 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 616 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0); 617 618 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1); 619 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 620 IOP13XX_ATU_OUMBAR_FUNC_NUM); 621 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 622 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1); 623 624 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2); 625 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 626 IOP13XX_ATU_OUMBAR_FUNC_NUM); 627 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 628 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2); 629 630 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3); 631 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 632 IOP13XX_ATU_OUMBAR_FUNC_NUM); 633 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 634 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3); 635 636 /* Enable inbound and outbound cycles 637 */ 638 reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD); 639 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 640 PCI_COMMAND_PARITY | PCI_COMMAND_SERR; 641 __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD); 642 643 reg_val = __raw_readl(IOP13XX_ATUE_ATUCR); 644 reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN | 645 IOP13XX_ATUE_ATUCR_IVM; 646 __raw_writel(reg_val, IOP13XX_ATUE_ATUCR); 647} 648 649void __init iop13xx_atue_disable(void) 650{ 651 u32 reg_val; 652 653 __raw_writew(0x0, IOP13XX_ATUE_ATUCMD); 654 __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR); 655 656 /* wait for cycles to quiesce */ 657 while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY | 658 IOP13XX_ATUE_PCSR_IN_Q_BUSY | 659 IOP13XX_ATUE_PCSR_LLRB_BUSY)) 660 cpu_relax(); 661 662 /* BAR 0 ( Disabled ) */ 663 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0); 664 __raw_writel(0x0, IOP13XX_ATUE_IABAR0); 665 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0); 666 __raw_writel(0x0, IOP13XX_ATUE_IATVR0); 667 __raw_writel(0x0, IOP13XX_ATUE_IALR0); 668 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0); 669 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; 670 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0); 671 672 /* BAR 1 ( Disabled ) */ 673 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1); 674 __raw_writel(0x0, IOP13XX_ATUE_IABAR1); 675 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1); 676 __raw_writel(0x0, IOP13XX_ATUE_IATVR1); 677 __raw_writel(0x0, IOP13XX_ATUE_IALR1); 678 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1); 679 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; 680 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1); 681 682 /* BAR 2 ( Disabled ) */ 683 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2); 684 __raw_writel(0x0, IOP13XX_ATUE_IABAR2); 685 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2); 686 __raw_writel(0x0, IOP13XX_ATUE_IATVR2); 687 __raw_writel(0x0, IOP13XX_ATUE_IALR2); 688 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2); 689 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; 690 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2); 691 692 /* BAR 3 ( Disabled ) */ 693 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3); 694 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE; 695 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3); 696 697 /* Setup the I/O Bar 698 * A[35-16] in 31-12 699 */ 700 __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000, 701 IOP13XX_ATUE_OIOBAR); 702 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR); 703} 704 705/* This function is called from iop13xx_pci_init() after assigning valid 706 * values to iop13xx_atux_pmmr_offset. This is the location for common 707 * setup of ATUX for all IOP13XX implementations. 708 */ 709void __init iop13xx_atux_setup(void) 710{ 711 u32 reg_val; 712 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX); 713 714 /* Take PCI-X bus out of reset if bootloader hasn't already. 715 * According to spec, we should wait for 2^25 PCI clocks to meet 716 * the PCI timing parameter Trhfa (RST# high to first access). 717 * This is rarely necessary and often ignored. 718 */ 719 reg_val = __raw_readl(IOP13XX_ATUX_PCSR); 720 if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) { 721 int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7; 722 msec = 1000 / (8-msec); /* bits 100=133MHz, 111=>33MHz */ 723 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT, 724 IOP13XX_ATUX_PCSR); 725 atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec); 726 } 727 else 728 atux_trhfa_timeout = jiffies; 729 730#ifdef CONFIG_PCI_MSI 731 /* BAR 0 (inbound msi window) */ 732 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); 733 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0); 734 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0); 735 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0); 736#endif 737 738 /* BAR 1 (1:1 mapping with Physical RAM) */ 739 /* Set limit and enable */ 740 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, 741 IOP13XX_ATUX_IALR1); 742 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1); 743 744 /* Set base at the top of the reserved address space */ 745 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 | 746 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1); 747 748 /* 1:1 mapping with physical ram 749 * (leave big endian byte swap disabled) 750 */ 751 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1); 752 __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1); 753 754 /* Outbound window 1 (PCIX/PCIE memory window) */ 755 /* 32 bit Address Space */ 756 __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1); 757 /* PA[35:32] */ 758 __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE | 759 IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32, 760 IOP13XX_ATUX_OUMBAR1); 761 762 /* Setup the I/O Bar 763 * A[35-16] in 31-12 764 */ 765 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000, 766 IOP13XX_ATUX_OIOBAR); 767 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR); 768 769 /* clear startup errors */ 770 iop13xx_atux_pci_status(1); 771 772 /* OIOBAR function number 773 */ 774 reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR); 775 reg_val &= ~0x7; 776 reg_val |= func; 777 __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR); 778 779 /* OUMBAR function numbers 780 */ 781 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0); 782 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 783 IOP13XX_ATU_OUMBAR_FUNC_NUM); 784 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 785 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0); 786 787 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1); 788 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 789 IOP13XX_ATU_OUMBAR_FUNC_NUM); 790 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 791 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1); 792 793 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2); 794 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 795 IOP13XX_ATU_OUMBAR_FUNC_NUM); 796 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 797 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2); 798 799 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3); 800 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK << 801 IOP13XX_ATU_OUMBAR_FUNC_NUM); 802 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM; 803 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3); 804 805 /* Enable inbound and outbound cycles 806 */ 807 reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD); 808 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | 809 PCI_COMMAND_PARITY | PCI_COMMAND_SERR; 810 __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD); 811 812 reg_val = __raw_readl(IOP13XX_ATUX_ATUCR); 813 reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN; 814 __raw_writel(reg_val, IOP13XX_ATUX_ATUCR); 815} 816 817void __init iop13xx_atux_disable(void) 818{ 819 u32 reg_val; 820 821 __raw_writew(0x0, IOP13XX_ATUX_ATUCMD); 822 __raw_writel(0x0, IOP13XX_ATUX_ATUCR); 823 824 /* wait for cycles to quiesce */ 825 while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY | 826 IOP13XX_ATUX_PCSR_IN_Q_BUSY)) 827 cpu_relax(); 828 829 /* BAR 0 ( Disabled ) */ 830 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0); 831 __raw_writel(0x0, IOP13XX_ATUX_IABAR0); 832 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0); 833 __raw_writel(0x0, IOP13XX_ATUX_IATVR0); 834 __raw_writel(0x0, IOP13XX_ATUX_IALR0); 835 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0); 836 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; 837 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0); 838 839 /* BAR 1 ( Disabled ) */ 840 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1); 841 __raw_writel(0x0, IOP13XX_ATUX_IABAR1); 842 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1); 843 __raw_writel(0x0, IOP13XX_ATUX_IATVR1); 844 __raw_writel(0x0, IOP13XX_ATUX_IALR1); 845 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1); 846 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; 847 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1); 848 849 /* BAR 2 ( Disabled ) */ 850 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2); 851 __raw_writel(0x0, IOP13XX_ATUX_IABAR2); 852 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2); 853 __raw_writel(0x0, IOP13XX_ATUX_IATVR2); 854 __raw_writel(0x0, IOP13XX_ATUX_IALR2); 855 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2); 856 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; 857 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2); 858 859 /* BAR 3 ( Disabled ) */ 860 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3); 861 __raw_writel(0x0, IOP13XX_ATUX_IABAR3); 862 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3); 863 __raw_writel(0x0, IOP13XX_ATUX_IATVR3); 864 __raw_writel(0x0, IOP13XX_ATUX_IALR3); 865 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3); 866 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE; 867 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3); 868 869 /* Setup the I/O Bar 870 * A[35-16] in 31-12 871 */ 872 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000, 873 IOP13XX_ATUX_OIOBAR); 874 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR); 875} 876 877void __init iop13xx_set_atu_mmr_bases(void) 878{ 879 /* Based on ESSR0, determine the ATU X/E offsets */ 880 switch(__raw_readl(IOP13XX_ESSR0) & 881 (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) { 882 /* both asserted */ 883 case 0: 884 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET; 885 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET; 886 break; 887 /* IOP13XX_CONTROLLER_ONLY = deasserted 888 * IOP13XX_INTERFACE_SEL_PCIX = asserted 889 */ 890 case IOP13XX_CONTROLLER_ONLY: 891 iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET; 892 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET; 893 break; 894 /* IOP13XX_CONTROLLER_ONLY = asserted 895 * IOP13XX_INTERFACE_SEL_PCIX = deasserted 896 */ 897 case IOP13XX_INTERFACE_SEL_PCIX: 898 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET; 899 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET; 900 break; 901 /* both deasserted */ 902 case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX: 903 iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET; 904 iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET; 905 break; 906 default: 907 BUG(); 908 } 909} 910 911void __init iop13xx_atu_select(struct hw_pci *plat_pci) 912{ 913 int i; 914 915 /* set system defaults 916 * note: if "iop13xx_init_atu=" is specified this autodetect 917 * sequence will be bypassed 918 */ 919 if (init_atu == IOP13XX_INIT_ATU_DEFAULT) { 920 /* check for single/dual interface */ 921 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) { 922 /* ATUE must be present check the device id 923 * to see if ATUX is present. 924 */ 925 init_atu |= IOP13XX_INIT_ATU_ATUE; 926 switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) { 927 case 0x70: 928 case 0x80: 929 case 0xc0: 930 init_atu |= IOP13XX_INIT_ATU_ATUX; 931 break; 932 } 933 } else { 934 /* ATUX must be present check the device id 935 * to see if ATUE is present. 936 */ 937 init_atu |= IOP13XX_INIT_ATU_ATUX; 938 switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) { 939 case 0x70: 940 case 0x80: 941 case 0xc0: 942 init_atu |= IOP13XX_INIT_ATU_ATUE; 943 break; 944 } 945 } 946 947 /* check central resource and root complex capability */ 948 if (init_atu & IOP13XX_INIT_ATU_ATUX) 949 if (!(__raw_readl(IOP13XX_ATUX_PCSR) & 950 IOP13XX_ATUX_PCSR_CENTRAL_RES)) 951 init_atu &= ~IOP13XX_INIT_ATU_ATUX; 952 953 if (init_atu & IOP13XX_INIT_ATU_ATUE) 954 if (__raw_readl(IOP13XX_ATUE_PCSR) & 955 IOP13XX_ATUE_PCSR_END_POINT) 956 init_atu &= ~IOP13XX_INIT_ATU_ATUE; 957 } 958 959 for (i = 0; i < 2; i++) { 960 if((init_atu & (1 << i)) == (1 << i)) 961 plat_pci->nr_controllers++; 962 } 963} 964 965void __init iop13xx_pci_init(void) 966{ 967 /* clear pre-existing south bridge errors */ 968 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); 969 970 /* Setup the Min Address for PCI memory... */ 971 pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; 972 973 /* if Linux is given control of an ATU 974 * clear out its prior configuration, 975 * otherwise do not touch the registers 976 */ 977 if (init_atu & IOP13XX_INIT_ATU_ATUE) { 978 iop13xx_atue_disable(); 979 iop13xx_atue_setup(); 980 } 981 982 if (init_atu & IOP13XX_INIT_ATU_ATUX) { 983 iop13xx_atux_disable(); 984 iop13xx_atux_setup(); 985 } 986 987 hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0, 988 "imprecise external abort"); 989} 990 991/* initialize the pci memory space. handle any combination of 992 * atue and atux enabled/disabled 993 */ 994int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) 995{ 996 struct resource *res; 997 int which_atu; 998 u32 pcixsr, pcsr; 999 1000 if (nr > 1) 1001 return 0; 1002 1003 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1004 if (!res) 1005 panic("PCI: unable to alloc resources"); 1006 1007 1008 /* 'nr' assumptions: 1009 * ATUX is always 0 1010 * ATUE is 1 when ATUX is also enabled 1011 * ATUE is 0 when ATUX is disabled 1012 */ 1013 switch(init_atu) { 1014 case IOP13XX_INIT_ATU_ATUX: 1015 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX; 1016 break; 1017 case IOP13XX_INIT_ATU_ATUE: 1018 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE; 1019 break; 1020 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE): 1021 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX; 1022 break; 1023 default: 1024 which_atu = 0; 1025 } 1026 1027 if (!which_atu) { 1028 kfree(res); 1029 return 0; 1030 } 1031 1032 switch(which_atu) { 1033 case IOP13XX_INIT_ATU_ATUX: 1034 pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR); 1035 pcixsr &= ~0xffff; 1036 pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM | 1037 0 << IOP13XX_ATUX_PCIXSR_DEV_NUM | 1038 iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX) 1039 << IOP13XX_ATUX_PCIXSR_FUNC_NUM; 1040 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); 1041 1042 pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA); 1043 1044 res->start = IOP13XX_PCIX_LOWER_MEM_RA; 1045 res->end = IOP13XX_PCIX_UPPER_MEM_RA; 1046 res->name = "IQ81340 ATUX PCI Memory Space"; 1047 res->flags = IORESOURCE_MEM; 1048 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; 1049 break; 1050 case IOP13XX_INIT_ATU_ATUE: 1051 /* Note: the function number field in the PCSR is ro */ 1052 pcsr = __raw_readl(IOP13XX_ATUE_PCSR); 1053 pcsr &= ~(0xfff8 << 16); 1054 pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM | 1055 0 << IOP13XX_ATUE_PCSR_DEV_NUM; 1056 1057 __raw_writel(pcsr, IOP13XX_ATUE_PCSR); 1058 1059 pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA); 1060 1061 res->start = IOP13XX_PCIE_LOWER_MEM_RA; 1062 res->end = IOP13XX_PCIE_UPPER_MEM_RA; 1063 res->name = "IQ81340 ATUE PCI Memory Space"; 1064 res->flags = IORESOURCE_MEM; 1065 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; 1066 sys->map_irq = iop13xx_pcie_map_irq; 1067 break; 1068 default: 1069 kfree(res); 1070 return 0; 1071 } 1072 1073 request_resource(&iomem_resource, res); 1074 1075 pci_add_resource_offset(&sys->resources, res, sys->mem_offset); 1076 1077 return 1; 1078} 1079 1080u16 iop13xx_dev_id(void) 1081{ 1082 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) 1083 return __raw_readw(IOP13XX_ATUE_DID); 1084 else 1085 return __raw_readw(IOP13XX_ATUX_DID); 1086} 1087 1088static int __init iop13xx_init_atu_setup(char *str) 1089{ 1090 init_atu = IOP13XX_INIT_ATU_NONE; 1091 if (str) { 1092 while (*str != '\0') { 1093 switch (*str) { 1094 case 'x': 1095 case 'X': 1096 init_atu |= IOP13XX_INIT_ATU_ATUX; 1097 init_atu &= ~IOP13XX_INIT_ATU_NONE; 1098 break; 1099 case 'e': 1100 case 'E': 1101 init_atu |= IOP13XX_INIT_ATU_ATUE; 1102 init_atu &= ~IOP13XX_INIT_ATU_NONE; 1103 break; 1104 case ',': 1105 case '=': 1106 break; 1107 default: 1108 PRINTK("\"iop13xx_init_atu\" malformed at " 1109 "character: \'%c\'", *str); 1110 *(str + 1) = '\0'; 1111 init_atu = IOP13XX_INIT_ATU_DEFAULT; 1112 } 1113 str++; 1114 } 1115 } 1116 return 1; 1117} 1118 1119__setup("iop13xx_init_atu", iop13xx_init_atu_setup); 1120