1/*
2 * arch/arm/mach-ep93xx/dma.c
3 *
4 * Platform support code for the EP93xx dmaengine driver.
5 *
6 * Copyright (C) 2011 Mika Westerberg
7 *
8 * This work is based on the original dma-m2p implementation with
9 * following copyrights:
10 *
11 *   Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
12 *   Copyright (C) 2006 Applied Data Systems
13 *   Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or (at
18 * your option) any later version.
19 */
20
21#include <linux/dmaengine.h>
22#include <linux/dma-mapping.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/kernel.h>
26#include <linux/platform_device.h>
27
28#include <linux/platform_data/dma-ep93xx.h>
29#include <mach/hardware.h>
30
31#include "soc.h"
32
33#define DMA_CHANNEL(_name, _base, _irq) \
34	{ .name = (_name), .base = (_base), .irq = (_irq) }
35
36/*
37 * DMA M2P channels.
38 *
39 * On the EP93xx chip the following peripherals my be allocated to the 10
40 * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
41 *
42 *	I2S	contains 3 Tx and 3 Rx DMA Channels
43 *	AAC	contains 3 Tx and 3 Rx DMA Channels
44 *	UART1	contains 1 Tx and 1 Rx DMA Channels
45 *	UART2	contains 1 Tx and 1 Rx DMA Channels
46 *	UART3	contains 1 Tx and 1 Rx DMA Channels
47 *	IrDA	contains 1 Tx and 1 Rx DMA Channels
48 *
49 * Registers are mapped statically in ep93xx_map_io().
50 */
51static struct ep93xx_dma_chan_data ep93xx_dma_m2p_channels[] = {
52	DMA_CHANNEL("m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0),
53	DMA_CHANNEL("m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1),
54	DMA_CHANNEL("m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2),
55	DMA_CHANNEL("m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3),
56	DMA_CHANNEL("m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4),
57	DMA_CHANNEL("m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5),
58	DMA_CHANNEL("m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6),
59	DMA_CHANNEL("m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7),
60	DMA_CHANNEL("m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8),
61	DMA_CHANNEL("m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9),
62};
63
64static struct ep93xx_dma_platform_data ep93xx_dma_m2p_data = {
65	.channels		= ep93xx_dma_m2p_channels,
66	.num_channels		= ARRAY_SIZE(ep93xx_dma_m2p_channels),
67};
68
69static u64 ep93xx_dma_m2p_mask = DMA_BIT_MASK(32);
70
71static struct platform_device ep93xx_dma_m2p_device = {
72	.name			= "ep93xx-dma-m2p",
73	.id			= -1,
74	.dev			= {
75		.platform_data		= &ep93xx_dma_m2p_data,
76		.dma_mask		= &ep93xx_dma_m2p_mask,
77		.coherent_dma_mask	= DMA_BIT_MASK(32),
78	},
79};
80
81/*
82 * DMA M2M channels.
83 *
84 * There are 2 M2M channels which support memcpy/memset and in addition simple
85 * hardware requests from/to SSP and IDE. We do not implement an external
86 * hardware requests.
87 *
88 * Registers are mapped statically in ep93xx_map_io().
89 */
90static struct ep93xx_dma_chan_data ep93xx_dma_m2m_channels[] = {
91	DMA_CHANNEL("m2m0", EP93XX_DMA_BASE + 0x0100, IRQ_EP93XX_DMAM2M0),
92	DMA_CHANNEL("m2m1", EP93XX_DMA_BASE + 0x0140, IRQ_EP93XX_DMAM2M1),
93};
94
95static struct ep93xx_dma_platform_data ep93xx_dma_m2m_data = {
96	.channels		= ep93xx_dma_m2m_channels,
97	.num_channels		= ARRAY_SIZE(ep93xx_dma_m2m_channels),
98};
99
100static u64 ep93xx_dma_m2m_mask = DMA_BIT_MASK(32);
101
102static struct platform_device ep93xx_dma_m2m_device = {
103	.name			= "ep93xx-dma-m2m",
104	.id			= -1,
105	.dev			= {
106		.platform_data		= &ep93xx_dma_m2m_data,
107		.dma_mask		= &ep93xx_dma_m2m_mask,
108		.coherent_dma_mask	= DMA_BIT_MASK(32),
109	},
110};
111
112static int __init ep93xx_dma_init(void)
113{
114	platform_device_register(&ep93xx_dma_m2p_device);
115	platform_device_register(&ep93xx_dma_m2m_device);
116	return 0;
117}
118arch_initcall(ep93xx_dma_init);
119