1/*
2 * arch/arm/mach-dove/include/mach/dove.h
3 *
4 * Generic definitions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2.  This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_DOVE_H
12#define __ASM_ARCH_DOVE_H
13
14/*
15 * Marvell Dove address maps.
16 *
17 * phys		virt		size
18 * c8000000	fdb00000	1M	Cryptographic SRAM
19 * e0000000	@runtime	128M	PCIe-0 Memory space
20 * e8000000	@runtime	128M	PCIe-1 Memory space
21 * f1000000	fde00000	8M	on-chip south-bridge registers
22 * f1800000	fe600000	8M	on-chip north-bridge registers
23 * f2000000	fee00000	1M	PCIe-0 I/O space
24 * f2100000	fef00000	1M	PCIe-1 I/O space
25 */
26
27#define DOVE_CESA_PHYS_BASE		0xc8000000
28#define DOVE_CESA_VIRT_BASE		IOMEM(0xfdb00000)
29#define DOVE_CESA_SIZE			SZ_1M
30
31#define DOVE_PCIE0_MEM_PHYS_BASE	0xe0000000
32#define DOVE_PCIE0_MEM_SIZE		SZ_128M
33
34#define DOVE_PCIE1_MEM_PHYS_BASE	0xe8000000
35#define DOVE_PCIE1_MEM_SIZE		SZ_128M
36
37#define DOVE_BOOTROM_PHYS_BASE		0xf8000000
38#define DOVE_BOOTROM_SIZE		SZ_128M
39
40#define DOVE_SCRATCHPAD_PHYS_BASE	0xf0000000
41#define DOVE_SCRATCHPAD_VIRT_BASE	IOMEM(0xfdd00000)
42#define DOVE_SCRATCHPAD_SIZE		SZ_1M
43
44#define DOVE_SB_REGS_PHYS_BASE		0xf1000000
45#define DOVE_SB_REGS_VIRT_BASE		IOMEM(0xfde00000)
46#define DOVE_SB_REGS_SIZE		SZ_8M
47
48#define DOVE_NB_REGS_PHYS_BASE		0xf1800000
49#define DOVE_NB_REGS_VIRT_BASE		IOMEM(0xfe600000)
50#define DOVE_NB_REGS_SIZE		SZ_8M
51
52#define DOVE_PCIE0_IO_PHYS_BASE		0xf2000000
53#define DOVE_PCIE0_IO_BUS_BASE		0x00000000
54#define DOVE_PCIE0_IO_SIZE		SZ_64K
55
56#define DOVE_PCIE1_IO_PHYS_BASE		0xf2100000
57#define DOVE_PCIE1_IO_BUS_BASE		0x00010000
58#define DOVE_PCIE1_IO_SIZE		SZ_64K
59
60/*
61 * Dove Core Registers Map
62 */
63
64/* SPI, I2C, UART */
65#define DOVE_I2C_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x11000)
66#define DOVE_UART0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12000)
67#define DOVE_UART0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12000)
68#define DOVE_UART1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12100)
69#define DOVE_UART1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12100)
70#define DOVE_UART2_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12200)
71#define DOVE_UART2_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12200)
72#define DOVE_UART3_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12300)
73#define DOVE_UART3_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12300)
74#define DOVE_SPI0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x10600)
75#define DOVE_SPI1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x14600)
76
77/* North-South Bridge */
78#define BRIDGE_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x20000)
79#define BRIDGE_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x20000)
80#define  BRIDGE_WINS_BASE       (BRIDGE_PHYS_BASE)
81#define  BRIDGE_WINS_SZ         (0x80)
82
83/* Cryptographic Engine */
84#define DOVE_CRYPT_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x30000)
85
86/* PCIe 0 */
87#define DOVE_PCIE0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x40000)
88
89/* USB */
90#define DOVE_USB0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x50000)
91#define DOVE_USB1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x51000)
92
93/* XOR 0 Engine */
94#define DOVE_XOR0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60800)
95#define DOVE_XOR0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60800)
96#define DOVE_XOR0_HIGH_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60A00)
97#define DOVE_XOR0_HIGH_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60A00)
98
99/* XOR 1 Engine */
100#define DOVE_XOR1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60900)
101#define DOVE_XOR1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60900)
102#define DOVE_XOR1_HIGH_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60B00)
103#define DOVE_XOR1_HIGH_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60B00)
104
105/* Gigabit Ethernet */
106#define DOVE_GE00_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x70000)
107
108/* PCIe 1 */
109#define DOVE_PCIE1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x80000)
110
111/* CAFE */
112#define DOVE_SDIO0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x92000)
113#define DOVE_SDIO1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x90000)
114#define DOVE_CAM_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x94000)
115#define DOVE_CAFE_WIN_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x98000)
116
117/* SATA */
118#define DOVE_SATA_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xa0000)
119
120/* I2S/SPDIF */
121#define DOVE_AUD0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xb0000)
122#define DOVE_AUD1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xb4000)
123
124/* NAND Flash Controller */
125#define DOVE_NFC_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xc0000)
126
127/* MPP, GPIO, Reset Sampling */
128#define DOVE_MPP_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0200)
129#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
130#define DOVE_RESET_SAMPLE_LO	(DOVE_MPP_VIRT_BASE + 0x014)
131#define DOVE_RESET_SAMPLE_HI	(DOVE_MPP_VIRT_BASE + 0x018)
132#define DOVE_GPIO_LO_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0400)
133#define DOVE_GPIO_HI_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0420)
134#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
135#define DOVE_MPP_GENERAL_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xe803c)
136#define  DOVE_AU1_SPDIFO_GPIO_EN	(1 << 1)
137#define  DOVE_NAND_GPIO_EN		(1 << 0)
138#define DOVE_MPP_CTRL4_VIRT_BASE	(DOVE_GPIO_LO_VIRT_BASE + 0x40)
139#define  DOVE_SPI_GPIO_SEL		(1 << 5)
140#define  DOVE_UART1_GPIO_SEL		(1 << 4)
141#define  DOVE_AU1_GPIO_SEL		(1 << 3)
142#define  DOVE_CAM_GPIO_SEL		(1 << 2)
143#define  DOVE_SD1_GPIO_SEL		(1 << 1)
144#define  DOVE_SD0_GPIO_SEL		(1 << 0)
145
146/* Power Management */
147#define DOVE_PMU_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0000)
148#define DOVE_PMU_SIG_CTRL	(DOVE_PMU_VIRT_BASE + 0x802c)
149
150/* Real Time Clock */
151#define DOVE_RTC_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xd8500)
152
153/* AC97 */
154#define DOVE_AC97_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xe0000)
155#define DOVE_AC97_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xe0000)
156
157/* Peripheral DMA */
158#define DOVE_PDMA_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xe4000)
159#define DOVE_PDMA_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xe4000)
160
161#define DOVE_GLOBAL_CONFIG_1	(DOVE_SB_REGS_VIRT_BASE + 0xe802C)
162#define  DOVE_TWSI_ENABLE_OPTION1	(1 << 7)
163#define DOVE_GLOBAL_CONFIG_2	(DOVE_SB_REGS_VIRT_BASE + 0xe8030)
164#define  DOVE_TWSI_ENABLE_OPTION2	(1 << 20)
165#define  DOVE_TWSI_ENABLE_OPTION3	(1 << 21)
166#define  DOVE_TWSI_OPTION3_GPIO		(1 << 22)
167#define DOVE_SSP_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xec000)
168#define DOVE_SSP_CTRL_STATUS_1	(DOVE_SB_REGS_VIRT_BASE + 0xe8034)
169#define  DOVE_SSP_ON_AU1		(1 << 0)
170#define  DOVE_SSP_CLOCK_ENABLE		(1 << 1)
171#define  DOVE_SSP_BPB_CLOCK_SRC_SSP	(1 << 11)
172/* Memory Controller */
173#define DOVE_MC_PHYS_BASE       (DOVE_NB_REGS_PHYS_BASE + 0x00000)
174#define  DOVE_MC_WINS_BASE      (DOVE_MC_PHYS_BASE + 0x100)
175#define  DOVE_MC_WINS_SZ        (0x8)
176#define DOVE_MC_VIRT_BASE	(DOVE_NB_REGS_VIRT_BASE + 0x00000)
177
178/* LCD Controller */
179#define DOVE_LCD_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x10000)
180#define DOVE_LCD1_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x20000)
181#define DOVE_LCD2_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x10000)
182#define DOVE_LCD_DCON_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x30000)
183
184/* Graphic Engine */
185#define DOVE_GPU_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x40000)
186
187/* Video Engine */
188#define DOVE_VPU_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x400000)
189
190#endif
191