1/*
2 * DA8XX/OMAP L1XX platform device data
3 *
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 *	Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/dma-contiguous.h>
16#include <linux/serial_8250.h>
17#include <linux/ahci_platform.h>
18#include <linux/clk.h>
19#include <linux/reboot.h>
20
21#include <mach/cputype.h>
22#include <mach/common.h>
23#include <mach/time.h>
24#include <mach/da8xx.h>
25#include <mach/cpuidle.h>
26#include <mach/sram.h>
27
28#include "clock.h"
29#include "asp.h"
30
31#define DA8XX_TPCC_BASE			0x01c00000
32#define DA8XX_TPTC0_BASE		0x01c08000
33#define DA8XX_TPTC1_BASE		0x01c08400
34#define DA8XX_WDOG_BASE			0x01c21000 /* DA8XX_TIMER64P1_BASE */
35#define DA8XX_I2C0_BASE			0x01c22000
36#define DA8XX_RTC_BASE			0x01c23000
37#define DA8XX_PRUSS_MEM_BASE		0x01c30000
38#define DA8XX_MMCSD0_BASE		0x01c40000
39#define DA8XX_SPI0_BASE			0x01c41000
40#define DA830_SPI1_BASE			0x01e12000
41#define DA8XX_LCD_CNTRL_BASE		0x01e13000
42#define DA850_SATA_BASE			0x01e18000
43#define DA850_MMCSD1_BASE		0x01e1b000
44#define DA8XX_EMAC_CPPI_PORT_BASE	0x01e20000
45#define DA8XX_EMAC_CPGMACSS_BASE	0x01e22000
46#define DA8XX_EMAC_CPGMAC_BASE		0x01e23000
47#define DA8XX_EMAC_MDIO_BASE		0x01e24000
48#define DA8XX_I2C1_BASE			0x01e28000
49#define DA850_TPCC1_BASE		0x01e30000
50#define DA850_TPTC2_BASE		0x01e38000
51#define DA850_SPI1_BASE			0x01f0e000
52#define DA8XX_DDR2_CTL_BASE		0xb0000000
53
54#define DA8XX_EMAC_CTRL_REG_OFFSET	0x3000
55#define DA8XX_EMAC_MOD_REG_OFFSET	0x2000
56#define DA8XX_EMAC_RAM_OFFSET		0x0000
57#define DA8XX_EMAC_CTRL_RAM_SIZE	SZ_8K
58
59#define DA8XX_DMA_SPI0_RX	EDMA_CTLR_CHAN(0, 14)
60#define DA8XX_DMA_SPI0_TX	EDMA_CTLR_CHAN(0, 15)
61#define DA8XX_DMA_MMCSD0_RX	EDMA_CTLR_CHAN(0, 16)
62#define DA8XX_DMA_MMCSD0_TX	EDMA_CTLR_CHAN(0, 17)
63#define DA8XX_DMA_SPI1_RX	EDMA_CTLR_CHAN(0, 18)
64#define DA8XX_DMA_SPI1_TX	EDMA_CTLR_CHAN(0, 19)
65#define DA850_DMA_MMCSD1_RX	EDMA_CTLR_CHAN(1, 28)
66#define DA850_DMA_MMCSD1_TX	EDMA_CTLR_CHAN(1, 29)
67
68void __iomem *da8xx_syscfg0_base;
69void __iomem *da8xx_syscfg1_base;
70
71static struct plat_serial8250_port da8xx_serial0_pdata[] = {
72	{
73		.mapbase	= DA8XX_UART0_BASE,
74		.irq		= IRQ_DA8XX_UARTINT0,
75		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
76					UPF_IOREMAP,
77		.iotype		= UPIO_MEM,
78		.regshift	= 2,
79	},
80	{
81		.flags	= 0,
82	}
83};
84static struct plat_serial8250_port da8xx_serial1_pdata[] = {
85	{
86		.mapbase	= DA8XX_UART1_BASE,
87		.irq		= IRQ_DA8XX_UARTINT1,
88		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
89					UPF_IOREMAP,
90		.iotype		= UPIO_MEM,
91		.regshift	= 2,
92	},
93	{
94		.flags	= 0,
95	}
96};
97static struct plat_serial8250_port da8xx_serial2_pdata[] = {
98	{
99		.mapbase	= DA8XX_UART2_BASE,
100		.irq		= IRQ_DA8XX_UARTINT2,
101		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
102					UPF_IOREMAP,
103		.iotype		= UPIO_MEM,
104		.regshift	= 2,
105	},
106	{
107		.flags	= 0,
108	}
109};
110
111struct platform_device da8xx_serial_device[] = {
112	{
113		.name	= "serial8250",
114		.id	= PLAT8250_DEV_PLATFORM,
115		.dev	= {
116			.platform_data	= da8xx_serial0_pdata,
117		}
118	},
119	{
120		.name	= "serial8250",
121		.id	= PLAT8250_DEV_PLATFORM1,
122		.dev	= {
123			.platform_data	= da8xx_serial1_pdata,
124		}
125	},
126	{
127		.name	= "serial8250",
128		.id	= PLAT8250_DEV_PLATFORM2,
129		.dev	= {
130			.platform_data	= da8xx_serial2_pdata,
131		}
132	},
133	{
134	}
135};
136
137static s8 da8xx_queue_priority_mapping[][2] = {
138	/* {event queue no, Priority} */
139	{0, 3},
140	{1, 7},
141	{-1, -1}
142};
143
144static s8 da850_queue_priority_mapping[][2] = {
145	/* {event queue no, Priority} */
146	{0, 3},
147	{-1, -1}
148};
149
150static struct edma_soc_info da8xx_edma0_pdata = {
151	.queue_priority_mapping	= da8xx_queue_priority_mapping,
152	.default_queue		= EVENTQ_1,
153};
154
155static struct edma_soc_info da850_edma1_pdata = {
156	.queue_priority_mapping	= da850_queue_priority_mapping,
157	.default_queue		= EVENTQ_0,
158};
159
160static struct resource da8xx_edma0_resources[] = {
161	{
162		.name	= "edma3_cc",
163		.start	= DA8XX_TPCC_BASE,
164		.end	= DA8XX_TPCC_BASE + SZ_32K - 1,
165		.flags	= IORESOURCE_MEM,
166	},
167	{
168		.name	= "edma3_tc0",
169		.start	= DA8XX_TPTC0_BASE,
170		.end	= DA8XX_TPTC0_BASE + SZ_1K - 1,
171		.flags	= IORESOURCE_MEM,
172	},
173	{
174		.name	= "edma3_tc1",
175		.start	= DA8XX_TPTC1_BASE,
176		.end	= DA8XX_TPTC1_BASE + SZ_1K - 1,
177		.flags	= IORESOURCE_MEM,
178	},
179	{
180		.name	= "edma3_ccint",
181		.start	= IRQ_DA8XX_CCINT0,
182		.flags	= IORESOURCE_IRQ,
183	},
184	{
185		.name	= "edma3_ccerrint",
186		.start	= IRQ_DA8XX_CCERRINT,
187		.flags	= IORESOURCE_IRQ,
188	},
189};
190
191static struct resource da850_edma1_resources[] = {
192	{
193		.name	= "edma3_cc",
194		.start	= DA850_TPCC1_BASE,
195		.end	= DA850_TPCC1_BASE + SZ_32K - 1,
196		.flags	= IORESOURCE_MEM,
197	},
198	{
199		.name	= "edma3_tc0",
200		.start	= DA850_TPTC2_BASE,
201		.end	= DA850_TPTC2_BASE + SZ_1K - 1,
202		.flags	= IORESOURCE_MEM,
203	},
204	{
205		.name	= "edma3_ccint",
206		.start	= IRQ_DA850_CCINT1,
207		.flags	= IORESOURCE_IRQ,
208	},
209	{
210		.name	= "edma3_ccerrint",
211		.start	= IRQ_DA850_CCERRINT1,
212		.flags	= IORESOURCE_IRQ,
213	},
214};
215
216static const struct platform_device_info da8xx_edma0_device __initconst = {
217	.name		= "edma",
218	.id		= 0,
219	.dma_mask	= DMA_BIT_MASK(32),
220	.res		= da8xx_edma0_resources,
221	.num_res	= ARRAY_SIZE(da8xx_edma0_resources),
222	.data		= &da8xx_edma0_pdata,
223	.size_data	= sizeof(da8xx_edma0_pdata),
224};
225
226static const struct platform_device_info da850_edma1_device __initconst = {
227	.name		= "edma",
228	.id		= 1,
229	.dma_mask	= DMA_BIT_MASK(32),
230	.res		= da850_edma1_resources,
231	.num_res	= ARRAY_SIZE(da850_edma1_resources),
232	.data		= &da850_edma1_pdata,
233	.size_data	= sizeof(da850_edma1_pdata),
234};
235
236int __init da830_register_edma(struct edma_rsv_info *rsv)
237{
238	struct platform_device *edma_pdev;
239
240	da8xx_edma0_pdata.rsv = rsv;
241
242	edma_pdev = platform_device_register_full(&da8xx_edma0_device);
243	return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
244}
245
246int __init da850_register_edma(struct edma_rsv_info *rsv[2])
247{
248	struct platform_device *edma_pdev;
249
250	if (rsv) {
251		da8xx_edma0_pdata.rsv = rsv[0];
252		da850_edma1_pdata.rsv = rsv[1];
253	}
254
255	edma_pdev = platform_device_register_full(&da8xx_edma0_device);
256	if (IS_ERR(edma_pdev)) {
257		pr_warn("%s: Failed to register eDMA0\n", __func__);
258		return PTR_ERR(edma_pdev);
259	}
260	edma_pdev = platform_device_register_full(&da850_edma1_device);
261	return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
262}
263
264static struct resource da8xx_i2c_resources0[] = {
265	{
266		.start	= DA8XX_I2C0_BASE,
267		.end	= DA8XX_I2C0_BASE + SZ_4K - 1,
268		.flags	= IORESOURCE_MEM,
269	},
270	{
271		.start	= IRQ_DA8XX_I2CINT0,
272		.end	= IRQ_DA8XX_I2CINT0,
273		.flags	= IORESOURCE_IRQ,
274	},
275};
276
277static struct platform_device da8xx_i2c_device0 = {
278	.name		= "i2c_davinci",
279	.id		= 1,
280	.num_resources	= ARRAY_SIZE(da8xx_i2c_resources0),
281	.resource	= da8xx_i2c_resources0,
282};
283
284static struct resource da8xx_i2c_resources1[] = {
285	{
286		.start	= DA8XX_I2C1_BASE,
287		.end	= DA8XX_I2C1_BASE + SZ_4K - 1,
288		.flags	= IORESOURCE_MEM,
289	},
290	{
291		.start	= IRQ_DA8XX_I2CINT1,
292		.end	= IRQ_DA8XX_I2CINT1,
293		.flags	= IORESOURCE_IRQ,
294	},
295};
296
297static struct platform_device da8xx_i2c_device1 = {
298	.name		= "i2c_davinci",
299	.id		= 2,
300	.num_resources	= ARRAY_SIZE(da8xx_i2c_resources1),
301	.resource	= da8xx_i2c_resources1,
302};
303
304int __init da8xx_register_i2c(int instance,
305		struct davinci_i2c_platform_data *pdata)
306{
307	struct platform_device *pdev;
308
309	if (instance == 0)
310		pdev = &da8xx_i2c_device0;
311	else if (instance == 1)
312		pdev = &da8xx_i2c_device1;
313	else
314		return -EINVAL;
315
316	pdev->dev.platform_data = pdata;
317	return platform_device_register(pdev);
318}
319
320static struct resource da8xx_watchdog_resources[] = {
321	{
322		.start	= DA8XX_WDOG_BASE,
323		.end	= DA8XX_WDOG_BASE + SZ_4K - 1,
324		.flags	= IORESOURCE_MEM,
325	},
326};
327
328static struct platform_device da8xx_wdt_device = {
329	.name		= "davinci-wdt",
330	.id		= -1,
331	.num_resources	= ARRAY_SIZE(da8xx_watchdog_resources),
332	.resource	= da8xx_watchdog_resources,
333};
334
335void da8xx_restart(enum reboot_mode mode, const char *cmd)
336{
337	struct device *dev;
338
339	dev = bus_find_device_by_name(&platform_bus_type, NULL, "davinci-wdt");
340	if (!dev) {
341		pr_err("%s: failed to find watchdog device\n", __func__);
342		return;
343	}
344
345	davinci_watchdog_reset(to_platform_device(dev));
346}
347
348int __init da8xx_register_watchdog(void)
349{
350	return platform_device_register(&da8xx_wdt_device);
351}
352
353static struct resource da8xx_emac_resources[] = {
354	{
355		.start	= DA8XX_EMAC_CPPI_PORT_BASE,
356		.end	= DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
357		.flags	= IORESOURCE_MEM,
358	},
359	{
360		.start	= IRQ_DA8XX_C0_RX_THRESH_PULSE,
361		.end	= IRQ_DA8XX_C0_RX_THRESH_PULSE,
362		.flags	= IORESOURCE_IRQ,
363	},
364	{
365		.start	= IRQ_DA8XX_C0_RX_PULSE,
366		.end	= IRQ_DA8XX_C0_RX_PULSE,
367		.flags	= IORESOURCE_IRQ,
368	},
369	{
370		.start	= IRQ_DA8XX_C0_TX_PULSE,
371		.end	= IRQ_DA8XX_C0_TX_PULSE,
372		.flags	= IORESOURCE_IRQ,
373	},
374	{
375		.start	= IRQ_DA8XX_C0_MISC_PULSE,
376		.end	= IRQ_DA8XX_C0_MISC_PULSE,
377		.flags	= IORESOURCE_IRQ,
378	},
379};
380
381struct emac_platform_data da8xx_emac_pdata = {
382	.ctrl_reg_offset	= DA8XX_EMAC_CTRL_REG_OFFSET,
383	.ctrl_mod_reg_offset	= DA8XX_EMAC_MOD_REG_OFFSET,
384	.ctrl_ram_offset	= DA8XX_EMAC_RAM_OFFSET,
385	.ctrl_ram_size		= DA8XX_EMAC_CTRL_RAM_SIZE,
386	.version		= EMAC_VERSION_2,
387};
388
389static struct platform_device da8xx_emac_device = {
390	.name		= "davinci_emac",
391	.id		= 1,
392	.dev = {
393		.platform_data	= &da8xx_emac_pdata,
394	},
395	.num_resources	= ARRAY_SIZE(da8xx_emac_resources),
396	.resource	= da8xx_emac_resources,
397};
398
399static struct resource da8xx_mdio_resources[] = {
400	{
401		.start	= DA8XX_EMAC_MDIO_BASE,
402		.end	= DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
403		.flags	= IORESOURCE_MEM,
404	},
405};
406
407static struct platform_device da8xx_mdio_device = {
408	.name		= "davinci_mdio",
409	.id		= 0,
410	.num_resources	= ARRAY_SIZE(da8xx_mdio_resources),
411	.resource	= da8xx_mdio_resources,
412};
413
414int __init da8xx_register_emac(void)
415{
416	int ret;
417
418	ret = platform_device_register(&da8xx_mdio_device);
419	if (ret < 0)
420		return ret;
421
422	return platform_device_register(&da8xx_emac_device);
423}
424
425static struct resource da830_mcasp1_resources[] = {
426	{
427		.name	= "mpu",
428		.start	= DAVINCI_DA830_MCASP1_REG_BASE,
429		.end	= DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
430		.flags	= IORESOURCE_MEM,
431	},
432	/* TX event */
433	{
434		.name	= "tx",
435		.start	= DAVINCI_DA830_DMA_MCASP1_AXEVT,
436		.end	= DAVINCI_DA830_DMA_MCASP1_AXEVT,
437		.flags	= IORESOURCE_DMA,
438	},
439	/* RX event */
440	{
441		.name	= "rx",
442		.start	= DAVINCI_DA830_DMA_MCASP1_AREVT,
443		.end	= DAVINCI_DA830_DMA_MCASP1_AREVT,
444		.flags	= IORESOURCE_DMA,
445	},
446	{
447		.name	= "common",
448		.start	= IRQ_DA8XX_MCASPINT,
449		.flags	= IORESOURCE_IRQ,
450	},
451};
452
453static struct platform_device da830_mcasp1_device = {
454	.name		= "davinci-mcasp",
455	.id		= 1,
456	.num_resources	= ARRAY_SIZE(da830_mcasp1_resources),
457	.resource	= da830_mcasp1_resources,
458};
459
460static struct resource da830_mcasp2_resources[] = {
461	{
462		.name	= "mpu",
463		.start	= DAVINCI_DA830_MCASP2_REG_BASE,
464		.end	= DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
465		.flags	= IORESOURCE_MEM,
466	},
467	/* TX event */
468	{
469		.name	= "tx",
470		.start	= DAVINCI_DA830_DMA_MCASP2_AXEVT,
471		.end	= DAVINCI_DA830_DMA_MCASP2_AXEVT,
472		.flags	= IORESOURCE_DMA,
473	},
474	/* RX event */
475	{
476		.name	= "rx",
477		.start	= DAVINCI_DA830_DMA_MCASP2_AREVT,
478		.end	= DAVINCI_DA830_DMA_MCASP2_AREVT,
479		.flags	= IORESOURCE_DMA,
480	},
481	{
482		.name	= "common",
483		.start	= IRQ_DA8XX_MCASPINT,
484		.flags	= IORESOURCE_IRQ,
485	},
486};
487
488static struct platform_device da830_mcasp2_device = {
489	.name		= "davinci-mcasp",
490	.id		= 2,
491	.num_resources	= ARRAY_SIZE(da830_mcasp2_resources),
492	.resource	= da830_mcasp2_resources,
493};
494
495static struct resource da850_mcasp_resources[] = {
496	{
497		.name	= "mpu",
498		.start	= DAVINCI_DA8XX_MCASP0_REG_BASE,
499		.end	= DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
500		.flags	= IORESOURCE_MEM,
501	},
502	/* TX event */
503	{
504		.name	= "tx",
505		.start	= DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
506		.end	= DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
507		.flags	= IORESOURCE_DMA,
508	},
509	/* RX event */
510	{
511		.name	= "rx",
512		.start	= DAVINCI_DA8XX_DMA_MCASP0_AREVT,
513		.end	= DAVINCI_DA8XX_DMA_MCASP0_AREVT,
514		.flags	= IORESOURCE_DMA,
515	},
516	{
517		.name	= "common",
518		.start	= IRQ_DA8XX_MCASPINT,
519		.flags	= IORESOURCE_IRQ,
520	},
521};
522
523static struct platform_device da850_mcasp_device = {
524	.name		= "davinci-mcasp",
525	.id		= 0,
526	.num_resources	= ARRAY_SIZE(da850_mcasp_resources),
527	.resource	= da850_mcasp_resources,
528};
529
530void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
531{
532	struct platform_device *pdev;
533
534	switch (id) {
535	case 0:
536		/* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
537		pdev = &da850_mcasp_device;
538		break;
539	case 1:
540		/* Valid for DA830/OMAP-L137 only */
541		if (!cpu_is_davinci_da830())
542			return;
543		pdev = &da830_mcasp1_device;
544		break;
545	case 2:
546		/* Valid for DA830/OMAP-L137 only */
547		if (!cpu_is_davinci_da830())
548			return;
549		pdev = &da830_mcasp2_device;
550		break;
551	default:
552		return;
553	}
554
555	pdev->dev.platform_data = pdata;
556	platform_device_register(pdev);
557}
558
559static struct resource da8xx_pruss_resources[] = {
560	{
561		.start	= DA8XX_PRUSS_MEM_BASE,
562		.end	= DA8XX_PRUSS_MEM_BASE + 0xFFFF,
563		.flags	= IORESOURCE_MEM,
564	},
565	{
566		.start	= IRQ_DA8XX_EVTOUT0,
567		.end	= IRQ_DA8XX_EVTOUT0,
568		.flags	= IORESOURCE_IRQ,
569	},
570	{
571		.start	= IRQ_DA8XX_EVTOUT1,
572		.end	= IRQ_DA8XX_EVTOUT1,
573		.flags	= IORESOURCE_IRQ,
574	},
575	{
576		.start	= IRQ_DA8XX_EVTOUT2,
577		.end	= IRQ_DA8XX_EVTOUT2,
578		.flags	= IORESOURCE_IRQ,
579	},
580	{
581		.start	= IRQ_DA8XX_EVTOUT3,
582		.end	= IRQ_DA8XX_EVTOUT3,
583		.flags	= IORESOURCE_IRQ,
584	},
585	{
586		.start	= IRQ_DA8XX_EVTOUT4,
587		.end	= IRQ_DA8XX_EVTOUT4,
588		.flags	= IORESOURCE_IRQ,
589	},
590	{
591		.start	= IRQ_DA8XX_EVTOUT5,
592		.end	= IRQ_DA8XX_EVTOUT5,
593		.flags	= IORESOURCE_IRQ,
594	},
595	{
596		.start	= IRQ_DA8XX_EVTOUT6,
597		.end	= IRQ_DA8XX_EVTOUT6,
598		.flags	= IORESOURCE_IRQ,
599	},
600	{
601		.start	= IRQ_DA8XX_EVTOUT7,
602		.end	= IRQ_DA8XX_EVTOUT7,
603		.flags	= IORESOURCE_IRQ,
604	},
605};
606
607static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
608	.pintc_base	= 0x4000,
609};
610
611static struct platform_device da8xx_uio_pruss_dev = {
612	.name		= "pruss_uio",
613	.id		= -1,
614	.num_resources	= ARRAY_SIZE(da8xx_pruss_resources),
615	.resource	= da8xx_pruss_resources,
616	.dev		= {
617		.coherent_dma_mask	= DMA_BIT_MASK(32),
618		.platform_data		= &da8xx_uio_pruss_pdata,
619	}
620};
621
622int __init da8xx_register_uio_pruss(void)
623{
624	da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
625	return platform_device_register(&da8xx_uio_pruss_dev);
626}
627
628static struct lcd_ctrl_config lcd_cfg = {
629	.panel_shade		= COLOR_ACTIVE,
630	.bpp			= 16,
631};
632
633struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
634	.manu_name		= "sharp",
635	.controller_data	= &lcd_cfg,
636	.type			= "Sharp_LCD035Q3DG01",
637};
638
639struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
640	.manu_name		= "sharp",
641	.controller_data	= &lcd_cfg,
642	.type			= "Sharp_LK043T1DG01",
643};
644
645static struct resource da8xx_lcdc_resources[] = {
646	[0] = { /* registers */
647		.start  = DA8XX_LCD_CNTRL_BASE,
648		.end    = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
649		.flags  = IORESOURCE_MEM,
650	},
651	[1] = { /* interrupt */
652		.start  = IRQ_DA8XX_LCDINT,
653		.end    = IRQ_DA8XX_LCDINT,
654		.flags  = IORESOURCE_IRQ,
655	},
656};
657
658static struct platform_device da8xx_lcdc_device = {
659	.name		= "da8xx_lcdc",
660	.id		= 0,
661	.num_resources	= ARRAY_SIZE(da8xx_lcdc_resources),
662	.resource	= da8xx_lcdc_resources,
663};
664
665int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
666{
667	da8xx_lcdc_device.dev.platform_data = pdata;
668	return platform_device_register(&da8xx_lcdc_device);
669}
670
671static struct resource da8xx_gpio_resources[] = {
672	{ /* registers */
673		.start	= DA8XX_GPIO_BASE,
674		.end	= DA8XX_GPIO_BASE + SZ_4K - 1,
675		.flags	= IORESOURCE_MEM,
676	},
677	{ /* interrupt */
678		.start	= IRQ_DA8XX_GPIO0,
679		.end	= IRQ_DA8XX_GPIO8,
680		.flags	= IORESOURCE_IRQ,
681	},
682};
683
684static struct platform_device da8xx_gpio_device = {
685	.name		= "davinci_gpio",
686	.id		= -1,
687	.num_resources	= ARRAY_SIZE(da8xx_gpio_resources),
688	.resource	= da8xx_gpio_resources,
689};
690
691int __init da8xx_register_gpio(void *pdata)
692{
693	da8xx_gpio_device.dev.platform_data = pdata;
694	return platform_device_register(&da8xx_gpio_device);
695}
696
697static struct resource da8xx_mmcsd0_resources[] = {
698	{		/* registers */
699		.start	= DA8XX_MMCSD0_BASE,
700		.end	= DA8XX_MMCSD0_BASE + SZ_4K - 1,
701		.flags	= IORESOURCE_MEM,
702	},
703	{		/* interrupt */
704		.start	= IRQ_DA8XX_MMCSDINT0,
705		.end	= IRQ_DA8XX_MMCSDINT0,
706		.flags	= IORESOURCE_IRQ,
707	},
708	{		/* DMA RX */
709		.start	= DA8XX_DMA_MMCSD0_RX,
710		.end	= DA8XX_DMA_MMCSD0_RX,
711		.flags	= IORESOURCE_DMA,
712	},
713	{		/* DMA TX */
714		.start	= DA8XX_DMA_MMCSD0_TX,
715		.end	= DA8XX_DMA_MMCSD0_TX,
716		.flags	= IORESOURCE_DMA,
717	},
718};
719
720static struct platform_device da8xx_mmcsd0_device = {
721	.name		= "da830-mmc",
722	.id		= 0,
723	.num_resources	= ARRAY_SIZE(da8xx_mmcsd0_resources),
724	.resource	= da8xx_mmcsd0_resources,
725};
726
727int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
728{
729	da8xx_mmcsd0_device.dev.platform_data = config;
730	return platform_device_register(&da8xx_mmcsd0_device);
731}
732
733#ifdef CONFIG_ARCH_DAVINCI_DA850
734static struct resource da850_mmcsd1_resources[] = {
735	{		/* registers */
736		.start	= DA850_MMCSD1_BASE,
737		.end	= DA850_MMCSD1_BASE + SZ_4K - 1,
738		.flags	= IORESOURCE_MEM,
739	},
740	{		/* interrupt */
741		.start	= IRQ_DA850_MMCSDINT0_1,
742		.end	= IRQ_DA850_MMCSDINT0_1,
743		.flags	= IORESOURCE_IRQ,
744	},
745	{		/* DMA RX */
746		.start	= DA850_DMA_MMCSD1_RX,
747		.end	= DA850_DMA_MMCSD1_RX,
748		.flags	= IORESOURCE_DMA,
749	},
750	{		/* DMA TX */
751		.start	= DA850_DMA_MMCSD1_TX,
752		.end	= DA850_DMA_MMCSD1_TX,
753		.flags	= IORESOURCE_DMA,
754	},
755};
756
757static struct platform_device da850_mmcsd1_device = {
758	.name		= "da830-mmc",
759	.id		= 1,
760	.num_resources	= ARRAY_SIZE(da850_mmcsd1_resources),
761	.resource	= da850_mmcsd1_resources,
762};
763
764int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
765{
766	da850_mmcsd1_device.dev.platform_data = config;
767	return platform_device_register(&da850_mmcsd1_device);
768}
769#endif
770
771static struct resource da8xx_rproc_resources[] = {
772	{ /* DSP boot address */
773		.start		= DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
774		.end		= DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
775		.flags		= IORESOURCE_MEM,
776	},
777	{ /* DSP interrupt registers */
778		.start		= DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
779		.end		= DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
780		.flags		= IORESOURCE_MEM,
781	},
782	{ /* dsp irq */
783		.start		= IRQ_DA8XX_CHIPINT0,
784		.end		= IRQ_DA8XX_CHIPINT0,
785		.flags		= IORESOURCE_IRQ,
786	},
787};
788
789static struct platform_device da8xx_dsp = {
790	.name	= "davinci-rproc",
791	.dev	= {
792		.coherent_dma_mask	= DMA_BIT_MASK(32),
793	},
794	.num_resources	= ARRAY_SIZE(da8xx_rproc_resources),
795	.resource	= da8xx_rproc_resources,
796};
797
798#if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
799
800static phys_addr_t rproc_base __initdata;
801static unsigned long rproc_size __initdata;
802
803static int __init early_rproc_mem(char *p)
804{
805	char *endp;
806
807	if (p == NULL)
808		return 0;
809
810	rproc_size = memparse(p, &endp);
811	if (*endp == '@')
812		rproc_base = memparse(endp + 1, NULL);
813
814	return 0;
815}
816early_param("rproc_mem", early_rproc_mem);
817
818void __init da8xx_rproc_reserve_cma(void)
819{
820	int ret;
821
822	if (!rproc_base || !rproc_size) {
823		pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
824		       "    'nn' and 'address' must both be non-zero\n",
825		       __func__);
826
827		return;
828	}
829
830	pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
831		__func__, rproc_size, (unsigned long)rproc_base);
832
833	ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
834	if (ret)
835		pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
836}
837
838#else
839
840void __init da8xx_rproc_reserve_cma(void)
841{
842}
843
844#endif
845
846int __init da8xx_register_rproc(void)
847{
848	int ret;
849
850	ret = platform_device_register(&da8xx_dsp);
851	if (ret)
852		pr_err("%s: can't register DSP device: %d\n", __func__, ret);
853
854	return ret;
855};
856
857static struct resource da8xx_rtc_resources[] = {
858	{
859		.start		= DA8XX_RTC_BASE,
860		.end		= DA8XX_RTC_BASE + SZ_4K - 1,
861		.flags		= IORESOURCE_MEM,
862	},
863	{ /* timer irq */
864		.start		= IRQ_DA8XX_RTC,
865		.end		= IRQ_DA8XX_RTC,
866		.flags		= IORESOURCE_IRQ,
867	},
868	{ /* alarm irq */
869		.start		= IRQ_DA8XX_RTC,
870		.end		= IRQ_DA8XX_RTC,
871		.flags		= IORESOURCE_IRQ,
872	},
873};
874
875static struct platform_device da8xx_rtc_device = {
876	.name           = "da830-rtc",
877	.id             = -1,
878	.num_resources	= ARRAY_SIZE(da8xx_rtc_resources),
879	.resource	= da8xx_rtc_resources,
880};
881
882int da8xx_register_rtc(void)
883{
884	return platform_device_register(&da8xx_rtc_device);
885}
886
887static void __iomem *da8xx_ddr2_ctlr_base;
888void __iomem * __init da8xx_get_mem_ctlr(void)
889{
890	if (da8xx_ddr2_ctlr_base)
891		return da8xx_ddr2_ctlr_base;
892
893	da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
894	if (!da8xx_ddr2_ctlr_base)
895		pr_warn("%s: Unable to map DDR2 controller", __func__);
896
897	return da8xx_ddr2_ctlr_base;
898}
899
900static struct resource da8xx_cpuidle_resources[] = {
901	{
902		.start		= DA8XX_DDR2_CTL_BASE,
903		.end		= DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
904		.flags		= IORESOURCE_MEM,
905	},
906};
907
908/* DA8XX devices support DDR2 power down */
909static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
910	.ddr2_pdown	= 1,
911};
912
913
914static struct platform_device da8xx_cpuidle_device = {
915	.name			= "cpuidle-davinci",
916	.num_resources		= ARRAY_SIZE(da8xx_cpuidle_resources),
917	.resource		= da8xx_cpuidle_resources,
918	.dev = {
919		.platform_data	= &da8xx_cpuidle_pdata,
920	},
921};
922
923int __init da8xx_register_cpuidle(void)
924{
925	da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
926
927	return platform_device_register(&da8xx_cpuidle_device);
928}
929
930static struct resource da8xx_spi0_resources[] = {
931	[0] = {
932		.start	= DA8XX_SPI0_BASE,
933		.end	= DA8XX_SPI0_BASE + SZ_4K - 1,
934		.flags	= IORESOURCE_MEM,
935	},
936	[1] = {
937		.start	= IRQ_DA8XX_SPINT0,
938		.end	= IRQ_DA8XX_SPINT0,
939		.flags	= IORESOURCE_IRQ,
940	},
941	[2] = {
942		.start	= DA8XX_DMA_SPI0_RX,
943		.end	= DA8XX_DMA_SPI0_RX,
944		.flags	= IORESOURCE_DMA,
945	},
946	[3] = {
947		.start	= DA8XX_DMA_SPI0_TX,
948		.end	= DA8XX_DMA_SPI0_TX,
949		.flags	= IORESOURCE_DMA,
950	},
951};
952
953static struct resource da8xx_spi1_resources[] = {
954	[0] = {
955		.start	= DA830_SPI1_BASE,
956		.end	= DA830_SPI1_BASE + SZ_4K - 1,
957		.flags	= IORESOURCE_MEM,
958	},
959	[1] = {
960		.start	= IRQ_DA8XX_SPINT1,
961		.end	= IRQ_DA8XX_SPINT1,
962		.flags	= IORESOURCE_IRQ,
963	},
964	[2] = {
965		.start	= DA8XX_DMA_SPI1_RX,
966		.end	= DA8XX_DMA_SPI1_RX,
967		.flags	= IORESOURCE_DMA,
968	},
969	[3] = {
970		.start	= DA8XX_DMA_SPI1_TX,
971		.end	= DA8XX_DMA_SPI1_TX,
972		.flags	= IORESOURCE_DMA,
973	},
974};
975
976static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
977	[0] = {
978		.version	= SPI_VERSION_2,
979		.intr_line	= 1,
980		.dma_event_q	= EVENTQ_0,
981		.prescaler_limit = 2,
982	},
983	[1] = {
984		.version	= SPI_VERSION_2,
985		.intr_line	= 1,
986		.dma_event_q	= EVENTQ_0,
987		.prescaler_limit = 2,
988	},
989};
990
991static struct platform_device da8xx_spi_device[] = {
992	[0] = {
993		.name		= "spi_davinci",
994		.id		= 0,
995		.num_resources	= ARRAY_SIZE(da8xx_spi0_resources),
996		.resource	= da8xx_spi0_resources,
997		.dev		= {
998			.platform_data = &da8xx_spi_pdata[0],
999		},
1000	},
1001	[1] = {
1002		.name		= "spi_davinci",
1003		.id		= 1,
1004		.num_resources	= ARRAY_SIZE(da8xx_spi1_resources),
1005		.resource	= da8xx_spi1_resources,
1006		.dev		= {
1007			.platform_data = &da8xx_spi_pdata[1],
1008		},
1009	},
1010};
1011
1012int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
1013{
1014	if (instance < 0 || instance > 1)
1015		return -EINVAL;
1016
1017	da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
1018
1019	if (instance == 1 && cpu_is_davinci_da850()) {
1020		da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1021		da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1022	}
1023
1024	return platform_device_register(&da8xx_spi_device[instance]);
1025}
1026
1027#ifdef CONFIG_ARCH_DAVINCI_DA850
1028static struct resource da850_sata_resources[] = {
1029	{
1030		.start	= DA850_SATA_BASE,
1031		.end	= DA850_SATA_BASE + 0x1fff,
1032		.flags	= IORESOURCE_MEM,
1033	},
1034	{
1035		.start	= DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
1036		.end	= DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
1037		.flags	= IORESOURCE_MEM,
1038	},
1039	{
1040		.start	= IRQ_DA850_SATAINT,
1041		.flags	= IORESOURCE_IRQ,
1042	},
1043};
1044
1045static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1046
1047static struct platform_device da850_sata_device = {
1048	.name	= "ahci_da850",
1049	.id	= -1,
1050	.dev	= {
1051		.dma_mask		= &da850_sata_dmamask,
1052		.coherent_dma_mask	= DMA_BIT_MASK(32),
1053	},
1054	.num_resources	= ARRAY_SIZE(da850_sata_resources),
1055	.resource	= da850_sata_resources,
1056};
1057
1058int __init da850_register_sata(unsigned long refclkpn)
1059{
1060	/* please see comment in drivers/ata/ahci_da850.c */
1061	BUG_ON(refclkpn != 100 * 1000 * 1000);
1062
1063	return platform_device_register(&da850_sata_device);
1064}
1065#endif
1066