1/* arch/arm/include/debug/sa1100.S
2 *
3 * Debugging macro include header
4 *
5 *  Copyright (C) 1994-1999 Russell King
6 *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#define UTCR3		0x0c
15#define UTDR		0x14
16#define UTSR1		0x20
17#define UTCR3_TXE	0x00000002	/* Transmit Enable                 */
18#define UTSR1_TBY	0x00000001	/* Transmitter BusY (read)         */
19#define UTSR1_TNF	0x00000004	/* Transmit FIFO Not Full (read)   */
20
21		.macro	addruart, rp, rv, tmp
22		mrc	p15, 0, \rp, c1, c0
23		tst	\rp, #1			@ MMU enabled?
24		moveq	\rp, #0x80000000	@ physical base address
25		movne	\rp, #0xf8000000	@ virtual address
26
27		@ We probe for the active serial port here, coherently with
28		@ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
29		@ We assume r1 can be clobbered.
30
31		@ see if Ser3 is active
32		add	\rp, \rp, #0x00050000
33		ldr	\rv, [\rp, #UTCR3]
34		tst	\rv, #UTCR3_TXE
35
36		@ if Ser3 is inactive, then try Ser1
37		addeq	\rp, \rp, #(0x00010000 - 0x00050000)
38		ldreq	\rv, [\rp, #UTCR3]
39		tsteq	\rv, #UTCR3_TXE
40
41		@ if Ser1 is inactive, then try Ser2
42		addeq	\rp, \rp, #(0x00030000 - 0x00010000)
43		ldreq	\rv, [\rp, #UTCR3]
44		tsteq	\rv, #UTCR3_TXE
45
46		@ clear top bits, and generate both phys and virt addresses
47		lsl	\rp, \rp, #8
48		lsr	\rp, \rp, #8
49		orr	\rv, \rp, #0xf8000000	@ virtual
50		orr	\rp, \rp, #0x80000000	@ physical
51
52		.endm
53
54		.macro	senduart,rd,rx
55		str	\rd, [\rx, #UTDR]
56		.endm
57
58		.macro	waituart,rd,rx
591001:		ldr	\rd, [\rx, #UTSR1]
60		tst	\rd, #UTSR1_TNF
61		beq	1001b
62		.endm
63
64		.macro	busyuart,rd,rx
651001:		ldr	\rd, [\rx, #UTSR1]
66		tst	\rd, #UTSR1_TBY
67		bne	1001b
68		.endm
69