1/* 2 * Device Tree Source for UniPhier PH1-Pro4 SoC 3 * 4 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45/include/ "skeleton.dtsi" 46 47/ { 48 compatible = "socionext,ph1-pro4"; 49 50 cpus { 51 #address-cells = <1>; 52 #size-cells = <0>; 53 enable-method = "socionext,uniphier-smp"; 54 55 cpu@0 { 56 device_type = "cpu"; 57 compatible = "arm,cortex-a9"; 58 reg = <0>; 59 next-level-cache = <&l2>; 60 }; 61 62 cpu@1 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a9"; 65 reg = <1>; 66 next-level-cache = <&l2>; 67 }; 68 }; 69 70 clocks { 71 arm_timer_clk: arm_timer_clk { 72 #clock-cells = <0>; 73 compatible = "fixed-clock"; 74 clock-frequency = <50000000>; 75 }; 76 77 uart_clk: uart_clk { 78 #clock-cells = <0>; 79 compatible = "fixed-clock"; 80 clock-frequency = <73728000>; 81 }; 82 83 i2c_clk: i2c_clk { 84 #clock-cells = <0>; 85 compatible = "fixed-clock"; 86 clock-frequency = <50000000>; 87 }; 88 }; 89 90 soc { 91 compatible = "simple-bus"; 92 #address-cells = <1>; 93 #size-cells = <1>; 94 ranges; 95 interrupt-parent = <&intc>; 96 97 extbus: extbus { 98 compatible = "simple-bus"; 99 #address-cells = <2>; 100 #size-cells = <1>; 101 }; 102 103 l2: l2-cache@500c0000 { 104 compatible = "socionext,uniphier-system-cache"; 105 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 106 <0x506c0000 0x400>; 107 interrupts = <0 174 4>, <0 175 4>; 108 cache-unified; 109 cache-size = <(768 * 1024)>; 110 cache-sets = <256>; 111 cache-line-size = <128>; 112 cache-level = <2>; 113 }; 114 115 serial0: serial@54006800 { 116 compatible = "socionext,uniphier-uart"; 117 status = "disabled"; 118 reg = <0x54006800 0x40>; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pinctrl_uart0>; 121 interrupts = <0 33 4>; 122 clocks = <&uart_clk>; 123 fifo-size = <64>; 124 }; 125 126 serial1: serial@54006900 { 127 compatible = "socionext,uniphier-uart"; 128 status = "disabled"; 129 reg = <0x54006900 0x40>; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_uart1>; 132 interrupts = <0 35 4>; 133 clocks = <&uart_clk>; 134 fifo-size = <64>; 135 }; 136 137 serial2: serial@54006a00 { 138 compatible = "socionext,uniphier-uart"; 139 status = "disabled"; 140 reg = <0x54006a00 0x40>; 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_uart2>; 143 interrupts = <0 37 4>; 144 clocks = <&uart_clk>; 145 fifo-size = <64>; 146 }; 147 148 serial3: serial@54006b00 { 149 compatible = "socionext,uniphier-uart"; 150 status = "disabled"; 151 reg = <0x54006b00 0x40>; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_uart3>; 154 interrupts = <0 29 4>; 155 clocks = <&uart_clk>; 156 fifo-size = <64>; 157 }; 158 159 i2c0: i2c@58780000 { 160 compatible = "socionext,uniphier-fi2c"; 161 status = "disabled"; 162 reg = <0x58780000 0x80>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_i2c0>; 167 interrupts = <0 41 4>; 168 clocks = <&i2c_clk>; 169 clock-frequency = <100000>; 170 }; 171 172 i2c1: i2c@58781000 { 173 compatible = "socionext,uniphier-fi2c"; 174 status = "disabled"; 175 reg = <0x58781000 0x80>; 176 #address-cells = <1>; 177 #size-cells = <0>; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_i2c1>; 180 interrupts = <0 42 4>; 181 clocks = <&i2c_clk>; 182 clock-frequency = <100000>; 183 }; 184 185 i2c2: i2c@58782000 { 186 compatible = "socionext,uniphier-fi2c"; 187 status = "disabled"; 188 reg = <0x58782000 0x80>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_i2c2>; 193 interrupts = <0 43 4>; 194 clocks = <&i2c_clk>; 195 clock-frequency = <100000>; 196 }; 197 198 i2c3: i2c@58783000 { 199 compatible = "socionext,uniphier-fi2c"; 200 status = "disabled"; 201 reg = <0x58783000 0x80>; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_i2c3>; 206 interrupts = <0 44 4>; 207 clocks = <&i2c_clk>; 208 clock-frequency = <100000>; 209 }; 210 211 /* i2c4 does not exist */ 212 213 /* chip-internal connection for DMD */ 214 i2c5: i2c@58785000 { 215 compatible = "socionext,uniphier-fi2c"; 216 reg = <0x58785000 0x80>; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 interrupts = <0 25 4>; 220 clocks = <&i2c_clk>; 221 clock-frequency = <400000>; 222 }; 223 224 /* chip-internal connection for HDMI */ 225 i2c6: i2c@58786000 { 226 compatible = "socionext,uniphier-fi2c"; 227 reg = <0x58786000 0x80>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 interrupts = <0 26 4>; 231 clocks = <&i2c_clk>; 232 clock-frequency = <400000>; 233 }; 234 235 system-bus-controller@58c00000 { 236 compatible = "socionext,uniphier-system-bus-controller"; 237 reg = <0x58c00000 0x400>, <0x59800000 0x2000>; 238 }; 239 240 usb2: usb@5a800100 { 241 compatible = "socionext,uniphier-ehci", "generic-ehci"; 242 status = "disabled"; 243 reg = <0x5a800100 0x100>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_usb2>; 246 interrupts = <0 80 4>; 247 }; 248 249 usb3: usb@5a810100 { 250 compatible = "socionext,uniphier-ehci", "generic-ehci"; 251 status = "disabled"; 252 reg = <0x5a810100 0x100>; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&pinctrl_usb3>; 255 interrupts = <0 81 4>; 256 }; 257 258 pinctrl: pinctrl@5f801000 { 259 compatible = "socionext,ph1-pro4-pinctrl", 260 "syscon"; 261 reg = <0x5f801000 0xe00>; 262 }; 263 264 timer@60000200 { 265 compatible = "arm,cortex-a9-global-timer"; 266 reg = <0x60000200 0x20>; 267 interrupts = <1 11 0x304>; 268 clocks = <&arm_timer_clk>; 269 }; 270 271 timer@60000600 { 272 compatible = "arm,cortex-a9-twd-timer"; 273 reg = <0x60000600 0x20>; 274 interrupts = <1 13 0x304>; 275 clocks = <&arm_timer_clk>; 276 }; 277 278 intc: interrupt-controller@60001000 { 279 compatible = "arm,cortex-a9-gic"; 280 #interrupt-cells = <3>; 281 interrupt-controller; 282 reg = <0x60001000 0x1000>, 283 <0x60000100 0x100>; 284 }; 285 }; 286}; 287 288/include/ "uniphier-pinctrl.dtsi" 289