1#include <dt-bindings/clock/tegra124-car.h> 2#include <dt-bindings/gpio/tegra-gpio.h> 3#include <dt-bindings/memory/tegra124-mc.h> 4#include <dt-bindings/pinctrl/pinctrl-tegra.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/reset/tegra124-car.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9 10#include "skeleton.dtsi" 11 12/ { 13 compatible = "nvidia,tegra124"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie-controller@0,01003000 { 19 compatible = "nvidia,tegra124-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ 22 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ 23 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ 38 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ 39 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ 40 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 41 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 44 <&tegra_car TEGRA124_CLK_AFI>, 45 <&tegra_car TEGRA124_CLK_PLL_E>, 46 <&tegra_car TEGRA124_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 status = "disabled"; 53 54 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; 55 phy-names = "pcie"; 56 57 pci@1,0 { 58 device_type = "pci"; 59 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 60 reg = <0x000800 0 0 0 0>; 61 status = "disabled"; 62 63 #address-cells = <3>; 64 #size-cells = <2>; 65 ranges; 66 67 nvidia,num-lanes = <2>; 68 }; 69 70 pci@2,0 { 71 device_type = "pci"; 72 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 73 reg = <0x001000 0 0 0 0>; 74 status = "disabled"; 75 76 #address-cells = <3>; 77 #size-cells = <2>; 78 ranges; 79 80 nvidia,num-lanes = <1>; 81 }; 82 }; 83 84 host1x@0,50000000 { 85 compatible = "nvidia,tegra124-host1x", "simple-bus"; 86 reg = <0x0 0x50000000 0x0 0x00034000>; 87 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 88 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 89 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 90 resets = <&tegra_car 28>; 91 reset-names = "host1x"; 92 93 #address-cells = <2>; 94 #size-cells = <2>; 95 96 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 97 98 dc@0,54200000 { 99 compatible = "nvidia,tegra124-dc"; 100 reg = <0x0 0x54200000 0x0 0x00040000>; 101 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 102 clocks = <&tegra_car TEGRA124_CLK_DISP1>, 103 <&tegra_car TEGRA124_CLK_PLL_P>; 104 clock-names = "dc", "parent"; 105 resets = <&tegra_car 27>; 106 reset-names = "dc"; 107 108 iommus = <&mc TEGRA_SWGROUP_DC>; 109 110 nvidia,head = <0>; 111 }; 112 113 dc@0,54240000 { 114 compatible = "nvidia,tegra124-dc"; 115 reg = <0x0 0x54240000 0x0 0x00040000>; 116 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&tegra_car TEGRA124_CLK_DISP2>, 118 <&tegra_car TEGRA124_CLK_PLL_P>; 119 clock-names = "dc", "parent"; 120 resets = <&tegra_car 26>; 121 reset-names = "dc"; 122 123 iommus = <&mc TEGRA_SWGROUP_DCB>; 124 125 nvidia,head = <1>; 126 }; 127 128 hdmi@0,54280000 { 129 compatible = "nvidia,tegra124-hdmi"; 130 reg = <0x0 0x54280000 0x0 0x00040000>; 131 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 133 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 134 clock-names = "hdmi", "parent"; 135 resets = <&tegra_car 51>; 136 reset-names = "hdmi"; 137 status = "disabled"; 138 }; 139 140 sor@0,54540000 { 141 compatible = "nvidia,tegra124-sor"; 142 reg = <0x0 0x54540000 0x0 0x00040000>; 143 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 145 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 146 <&tegra_car TEGRA124_CLK_PLL_DP>, 147 <&tegra_car TEGRA124_CLK_CLK_M>; 148 clock-names = "sor", "parent", "dp", "safe"; 149 resets = <&tegra_car 182>; 150 reset-names = "sor"; 151 status = "disabled"; 152 }; 153 154 dpaux: dpaux@0,545c0000 { 155 compatible = "nvidia,tegra124-dpaux"; 156 reg = <0x0 0x545c0000 0x0 0x00040000>; 157 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 159 <&tegra_car TEGRA124_CLK_PLL_DP>; 160 clock-names = "dpaux", "parent"; 161 resets = <&tegra_car 181>; 162 reset-names = "dpaux"; 163 status = "disabled"; 164 }; 165 }; 166 167 gic: interrupt-controller@0,50041000 { 168 compatible = "arm,cortex-a15-gic"; 169 #interrupt-cells = <3>; 170 interrupt-controller; 171 reg = <0x0 0x50041000 0x0 0x1000>, 172 <0x0 0x50042000 0x0 0x1000>, 173 <0x0 0x50044000 0x0 0x2000>, 174 <0x0 0x50046000 0x0 0x2000>; 175 interrupts = <GIC_PPI 9 176 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 177 interrupt-parent = <&gic>; 178 }; 179 180 gpu@0,57000000 { 181 compatible = "nvidia,gk20a"; 182 reg = <0x0 0x57000000 0x0 0x01000000>, 183 <0x0 0x58000000 0x0 0x01000000>; 184 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 186 interrupt-names = "stall", "nonstall"; 187 clocks = <&tegra_car TEGRA124_CLK_GPU>, 188 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 189 clock-names = "gpu", "pwr"; 190 resets = <&tegra_car 184>; 191 reset-names = "gpu"; 192 193 iommus = <&mc TEGRA_SWGROUP_GPU>; 194 195 status = "disabled"; 196 }; 197 198 lic: interrupt-controller@60004000 { 199 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 200 reg = <0x0 0x60004000 0x0 0x100>, 201 <0x0 0x60004100 0x0 0x100>, 202 <0x0 0x60004200 0x0 0x100>, 203 <0x0 0x60004300 0x0 0x100>, 204 <0x0 0x60004400 0x0 0x100>; 205 interrupt-controller; 206 #interrupt-cells = <3>; 207 interrupt-parent = <&gic>; 208 }; 209 210 timer@0,60005000 { 211 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 212 reg = <0x0 0x60005000 0x0 0x400>; 213 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 220 }; 221 222 tegra_car: clock@0,60006000 { 223 compatible = "nvidia,tegra124-car"; 224 reg = <0x0 0x60006000 0x0 0x1000>; 225 #clock-cells = <1>; 226 #reset-cells = <1>; 227 nvidia,external-memory-controller = <&emc>; 228 }; 229 230 flow-controller@0,60007000 { 231 compatible = "nvidia,tegra124-flowctrl"; 232 reg = <0x0 0x60007000 0x0 0x1000>; 233 }; 234 235 actmon@0,6000c800 { 236 compatible = "nvidia,tegra124-actmon"; 237 reg = <0x0 0x6000c800 0x0 0x400>; 238 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 240 <&tegra_car TEGRA124_CLK_EMC>; 241 clock-names = "actmon", "emc"; 242 resets = <&tegra_car 119>; 243 reset-names = "actmon"; 244 }; 245 246 gpio: gpio@0,6000d000 { 247 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 248 reg = <0x0 0x6000d000 0x0 0x1000>; 249 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 257 #gpio-cells = <2>; 258 gpio-controller; 259 #interrupt-cells = <2>; 260 interrupt-controller; 261 /* 262 gpio-ranges = <&pinmux 0 0 251>; 263 */ 264 }; 265 266 apbdma: dma@0,60020000 { 267 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 268 reg = <0x0 0x60020000 0x0 0x1400>; 269 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 302 resets = <&tegra_car 34>; 303 reset-names = "dma"; 304 #dma-cells = <1>; 305 }; 306 307 apbmisc@0,70000800 { 308 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 309 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 310 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 311 }; 312 313 pinmux: pinmux@0,70000868 { 314 compatible = "nvidia,tegra124-pinmux"; 315 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 316 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 317 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 318 }; 319 320 /* 321 * There are two serial driver i.e. 8250 based simple serial 322 * driver and APB DMA based serial driver for higher baudrate 323 * and performace. To enable the 8250 based driver, the compatible 324 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 325 * the APB DMA based serial driver, the comptible is 326 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 327 */ 328 uarta: serial@0,70006000 { 329 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 330 reg = <0x0 0x70006000 0x0 0x40>; 331 reg-shift = <2>; 332 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 334 resets = <&tegra_car 6>; 335 reset-names = "serial"; 336 dmas = <&apbdma 8>, <&apbdma 8>; 337 dma-names = "rx", "tx"; 338 status = "disabled"; 339 }; 340 341 uartb: serial@0,70006040 { 342 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 343 reg = <0x0 0x70006040 0x0 0x40>; 344 reg-shift = <2>; 345 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 347 resets = <&tegra_car 7>; 348 reset-names = "serial"; 349 dmas = <&apbdma 9>, <&apbdma 9>; 350 dma-names = "rx", "tx"; 351 status = "disabled"; 352 }; 353 354 uartc: serial@0,70006200 { 355 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 356 reg = <0x0 0x70006200 0x0 0x40>; 357 reg-shift = <2>; 358 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 360 resets = <&tegra_car 55>; 361 reset-names = "serial"; 362 dmas = <&apbdma 10>, <&apbdma 10>; 363 dma-names = "rx", "tx"; 364 status = "disabled"; 365 }; 366 367 uartd: serial@0,70006300 { 368 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 369 reg = <0x0 0x70006300 0x0 0x40>; 370 reg-shift = <2>; 371 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 373 resets = <&tegra_car 65>; 374 reset-names = "serial"; 375 dmas = <&apbdma 19>, <&apbdma 19>; 376 dma-names = "rx", "tx"; 377 status = "disabled"; 378 }; 379 380 pwm: pwm@0,7000a000 { 381 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 382 reg = <0x0 0x7000a000 0x0 0x100>; 383 #pwm-cells = <2>; 384 clocks = <&tegra_car TEGRA124_CLK_PWM>; 385 resets = <&tegra_car 17>; 386 reset-names = "pwm"; 387 status = "disabled"; 388 }; 389 390 i2c@0,7000c000 { 391 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 392 reg = <0x0 0x7000c000 0x0 0x100>; 393 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 397 clock-names = "div-clk"; 398 resets = <&tegra_car 12>; 399 reset-names = "i2c"; 400 dmas = <&apbdma 21>, <&apbdma 21>; 401 dma-names = "rx", "tx"; 402 status = "disabled"; 403 }; 404 405 i2c@0,7000c400 { 406 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 407 reg = <0x0 0x7000c400 0x0 0x100>; 408 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 412 clock-names = "div-clk"; 413 resets = <&tegra_car 54>; 414 reset-names = "i2c"; 415 dmas = <&apbdma 22>, <&apbdma 22>; 416 dma-names = "rx", "tx"; 417 status = "disabled"; 418 }; 419 420 i2c@0,7000c500 { 421 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 422 reg = <0x0 0x7000c500 0x0 0x100>; 423 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 427 clock-names = "div-clk"; 428 resets = <&tegra_car 67>; 429 reset-names = "i2c"; 430 dmas = <&apbdma 23>, <&apbdma 23>; 431 dma-names = "rx", "tx"; 432 status = "disabled"; 433 }; 434 435 i2c@0,7000c700 { 436 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 437 reg = <0x0 0x7000c700 0x0 0x100>; 438 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 442 clock-names = "div-clk"; 443 resets = <&tegra_car 103>; 444 reset-names = "i2c"; 445 dmas = <&apbdma 26>, <&apbdma 26>; 446 dma-names = "rx", "tx"; 447 status = "disabled"; 448 }; 449 450 i2c@0,7000d000 { 451 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 452 reg = <0x0 0x7000d000 0x0 0x100>; 453 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 457 clock-names = "div-clk"; 458 resets = <&tegra_car 47>; 459 reset-names = "i2c"; 460 dmas = <&apbdma 24>, <&apbdma 24>; 461 dma-names = "rx", "tx"; 462 status = "disabled"; 463 }; 464 465 i2c@0,7000d100 { 466 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 467 reg = <0x0 0x7000d100 0x0 0x100>; 468 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 472 clock-names = "div-clk"; 473 resets = <&tegra_car 166>; 474 reset-names = "i2c"; 475 dmas = <&apbdma 30>, <&apbdma 30>; 476 dma-names = "rx", "tx"; 477 status = "disabled"; 478 }; 479 480 spi@0,7000d400 { 481 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 482 reg = <0x0 0x7000d400 0x0 0x200>; 483 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 487 clock-names = "spi"; 488 resets = <&tegra_car 41>; 489 reset-names = "spi"; 490 dmas = <&apbdma 15>, <&apbdma 15>; 491 dma-names = "rx", "tx"; 492 status = "disabled"; 493 }; 494 495 spi@0,7000d600 { 496 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 497 reg = <0x0 0x7000d600 0x0 0x200>; 498 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 502 clock-names = "spi"; 503 resets = <&tegra_car 44>; 504 reset-names = "spi"; 505 dmas = <&apbdma 16>, <&apbdma 16>; 506 dma-names = "rx", "tx"; 507 status = "disabled"; 508 }; 509 510 spi@0,7000d800 { 511 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 512 reg = <0x0 0x7000d800 0x0 0x200>; 513 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 517 clock-names = "spi"; 518 resets = <&tegra_car 46>; 519 reset-names = "spi"; 520 dmas = <&apbdma 17>, <&apbdma 17>; 521 dma-names = "rx", "tx"; 522 status = "disabled"; 523 }; 524 525 spi@0,7000da00 { 526 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 527 reg = <0x0 0x7000da00 0x0 0x200>; 528 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 532 clock-names = "spi"; 533 resets = <&tegra_car 68>; 534 reset-names = "spi"; 535 dmas = <&apbdma 18>, <&apbdma 18>; 536 dma-names = "rx", "tx"; 537 status = "disabled"; 538 }; 539 540 spi@0,7000dc00 { 541 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 542 reg = <0x0 0x7000dc00 0x0 0x200>; 543 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 547 clock-names = "spi"; 548 resets = <&tegra_car 104>; 549 reset-names = "spi"; 550 dmas = <&apbdma 27>, <&apbdma 27>; 551 dma-names = "rx", "tx"; 552 status = "disabled"; 553 }; 554 555 spi@0,7000de00 { 556 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 557 reg = <0x0 0x7000de00 0x0 0x200>; 558 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 562 clock-names = "spi"; 563 resets = <&tegra_car 105>; 564 reset-names = "spi"; 565 dmas = <&apbdma 28>, <&apbdma 28>; 566 dma-names = "rx", "tx"; 567 status = "disabled"; 568 }; 569 570 rtc@0,7000e000 { 571 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 572 reg = <0x0 0x7000e000 0x0 0x100>; 573 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&tegra_car TEGRA124_CLK_RTC>; 575 }; 576 577 pmc@0,7000e400 { 578 compatible = "nvidia,tegra124-pmc"; 579 reg = <0x0 0x7000e400 0x0 0x400>; 580 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 581 clock-names = "pclk", "clk32k_in"; 582 }; 583 584 fuse@0,7000f800 { 585 compatible = "nvidia,tegra124-efuse"; 586 reg = <0x0 0x7000f800 0x0 0x400>; 587 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 588 clock-names = "fuse"; 589 resets = <&tegra_car 39>; 590 reset-names = "fuse"; 591 }; 592 593 mc: memory-controller@0,70019000 { 594 compatible = "nvidia,tegra124-mc"; 595 reg = <0x0 0x70019000 0x0 0x1000>; 596 clocks = <&tegra_car TEGRA124_CLK_MC>; 597 clock-names = "mc"; 598 599 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 600 601 #iommu-cells = <1>; 602 }; 603 604 emc: emc@0,7001b000 { 605 compatible = "nvidia,tegra124-emc"; 606 reg = <0x0 0x7001b000 0x0 0x1000>; 607 608 nvidia,memory-controller = <&mc>; 609 }; 610 611 sata@0,70020000 { 612 compatible = "nvidia,tegra124-ahci"; 613 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 614 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 615 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&tegra_car TEGRA124_CLK_SATA>, 617 <&tegra_car TEGRA124_CLK_SATA_OOB>, 618 <&tegra_car TEGRA124_CLK_CML1>, 619 <&tegra_car TEGRA124_CLK_PLL_E>; 620 clock-names = "sata", "sata-oob", "cml1", "pll_e"; 621 resets = <&tegra_car 124>, 622 <&tegra_car 123>, 623 <&tegra_car 129>; 624 reset-names = "sata", "sata-oob", "sata-cold"; 625 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; 626 phy-names = "sata-phy"; 627 status = "disabled"; 628 }; 629 630 hda@0,70030000 { 631 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; 632 reg = <0x0 0x70030000 0x0 0x10000>; 633 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&tegra_car TEGRA124_CLK_HDA>, 635 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 636 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 637 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 638 resets = <&tegra_car 125>, /* hda */ 639 <&tegra_car 128>, /* hda2hdmi */ 640 <&tegra_car 111>; /* hda2codec_2x */ 641 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 642 status = "disabled"; 643 }; 644 645 padctl: padctl@0,7009f000 { 646 compatible = "nvidia,tegra124-xusb-padctl"; 647 reg = <0x0 0x7009f000 0x0 0x1000>; 648 resets = <&tegra_car 142>; 649 reset-names = "padctl"; 650 651 #phy-cells = <1>; 652 }; 653 654 sdhci@0,700b0000 { 655 compatible = "nvidia,tegra124-sdhci"; 656 reg = <0x0 0x700b0000 0x0 0x200>; 657 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 659 resets = <&tegra_car 14>; 660 reset-names = "sdhci"; 661 status = "disabled"; 662 }; 663 664 sdhci@0,700b0200 { 665 compatible = "nvidia,tegra124-sdhci"; 666 reg = <0x0 0x700b0200 0x0 0x200>; 667 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 668 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 669 resets = <&tegra_car 9>; 670 reset-names = "sdhci"; 671 status = "disabled"; 672 }; 673 674 sdhci@0,700b0400 { 675 compatible = "nvidia,tegra124-sdhci"; 676 reg = <0x0 0x700b0400 0x0 0x200>; 677 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 679 resets = <&tegra_car 69>; 680 reset-names = "sdhci"; 681 status = "disabled"; 682 }; 683 684 sdhci@0,700b0600 { 685 compatible = "nvidia,tegra124-sdhci"; 686 reg = <0x0 0x700b0600 0x0 0x200>; 687 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 689 resets = <&tegra_car 15>; 690 reset-names = "sdhci"; 691 status = "disabled"; 692 }; 693 694 soctherm: thermal-sensor@0,700e2000 { 695 compatible = "nvidia,tegra124-soctherm"; 696 reg = <0x0 0x700e2000 0x0 0x1000>; 697 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 699 <&tegra_car TEGRA124_CLK_SOC_THERM>; 700 clock-names = "tsensor", "soctherm"; 701 resets = <&tegra_car 78>; 702 reset-names = "soctherm"; 703 #thermal-sensor-cells = <1>; 704 }; 705 706 dfll: clock@0,70110000 { 707 compatible = "nvidia,tegra124-dfll"; 708 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 709 <0 0x70110000 0 0x100>, /* I2C output control */ 710 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 711 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 712 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, 714 <&tegra_car TEGRA124_CLK_DFLL_REF>, 715 <&tegra_car TEGRA124_CLK_I2C5>; 716 clock-names = "soc", "ref", "i2c"; 717 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; 718 reset-names = "dvco"; 719 #clock-cells = <0>; 720 clock-output-names = "dfllCPU_out"; 721 nvidia,sample-rate = <12500>; 722 nvidia,droop-ctrl = <0x00000f00>; 723 nvidia,force-mode = <1>; 724 nvidia,cf = <10>; 725 nvidia,ci = <0>; 726 nvidia,cg = <2>; 727 status = "disabled"; 728 }; 729 730 ahub@0,70300000 { 731 compatible = "nvidia,tegra124-ahub"; 732 reg = <0x0 0x70300000 0x0 0x200>, 733 <0x0 0x70300800 0x0 0x800>, 734 <0x0 0x70300200 0x0 0x600>; 735 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 737 <&tegra_car TEGRA124_CLK_APBIF>; 738 clock-names = "d_audio", "apbif"; 739 resets = <&tegra_car 106>, /* d_audio */ 740 <&tegra_car 107>, /* apbif */ 741 <&tegra_car 30>, /* i2s0 */ 742 <&tegra_car 11>, /* i2s1 */ 743 <&tegra_car 18>, /* i2s2 */ 744 <&tegra_car 101>, /* i2s3 */ 745 <&tegra_car 102>, /* i2s4 */ 746 <&tegra_car 108>, /* dam0 */ 747 <&tegra_car 109>, /* dam1 */ 748 <&tegra_car 110>, /* dam2 */ 749 <&tegra_car 10>, /* spdif */ 750 <&tegra_car 153>, /* amx */ 751 <&tegra_car 185>, /* amx1 */ 752 <&tegra_car 154>, /* adx */ 753 <&tegra_car 180>, /* adx1 */ 754 <&tegra_car 186>, /* afc0 */ 755 <&tegra_car 187>, /* afc1 */ 756 <&tegra_car 188>, /* afc2 */ 757 <&tegra_car 189>, /* afc3 */ 758 <&tegra_car 190>, /* afc4 */ 759 <&tegra_car 191>; /* afc5 */ 760 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 761 "i2s3", "i2s4", "dam0", "dam1", "dam2", 762 "spdif", "amx", "amx1", "adx", "adx1", 763 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 764 dmas = <&apbdma 1>, <&apbdma 1>, 765 <&apbdma 2>, <&apbdma 2>, 766 <&apbdma 3>, <&apbdma 3>, 767 <&apbdma 4>, <&apbdma 4>, 768 <&apbdma 6>, <&apbdma 6>, 769 <&apbdma 7>, <&apbdma 7>, 770 <&apbdma 12>, <&apbdma 12>, 771 <&apbdma 13>, <&apbdma 13>, 772 <&apbdma 14>, <&apbdma 14>, 773 <&apbdma 29>, <&apbdma 29>; 774 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 775 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 776 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 777 "rx9", "tx9"; 778 ranges; 779 #address-cells = <2>; 780 #size-cells = <2>; 781 782 tegra_i2s0: i2s@0,70301000 { 783 compatible = "nvidia,tegra124-i2s"; 784 reg = <0x0 0x70301000 0x0 0x100>; 785 nvidia,ahub-cif-ids = <4 4>; 786 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 787 resets = <&tegra_car 30>; 788 reset-names = "i2s"; 789 status = "disabled"; 790 }; 791 792 tegra_i2s1: i2s@0,70301100 { 793 compatible = "nvidia,tegra124-i2s"; 794 reg = <0x0 0x70301100 0x0 0x100>; 795 nvidia,ahub-cif-ids = <5 5>; 796 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 797 resets = <&tegra_car 11>; 798 reset-names = "i2s"; 799 status = "disabled"; 800 }; 801 802 tegra_i2s2: i2s@0,70301200 { 803 compatible = "nvidia,tegra124-i2s"; 804 reg = <0x0 0x70301200 0x0 0x100>; 805 nvidia,ahub-cif-ids = <6 6>; 806 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 807 resets = <&tegra_car 18>; 808 reset-names = "i2s"; 809 status = "disabled"; 810 }; 811 812 tegra_i2s3: i2s@0,70301300 { 813 compatible = "nvidia,tegra124-i2s"; 814 reg = <0x0 0x70301300 0x0 0x100>; 815 nvidia,ahub-cif-ids = <7 7>; 816 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 817 resets = <&tegra_car 101>; 818 reset-names = "i2s"; 819 status = "disabled"; 820 }; 821 822 tegra_i2s4: i2s@0,70301400 { 823 compatible = "nvidia,tegra124-i2s"; 824 reg = <0x0 0x70301400 0x0 0x100>; 825 nvidia,ahub-cif-ids = <8 8>; 826 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 827 resets = <&tegra_car 102>; 828 reset-names = "i2s"; 829 status = "disabled"; 830 }; 831 }; 832 833 usb@0,7d000000 { 834 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 835 reg = <0x0 0x7d000000 0x0 0x4000>; 836 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 837 phy_type = "utmi"; 838 clocks = <&tegra_car TEGRA124_CLK_USBD>; 839 resets = <&tegra_car 22>; 840 reset-names = "usb"; 841 nvidia,phy = <&phy1>; 842 status = "disabled"; 843 }; 844 845 phy1: usb-phy@0,7d000000 { 846 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 847 reg = <0x0 0x7d000000 0x0 0x4000>, 848 <0x0 0x7d000000 0x0 0x4000>; 849 phy_type = "utmi"; 850 clocks = <&tegra_car TEGRA124_CLK_USBD>, 851 <&tegra_car TEGRA124_CLK_PLL_U>, 852 <&tegra_car TEGRA124_CLK_USBD>; 853 clock-names = "reg", "pll_u", "utmi-pads"; 854 resets = <&tegra_car 22>, <&tegra_car 22>; 855 reset-names = "usb", "utmi-pads"; 856 nvidia,hssync-start-delay = <0>; 857 nvidia,idle-wait-delay = <17>; 858 nvidia,elastic-limit = <16>; 859 nvidia,term-range-adj = <6>; 860 nvidia,xcvr-setup = <9>; 861 nvidia,xcvr-lsfslew = <0>; 862 nvidia,xcvr-lsrslew = <3>; 863 nvidia,hssquelch-level = <2>; 864 nvidia,hsdiscon-level = <5>; 865 nvidia,xcvr-hsslew = <12>; 866 nvidia,has-utmi-pad-registers; 867 status = "disabled"; 868 }; 869 870 usb@0,7d004000 { 871 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 872 reg = <0x0 0x7d004000 0x0 0x4000>; 873 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 874 phy_type = "utmi"; 875 clocks = <&tegra_car TEGRA124_CLK_USB2>; 876 resets = <&tegra_car 58>; 877 reset-names = "usb"; 878 nvidia,phy = <&phy2>; 879 status = "disabled"; 880 }; 881 882 phy2: usb-phy@0,7d004000 { 883 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 884 reg = <0x0 0x7d004000 0x0 0x4000>, 885 <0x0 0x7d000000 0x0 0x4000>; 886 phy_type = "utmi"; 887 clocks = <&tegra_car TEGRA124_CLK_USB2>, 888 <&tegra_car TEGRA124_CLK_PLL_U>, 889 <&tegra_car TEGRA124_CLK_USBD>; 890 clock-names = "reg", "pll_u", "utmi-pads"; 891 resets = <&tegra_car 58>, <&tegra_car 22>; 892 reset-names = "usb", "utmi-pads"; 893 nvidia,hssync-start-delay = <0>; 894 nvidia,idle-wait-delay = <17>; 895 nvidia,elastic-limit = <16>; 896 nvidia,term-range-adj = <6>; 897 nvidia,xcvr-setup = <9>; 898 nvidia,xcvr-lsfslew = <0>; 899 nvidia,xcvr-lsrslew = <3>; 900 nvidia,hssquelch-level = <2>; 901 nvidia,hsdiscon-level = <5>; 902 nvidia,xcvr-hsslew = <12>; 903 status = "disabled"; 904 }; 905 906 usb@0,7d008000 { 907 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 908 reg = <0x0 0x7d008000 0x0 0x4000>; 909 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 910 phy_type = "utmi"; 911 clocks = <&tegra_car TEGRA124_CLK_USB3>; 912 resets = <&tegra_car 59>; 913 reset-names = "usb"; 914 nvidia,phy = <&phy3>; 915 status = "disabled"; 916 }; 917 918 phy3: usb-phy@0,7d008000 { 919 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 920 reg = <0x0 0x7d008000 0x0 0x4000>, 921 <0x0 0x7d000000 0x0 0x4000>; 922 phy_type = "utmi"; 923 clocks = <&tegra_car TEGRA124_CLK_USB3>, 924 <&tegra_car TEGRA124_CLK_PLL_U>, 925 <&tegra_car TEGRA124_CLK_USBD>; 926 clock-names = "reg", "pll_u", "utmi-pads"; 927 resets = <&tegra_car 59>, <&tegra_car 22>; 928 reset-names = "usb", "utmi-pads"; 929 nvidia,hssync-start-delay = <0>; 930 nvidia,idle-wait-delay = <17>; 931 nvidia,elastic-limit = <16>; 932 nvidia,term-range-adj = <6>; 933 nvidia,xcvr-setup = <9>; 934 nvidia,xcvr-lsfslew = <0>; 935 nvidia,xcvr-lsrslew = <3>; 936 nvidia,hssquelch-level = <2>; 937 nvidia,hsdiscon-level = <5>; 938 nvidia,xcvr-hsslew = <12>; 939 status = "disabled"; 940 }; 941 942 cpus { 943 #address-cells = <1>; 944 #size-cells = <0>; 945 946 cpu@0 { 947 device_type = "cpu"; 948 compatible = "arm,cortex-a15"; 949 reg = <0>; 950 951 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, 952 <&tegra_car TEGRA124_CLK_CCLK_LP>, 953 <&tegra_car TEGRA124_CLK_PLL_X>, 954 <&tegra_car TEGRA124_CLK_PLL_P>, 955 <&dfll>; 956 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; 957 /* FIXME: what's the actual transition time? */ 958 clock-latency = <300000>; 959 }; 960 961 cpu@1 { 962 device_type = "cpu"; 963 compatible = "arm,cortex-a15"; 964 reg = <1>; 965 }; 966 967 cpu@2 { 968 device_type = "cpu"; 969 compatible = "arm,cortex-a15"; 970 reg = <2>; 971 }; 972 973 cpu@3 { 974 device_type = "cpu"; 975 compatible = "arm,cortex-a15"; 976 reg = <3>; 977 }; 978 }; 979 980 pmu { 981 compatible = "arm,cortex-a15-pmu"; 982 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 986 interrupt-affinity = <&{/cpus/cpu@0}>, 987 <&{/cpus/cpu@1}>, 988 <&{/cpus/cpu@2}>, 989 <&{/cpus/cpu@3}>; 990 }; 991 992 thermal-zones { 993 cpu { 994 polling-delay-passive = <1000>; 995 polling-delay = <1000>; 996 997 thermal-sensors = 998 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 999 }; 1000 1001 mem { 1002 polling-delay-passive = <1000>; 1003 polling-delay = <1000>; 1004 1005 thermal-sensors = 1006 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1007 }; 1008 1009 gpu { 1010 polling-delay-passive = <1000>; 1011 polling-delay = <1000>; 1012 1013 thermal-sensors = 1014 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1015 }; 1016 1017 pllx { 1018 polling-delay-passive = <1000>; 1019 polling-delay = <1000>; 1020 1021 thermal-sensors = 1022 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1023 }; 1024 }; 1025 1026 timer { 1027 compatible = "arm,armv7-timer"; 1028 interrupts = <GIC_PPI 13 1029 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1030 <GIC_PPI 14 1031 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1032 <GIC_PPI 11 1033 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1034 <GIC_PPI 10 1035 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1036 interrupt-parent = <&gic>; 1037 }; 1038}; 1039