1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "st-pincfg.h"
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11/ {
12
13	aliases {
14		/* 0-5: PIO_SBC */
15		gpio0 = &pio0;
16		gpio1 = &pio1;
17		gpio2 = &pio2;
18		gpio3 = &pio3;
19		gpio4 = &pio4;
20		gpio5 = &pio5;
21		/* 10-19: PIO_FRONT0 */
22		gpio6 = &pio10;
23		gpio7 = &pio11;
24		gpio8 = &pio12;
25		gpio9 = &pio13;
26		gpio10 = &pio14;
27		gpio11 = &pio15;
28		gpio12 = &pio16;
29		gpio13 = &pio17;
30		gpio14 = &pio18;
31		gpio15 = &pio19;
32		/* 20: PIO_FRONT1 */
33		gpio16 = &pio20;
34		/* 30-35: PIO_REAR */
35		gpio17 = &pio30;
36		gpio18 = &pio31;
37		gpio19 = &pio32;
38		gpio20 = &pio33;
39		gpio21 = &pio34;
40		gpio22 = &pio35;
41		/* 40-42: PIO_FLASH */
42		gpio23 = &pio40;
43		gpio24 = &pio41;
44		gpio25 = &pio42;
45	};
46
47	soc {
48		pin-controller-sbc {
49			#address-cells = <1>;
50			#size-cells = <1>;
51			compatible = "st,stih407-sbc-pinctrl";
52			st,syscfg = <&syscfg_sbc>;
53			reg = <0x0961f080 0x4>;
54			reg-names = "irqmux";
55			interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
56			interrupt-names = "irqmux";
57			ranges = <0 0x09610000 0x6000>;
58
59			pio0: gpio@09610000 {
60				gpio-controller;
61				#gpio-cells = <1>;
62				interrupt-controller;
63				#interrupt-cells = <2>;
64				reg = <0x0 0x100>;
65				st,bank-name = "PIO0";
66			};
67			pio1: gpio@09611000 {
68				gpio-controller;
69				#gpio-cells = <1>;
70				interrupt-controller;
71				#interrupt-cells = <2>;
72				reg = <0x1000 0x100>;
73				st,bank-name = "PIO1";
74			};
75			pio2: gpio@09612000 {
76				gpio-controller;
77				#gpio-cells = <1>;
78				interrupt-controller;
79				#interrupt-cells = <2>;
80				reg = <0x2000 0x100>;
81				st,bank-name = "PIO2";
82			};
83			pio3: gpio@09613000 {
84				gpio-controller;
85				#gpio-cells = <1>;
86				interrupt-controller;
87				#interrupt-cells = <2>;
88				reg = <0x3000 0x100>;
89				st,bank-name = "PIO3";
90			};
91			pio4: gpio@09614000 {
92				gpio-controller;
93				#gpio-cells = <1>;
94				interrupt-controller;
95				#interrupt-cells = <2>;
96				reg = <0x4000 0x100>;
97				st,bank-name = "PIO4";
98			};
99
100			pio5: gpio@09615000 {
101				gpio-controller;
102				#gpio-cells = <1>;
103				interrupt-controller;
104				#interrupt-cells = <2>;
105				reg = <0x5000 0x100>;
106				st,bank-name = "PIO5";
107				st,retime-pin-mask = <0x3f>;
108			};
109
110			cec0 {
111				pinctrl_cec0_default: cec0-default {
112					st,pins {
113						hdmi_cec = <&pio2 4 ALT1 BIDIR>;
114					};
115				};
116			};
117
118			rc {
119				pinctrl_ir: ir0 {
120					st,pins {
121						ir = <&pio4 0 ALT2 IN>;
122					};
123				};
124
125				pinctrl_uhf: uhf0 {
126					st,pins {
127						ir = <&pio4 1 ALT2 IN>;
128					};
129				};
130
131				pinctrl_tx: tx0 {
132					st,pins {
133						tx = <&pio4 2 ALT2 OUT>;
134					};
135				};
136
137				pinctrl_tx_od: tx_od0 {
138					st,pins {
139						tx_od = <&pio4 3 ALT2 OUT>;
140					};
141				};
142			};
143
144			/* SBC_ASC0 - UART10 */
145			sbc_serial0 {
146				pinctrl_sbc_serial0: sbc_serial0-0 {
147					st,pins {
148						tx = <&pio3 4 ALT1 OUT>;
149						rx = <&pio3 5 ALT1 IN>;
150					};
151				};
152			};
153			/* SBC_ASC1 - UART11 */
154			sbc_serial1 {
155				pinctrl_sbc_serial1: sbc_serial1-0 {
156					st,pins {
157						tx = <&pio2 6 ALT3 OUT>;
158						rx = <&pio2 7 ALT3 IN>;
159					};
160				};
161			};
162
163			i2c10 {
164				pinctrl_i2c10_default: i2c10-default {
165					st,pins {
166						sda = <&pio4 6 ALT1 BIDIR>;
167						scl = <&pio4 5 ALT1 BIDIR>;
168					};
169				};
170			};
171
172			i2c11 {
173				pinctrl_i2c11_default: i2c11-default {
174					st,pins {
175						sda = <&pio5 1 ALT1 BIDIR>;
176						scl = <&pio5 0 ALT1 BIDIR>;
177					};
178				};
179			};
180
181			keyscan {
182				pinctrl_keyscan: keyscan {
183					st,pins {
184						keyin0 = <&pio4 0 ALT6 IN>;
185						keyin1 = <&pio4 5 ALT4 IN>;
186						keyin2 = <&pio0 4 ALT2 IN>;
187						keyin3 = <&pio2 6 ALT2 IN>;
188
189						keyout0 = <&pio4 6 ALT4 OUT>;
190						keyout1 = <&pio1 7 ALT2 OUT>;
191						keyout2 = <&pio0 6 ALT2 OUT>;
192						keyout3 = <&pio2 7 ALT2 OUT>;
193					};
194				};
195			};
196
197			gmac1 {
198				/*
199				 * Almost all the boards based on STiH407 SoC have an embedded
200				 * switch where the mdio/mdc have been used for managing the SMI
201				 * iface via I2C. For this reason these lines can be allocated
202				 * by using dedicated configuration (in case of there will be a
203				 * standard PHY transceiver on-board).
204				 */
205				pinctrl_rgmii1: rgmii1-0 {
206					st,pins {
207
208						txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
209						txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
210						txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
211						txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
212						txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
213						txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
214						rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
215						rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
216						rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
217						rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
218						rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
219						rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
220						clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
221						phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>;
222					};
223				};
224
225				pinctrl_rgmii1_mdio: rgmii1-mdio {
226					st,pins {
227						mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
228						mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
229						mdint = <&pio1 3 ALT1 IN BYPASS 0>;
230					};
231				};
232
233				pinctrl_mii1: mii1 {
234					st,pins {
235						txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
236						txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
237						txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
238						txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
239						txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
240						txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
241						txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
242						col = <&pio0 7 ALT1 IN BYPASS 1000>;
243
244						mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
245						mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
246						crs = <&pio1 2 ALT1 IN BYPASS 1000>;
247						mdint = <&pio1 3 ALT1 IN BYPASS 0>;
248						rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
249						rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
250						rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
251						rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
252
253						rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
254						rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
255						rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
256						phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
257					};
258				};
259
260				pinctrl_rmii1: rmii1-0 {
261					st,pins {
262						txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
263						txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
264						txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
265						mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
266						mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
267						mdint = <&pio1 3 ALT1 IN BYPASS 0>;
268						rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>;
269						rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>;
270						rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>;
271						rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
272					};
273				};
274
275				pinctrl_rmii1_phyclk: rmii1_phyclk {
276					st,pins {
277						phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
278					};
279				};
280
281				pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext {
282					st,pins {
283						phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>;
284					};
285				};
286			};
287
288			pwm1 {
289				pinctrl_pwm1_chan0_default: pwm1-0-default {
290					st,pins {
291						pwm-out = <&pio3 0 ALT1 OUT>;
292					};
293				};
294				pinctrl_pwm1_chan1_default: pwm1-1-default {
295					st,pins {
296						pwm-out = <&pio4 4 ALT1 OUT>;
297					};
298				};
299				pinctrl_pwm1_chan2_default: pwm1-2-default {
300					st,pins {
301						pwm-out = <&pio4 6 ALT3 OUT>;
302					};
303				};
304				pinctrl_pwm1_chan3_default: pwm1-3-default {
305					st,pins {
306						pwm-out = <&pio4 7 ALT3 OUT>;
307					};
308				};
309			};
310
311			spi10 {
312				pinctrl_spi10_default: spi10-4w-alt1-0 {
313					st,pins {
314						mtsr = <&pio4 6 ALT1 OUT>;
315						mrst = <&pio4 7 ALT1 IN>;
316						scl = <&pio4 5 ALT1 OUT>;
317					};
318				};
319
320				pinctrl_spi10_3w_alt1_0: spi10-3w-alt1-0 {
321					st,pins {
322						mtsr = <&pio4 6 ALT1 BIDIR_PU>;
323						scl = <&pio4 5 ALT1 OUT>;
324					};
325				};
326			};
327
328			spi11 {
329				pinctrl_spi11_default: spi11-4w-alt2-0 {
330					st,pins {
331						mtsr = <&pio3 1 ALT2 OUT>;
332						mrst = <&pio3 0 ALT2 IN>;
333						scl = <&pio3 2 ALT2 OUT>;
334					};
335				};
336
337				pinctrl_spi11_3w_alt2_0: spi11-3w-alt2-0 {
338					st,pins {
339						mtsr = <&pio3 1 ALT2 BIDIR_PU>;
340						scl = <&pio3 2 ALT2 OUT>;
341					};
342				};
343			};
344
345			spi12 {
346				pinctrl_spi12_default: spi12-4w-alt2-0 {
347					st,pins {
348						mtsr = <&pio3 6 ALT2 OUT>;
349						mrst = <&pio3 4 ALT2 IN>;
350						scl = <&pio3 7 ALT2 OUT>;
351					};
352				};
353
354				pinctrl_spi12_3w_alt2_0: spi12-3w-alt2-0 {
355					st,pins {
356						mtsr = <&pio3 6 ALT2 BIDIR_PU>;
357						scl = <&pio3 7 ALT2 OUT>;
358					};
359				};
360			};
361		};
362
363		pin-controller-front0 {
364			#address-cells = <1>;
365			#size-cells = <1>;
366			compatible = "st,stih407-front-pinctrl";
367			st,syscfg = <&syscfg_front>;
368			reg = <0x0920f080 0x4>;
369			reg-names = "irqmux";
370			interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>;
371			interrupt-names = "irqmux";
372			ranges = <0 0x09200000 0x10000>;
373
374			pio10: pio@09200000 {
375				gpio-controller;
376				#gpio-cells = <1>;
377				interrupt-controller;
378				#interrupt-cells = <2>;
379				reg = <0x0 0x100>;
380				st,bank-name = "PIO10";
381			};
382			pio11: pio@09201000 {
383				gpio-controller;
384				#gpio-cells = <1>;
385				interrupt-controller;
386				#interrupt-cells = <2>;
387				reg = <0x1000 0x100>;
388				st,bank-name = "PIO11";
389			};
390			pio12: pio@09202000 {
391				gpio-controller;
392				#gpio-cells = <1>;
393				interrupt-controller;
394				#interrupt-cells = <2>;
395				reg = <0x2000 0x100>;
396				st,bank-name = "PIO12";
397			};
398			pio13: pio@09203000 {
399				gpio-controller;
400				#gpio-cells = <1>;
401				interrupt-controller;
402				#interrupt-cells = <2>;
403				reg = <0x3000 0x100>;
404				st,bank-name = "PIO13";
405			};
406			pio14: pio@09204000 {
407				gpio-controller;
408				#gpio-cells = <1>;
409				interrupt-controller;
410				#interrupt-cells = <2>;
411				reg = <0x4000 0x100>;
412				st,bank-name = "PIO14";
413			};
414			pio15: pio@09205000 {
415				gpio-controller;
416				#gpio-cells = <1>;
417				interrupt-controller;
418				#interrupt-cells = <2>;
419				reg = <0x5000 0x100>;
420				st,bank-name = "PIO15";
421			};
422			pio16: pio@09206000 {
423				gpio-controller;
424				#gpio-cells = <1>;
425				interrupt-controller;
426				#interrupt-cells = <2>;
427				reg = <0x6000 0x100>;
428				st,bank-name = "PIO16";
429			};
430			pio17: pio@09207000 {
431				gpio-controller;
432				#gpio-cells = <1>;
433				interrupt-controller;
434				#interrupt-cells = <2>;
435				reg = <0x7000 0x100>;
436				st,bank-name = "PIO17";
437			};
438			pio18: pio@09208000 {
439				gpio-controller;
440				#gpio-cells = <1>;
441				interrupt-controller;
442				#interrupt-cells = <2>;
443				reg = <0x8000 0x100>;
444				st,bank-name = "PIO18";
445			};
446			pio19: pio@09209000 {
447				gpio-controller;
448				#gpio-cells = <1>;
449				interrupt-controller;
450				#interrupt-cells = <2>;
451				reg = <0x9000 0x100>;
452				st,bank-name = "PIO19";
453			};
454
455			/* Comms */
456			serial0 {
457				pinctrl_serial0: serial0-0 {
458					st,pins {
459						tx = <&pio17 0 ALT1 OUT>;
460						rx = <&pio17 1 ALT1 IN>;
461					};
462				};
463			};
464
465			serial1 {
466				pinctrl_serial1: serial1-0 {
467					st,pins {
468						tx = <&pio16 0 ALT1 OUT>;
469						rx = <&pio16 1 ALT1 IN>;
470					};
471				};
472			};
473
474			serial2 {
475				pinctrl_serial2: serial2-0 {
476					st,pins {
477						tx = <&pio15 0 ALT1 OUT>;
478						rx = <&pio15 1 ALT1 IN>;
479					};
480				};
481			};
482
483			mmc1 {
484				pinctrl_sd1: sd1-0 {
485					st,pins {
486						sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
487						sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
488						sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
489						sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
490						sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
491						sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
492						sd_led = <&pio16 6 ALT6 OUT>;
493						sd_pwren = <&pio16 7 ALT6 OUT>;
494						sd_cd = <&pio19 0 ALT6 IN>;
495						sd_wp = <&pio19 1 ALT6 IN>;
496					};
497				};
498			};
499
500
501			i2c0 {
502				pinctrl_i2c0_default: i2c0-default {
503					st,pins {
504						sda = <&pio10 6 ALT2 BIDIR>;
505						scl = <&pio10 5 ALT2 BIDIR>;
506					};
507				};
508			};
509
510			i2c1 {
511				pinctrl_i2c1_default: i2c1-default {
512					st,pins {
513						sda = <&pio11 1 ALT2 BIDIR>;
514						scl = <&pio11 0 ALT2 BIDIR>;
515					};
516				};
517			};
518
519			i2c2 {
520				pinctrl_i2c2_default: i2c2-default {
521					st,pins {
522						sda = <&pio15 6 ALT2 BIDIR>;
523						scl = <&pio15 5 ALT2 BIDIR>;
524					};
525				};
526			};
527
528			i2c3 {
529				pinctrl_i2c3_default: i2c3-alt1-0 {
530					st,pins {
531						sda = <&pio18 6 ALT1 BIDIR>;
532						scl = <&pio18 5 ALT1 BIDIR>;
533					};
534				};
535				pinctrl_i2c3_alt1_1: i2c3-alt1-1 {
536					st,pins {
537						sda = <&pio17 7 ALT1 BIDIR>;
538						scl = <&pio17 6 ALT1 BIDIR>;
539					};
540				};
541				pinctrl_i2c3_alt3_0: i2c3-alt3-0 {
542					st,pins {
543						sda = <&pio13 6 ALT3 BIDIR>;
544						scl = <&pio13 5 ALT3 BIDIR>;
545					};
546				};
547			};
548
549			spi0 {
550				pinctrl_spi0_default: spi0-4w-alt2-0 {
551					st,pins {
552						mtsr = <&pio10 6 ALT2 OUT>;
553						mrst = <&pio10 7 ALT2 IN>;
554						scl = <&pio10 5 ALT2 OUT>;
555					};
556				};
557
558				pinctrl_spi0_3w_alt2_0: spi0-3w-alt2-0 {
559					st,pins {
560						mtsr = <&pio10 6 ALT2 BIDIR_PU>;
561						scl = <&pio10 5 ALT2 OUT>;
562					};
563				};
564
565				pinctrl_spi0_4w_alt1_0: spi0-4w-alt1-0 {
566					st,pins {
567						mtsr = <&pio19 7 ALT1 OUT>;
568						mrst = <&pio19 5 ALT1 IN>;
569						scl = <&pio19 6 ALT1 OUT>;
570					};
571				};
572
573				pinctrl_spi0_3w_alt1_0: spi0-3w-alt1-0 {
574					st,pins {
575						mtsr = <&pio19 7 ALT1 BIDIR_PU>;
576						scl = <&pio19 6 ALT1 OUT>;
577					};
578				};
579			};
580
581			spi1 {
582				pinctrl_spi1_default: spi1-4w-alt2-0 {
583					st,pins {
584						mtsr = <&pio11 1 ALT2 OUT>;
585						mrst = <&pio11 2 ALT2 IN>;
586						scl = <&pio11 0 ALT2 OUT>;
587					};
588				};
589
590				pinctrl_spi1_3w_alt2_0: spi1-3w-alt2-0 {
591					st,pins {
592						mtsr = <&pio11 1 ALT2 BIDIR_PU>;
593						scl = <&pio11 0 ALT2 OUT>;
594					};
595				};
596
597				pinctrl_spi1_4w_alt1_0: spi1-4w-alt1-0 {
598					st,pins {
599						mtsr = <&pio14 3 ALT1 OUT>;
600						mrst = <&pio14 4 ALT1 IN>;
601						scl = <&pio14 2 ALT1 OUT>;
602					};
603				};
604
605				pinctrl_spi1_3w_alt1_0: spi1-3w-alt1-0 {
606					st,pins {
607						mtsr = <&pio14 3 ALT1 BIDIR_PU>;
608						scl = <&pio14 2 ALT1 OUT>;
609					};
610				};
611			};
612
613			spi2 {
614				pinctrl_spi2_default: spi2-4w-alt2-0 {
615					st,pins {
616						mtsr = <&pio12 6 ALT2 OUT>;
617						mrst = <&pio12 7 ALT2 IN>;
618						scl = <&pio12 5 ALT2 OUT>;
619					};
620				};
621
622				pinctrl_spi2_3w_alt2_0: spi2-3w-alt2-0 {
623					st,pins {
624						mtsr = <&pio12 6 ALT2 BIDIR_PU>;
625						scl = <&pio12 5 ALT2 OUT>;
626					};
627				};
628
629				pinctrl_spi2_4w_alt1_0: spi2-4w-alt1-0 {
630					st,pins {
631						mtsr = <&pio14 6 ALT1 OUT>;
632						mrst = <&pio14 7 ALT1 IN>;
633						scl = <&pio14 5 ALT1 OUT>;
634					};
635				};
636
637				pinctrl_spi2_3w_alt1_0: spi2-3w-alt1-0 {
638					st,pins {
639						mtsr = <&pio14 6 ALT1 BIDIR_PU>;
640						scl = <&pio14 5 ALT1 OUT>;
641					};
642				};
643
644				pinctrl_spi2_4w_alt2_1: spi2-4w-alt2-1 {
645					st,pins {
646						mtsr = <&pio15 6 ALT2 OUT>;
647						mrst = <&pio15 7 ALT2 IN>;
648						scl = <&pio15 5 ALT2 OUT>;
649					};
650				};
651
652				pinctrl_spi2_3w_alt2_1: spi2-3w-alt2-1 {
653					st,pins {
654						mtsr = <&pio15 6 ALT2 BIDIR_PU>;
655						scl = <&pio15 5 ALT2 OUT>;
656					};
657				};
658			};
659
660			spi3 {
661				pinctrl_spi3_default: spi3-4w-alt3-0 {
662					st,pins {
663						mtsr = <&pio13 6 ALT3 OUT>;
664						mrst = <&pio13 7 ALT3 IN>;
665						scl = <&pio13 5 ALT3 OUT>;
666					};
667				};
668
669				pinctrl_spi3_3w_alt3_0: spi3-3w-alt3-0 {
670					st,pins {
671						mtsr = <&pio13 6 ALT3 BIDIR_PU>;
672						scl = <&pio13 5 ALT3 OUT>;
673					};
674				};
675
676				pinctrl_spi3_4w_alt1_0: spi3-4w-alt1-0 {
677					st,pins {
678						mtsr = <&pio17 7 ALT1 OUT>;
679						mrst = <&pio17 5 ALT1 IN>;
680						scl = <&pio17 6 ALT1 OUT>;
681					};
682				};
683
684				pinctrl_spi3_3w_alt1_0: spi3-3w-alt1-0 {
685					st,pins {
686						mtsr = <&pio17 7 ALT1 BIDIR_PU>;
687						scl = <&pio17 6 ALT1 OUT>;
688					};
689				};
690
691				pinctrl_spi3_4w_alt1_1: spi3-4w-alt1-1 {
692					st,pins {
693						mtsr = <&pio18 6 ALT1 OUT>;
694						mrst = <&pio18 7 ALT1 IN>;
695						scl = <&pio18 5 ALT1 OUT>;
696					};
697				};
698
699				pinctrl_spi3_3w_alt1_1: spi3-3w-alt1-1 {
700					st,pins {
701						mtsr = <&pio18 6 ALT1 BIDIR_PU>;
702						scl = <&pio18 5 ALT1 OUT>;
703					};
704				};
705			};
706
707			tsin0 {
708				pinctrl_tsin0_parallel: tsin0_parallel {
709					st,pins {
710						DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
711						DATA6 = <&pio10 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
712						DATA5 = <&pio10 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
713						DATA4 = <&pio10 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
714						DATA3 = <&pio11 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
715						DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
716						DATA1 = <&pio11 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
717						DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
718						CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
719						VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
720						ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
721						PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
722					};
723				};
724				pinctrl_tsin0_serial: tsin0_serial {
725					st,pins {
726						DATA7 = <&pio10 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
727						CLKIN = <&pio10 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
728						VALID = <&pio10 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
729						ERROR = <&pio10 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
730						PKCLK = <&pio10 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
731					};
732				};
733			};
734
735			tsin1 {
736				pinctrl_tsin1_parallel: tsin1_parallel {
737					st,pins {
738						DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
739						DATA6 = <&pio12 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
740						DATA5 = <&pio12 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
741						DATA4 = <&pio12 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
742						DATA3 = <&pio12 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
743						DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
744						DATA1 = <&pio12 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
745						DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
746						CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
747						VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
748						ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
749						PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
750					};
751				};
752				pinctrl_tsin1_serial: tsin1_serial {
753					st,pins {
754						DATA7 = <&pio12 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
755						CLKIN = <&pio11 7 ALT1 IN CLKNOTDATA 0 CLK_A>;
756						VALID = <&pio11 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
757						ERROR = <&pio11 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
758						PKCLK = <&pio11 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
759					};
760				};
761			};
762
763			tsin2 {
764				pinctrl_tsin2_parallel: tsin2_parallel {
765					st,pins {
766						DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
767						DATA6 = <&pio13 5 ALT2 IN SE_NICLK_IO 0 CLK_B>;
768						DATA5 = <&pio13 6 ALT2 IN SE_NICLK_IO 0 CLK_B>;
769						DATA4 = <&pio13 7 ALT2 IN SE_NICLK_IO 0 CLK_B>;
770						DATA3 = <&pio14 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
771						DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;
772						DATA1 = <&pio14 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
773						DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
774						CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
775						VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
776						ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
777						PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
778					};
779				};
780				pinctrl_tsin2_serial: tsin2_serial {
781					st,pins {
782						DATA7 = <&pio13 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
783						CLKIN = <&pio13 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
784						VALID = <&pio13 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
785						ERROR = <&pio13 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
786						PKCLK = <&pio13 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
787					};
788				};
789			};
790
791			tsin3 {
792				pinctrl_tsin3_serial: tsin3_serial {
793					st,pins {
794						DATA7 = <&pio14 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
795						CLKIN = <&pio14 0 ALT1 IN CLKNOTDATA 0 CLK_A>;
796						VALID = <&pio13 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
797						ERROR = <&pio13 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
798						PKCLK = <&pio13 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
799					};
800				};
801			};
802
803			tsin4 {
804				pinctrl_tsin4_serial_alt3: tsin4_serial_alt3 {
805					st,pins {
806						DATA7 = <&pio14 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
807						CLKIN = <&pio14 5 ALT3 IN CLKNOTDATA 0 CLK_A>;
808						VALID = <&pio14 3 ALT3 IN SE_NICLK_IO 0 CLK_B>;
809						ERROR = <&pio14 2 ALT3 IN SE_NICLK_IO 0 CLK_B>;
810						PKCLK = <&pio14 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
811					};
812				};
813			};
814
815			tsin5 {
816				pinctrl_tsin5_serial_alt1: tsin5_serial_alt1 {
817					st,pins {
818						DATA7 = <&pio18 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
819						CLKIN = <&pio18 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
820						VALID = <&pio18 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
821						ERROR = <&pio18 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
822						PKCLK = <&pio18 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
823					};
824				};
825				pinctrl_tsin5_serial_alt2: tsin5_serial_alt2 {
826					st,pins {
827						DATA7 = <&pio19 4 ALT2 IN SE_NICLK_IO 0 CLK_A>;
828						CLKIN = <&pio19 3 ALT2 IN CLKNOTDATA 0 CLK_A>;
829						VALID = <&pio19 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
830						ERROR = <&pio19 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
831						PKCLK = <&pio19 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
832					};
833				};
834			};
835
836			tsout0 {
837				pinctrl_tsout0_parallel: tsout0_parallel {
838					st,pins {
839						DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
840						DATA6 = <&pio12 1 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
841						DATA5 = <&pio12 2 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
842						DATA4 = <&pio12 3 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
843						DATA3 = <&pio12 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
844						DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
845						DATA1 = <&pio12 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
846						DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
847						CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
848						VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
849						ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
850						PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
851					};
852				};
853				pinctrl_tsout0_serial: tsout0_serial {
854					st,pins {
855						DATA7 = <&pio12 0 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
856						CLKIN = <&pio11 7 ALT3 OUT NICLK 0 CLK_A>;
857						VALID = <&pio11 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
858						ERROR = <&pio11 4 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
859						PKCLK = <&pio11 6 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
860					};
861				};
862			};
863
864			tsout1 {
865				pinctrl_tsout1_serial: tsout1_serial {
866					st,pins {
867						DATA7 = <&pio19 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
868						CLKIN = <&pio19 3 ALT1 OUT NICLK 0 CLK_A>;
869						VALID = <&pio19 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
870						ERROR = <&pio19 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
871						PKCLK = <&pio19 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
872					};
873				};
874			};
875
876			mtsin0 {
877				pinctrl_mtsin0_parallel: mtsin0_parallel {
878					st,pins {
879						DATA7 = <&pio10 4 ALT3 IN SE_NICLK_IO 0 CLK_A>;
880						DATA6 = <&pio10 5 ALT3 IN SE_NICLK_IO 0 CLK_A>;
881						DATA5 = <&pio10 6 ALT3 IN SE_NICLK_IO 0 CLK_A>;
882						DATA4 = <&pio10 7 ALT3 IN SE_NICLK_IO 0 CLK_A>;
883						DATA3 = <&pio11 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
884						DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
885						DATA1 = <&pio11 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
886						DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>;
887						CLKIN = <&pio10 3 ALT3 IN CLKNOTDATA 0 CLK_A>;
888						VALID = <&pio10 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
889						ERROR = <&pio10 0 ALT3 IN SE_NICLK_IO 0 CLK_A>;
890						PKCLK = <&pio10 2 ALT3 IN SE_NICLK_IO 0 CLK_A>;
891					};
892				};
893			};
894
895			systrace {
896				pinctrl_systrace_default: systrace-default {
897					st,pins {
898						trc_data0 = <&pio11 3 ALT5 OUT>;
899						trc_data1 = <&pio11 4 ALT5 OUT>;
900						trc_data2 = <&pio11 5 ALT5 OUT>;
901						trc_data3 = <&pio11 6 ALT5 OUT>;
902						trc_clk   = <&pio11 7 ALT5 OUT>;
903					};
904				};
905			};
906		};
907
908		pin-controller-front1 {
909			#address-cells = <1>;
910			#size-cells = <1>;
911			compatible = "st,stih407-front-pinctrl";
912			st,syscfg = <&syscfg_front>;
913			reg = <0x0921f080 0x4>;
914			reg-names = "irqmux";
915			interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
916			interrupt-names = "irqmux";
917			ranges = <0 0x09210000 0x10000>;
918
919			tsin4 {
920				pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 {
921					st,pins {
922						DATA7 = <&pio20 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
923						CLKIN = <&pio20 3 ALT1 IN CLKNOTDATA 0 CLK_A>;
924						VALID = <&pio20 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
925						ERROR = <&pio20 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
926						PKCLK = <&pio20 2 ALT1 IN SE_NICLK_IO 0 CLK_A>;
927					};
928				};
929			};
930
931			pio20: pio@09210000 {
932				gpio-controller;
933				#gpio-cells = <1>;
934				interrupt-controller;
935				#interrupt-cells = <2>;
936				reg = <0x0 0x100>;
937				st,bank-name = "PIO20";
938			};
939		};
940
941		pin-controller-rear {
942			#address-cells = <1>;
943			#size-cells = <1>;
944			compatible = "st,stih407-rear-pinctrl";
945			st,syscfg = <&syscfg_rear>;
946			reg = <0x0922f080 0x4>;
947			reg-names = "irqmux";
948			interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>;
949			interrupt-names = "irqmux";
950			ranges = <0 0x09220000 0x6000>;
951
952			pio30: gpio@09220000 {
953				gpio-controller;
954				#gpio-cells = <1>;
955				interrupt-controller;
956				#interrupt-cells = <2>;
957				reg = <0x0 0x100>;
958				st,bank-name = "PIO30";
959			};
960			pio31: gpio@09221000 {
961				gpio-controller;
962				#gpio-cells = <1>;
963				interrupt-controller;
964				#interrupt-cells = <2>;
965				reg = <0x1000 0x100>;
966				st,bank-name = "PIO31";
967			};
968			pio32: gpio@09222000 {
969				gpio-controller;
970				#gpio-cells = <1>;
971				interrupt-controller;
972				#interrupt-cells = <2>;
973				reg = <0x2000 0x100>;
974				st,bank-name = "PIO32";
975			};
976			pio33: gpio@09223000 {
977				gpio-controller;
978				#gpio-cells = <1>;
979				interrupt-controller;
980				#interrupt-cells = <2>;
981				reg = <0x3000 0x100>;
982				st,bank-name = "PIO33";
983			};
984			pio34: gpio@09224000 {
985				gpio-controller;
986				#gpio-cells = <1>;
987				interrupt-controller;
988				#interrupt-cells = <2>;
989				reg = <0x4000 0x100>;
990				st,bank-name = "PIO34";
991			};
992			pio35: gpio@09225000 {
993				gpio-controller;
994				#gpio-cells = <1>;
995				interrupt-controller;
996				#interrupt-cells = <2>;
997				reg = <0x5000 0x100>;
998				st,bank-name = "PIO35";
999				st,retime-pin-mask = <0x7f>;
1000			};
1001
1002			i2c4 {
1003				pinctrl_i2c4_default: i2c4-default {
1004					st,pins {
1005						sda = <&pio30 1 ALT1 BIDIR>;
1006						scl = <&pio30 0 ALT1 BIDIR>;
1007					};
1008				};
1009			};
1010
1011			i2c5 {
1012				pinctrl_i2c5_default: i2c5-default {
1013					st,pins {
1014						sda = <&pio34 4 ALT1 BIDIR>;
1015						scl = <&pio34 3 ALT1 BIDIR>;
1016					};
1017				};
1018			};
1019
1020			usb3 {
1021				pinctrl_usb3: usb3-2 {
1022					st,pins {
1023						usb-oc-detect = <&pio35 4 ALT1 IN>;
1024						usb-pwr-enable = <&pio35 5 ALT1 OUT>;
1025						usb-vbus-valid = <&pio35 6 ALT1 IN>;
1026					};
1027				};
1028			};
1029
1030			pwm0 {
1031				pinctrl_pwm0_chan0_default: pwm0-0-default {
1032					st,pins {
1033						pwm-out = <&pio31 1 ALT1 OUT>;
1034					};
1035				};
1036			};
1037
1038			spi4 {
1039				pinctrl_spi4_default: spi4-4w-alt1-0 {
1040					st,pins {
1041						mtsr = <&pio30 1 ALT1 OUT>;
1042						mrst = <&pio30 2 ALT1 IN>;
1043						scl = <&pio30 0 ALT1 OUT>;
1044					};
1045				};
1046
1047				pinctrl_spi4_3w_alt1_0: spi4-3w-alt1-0 {
1048					st,pins {
1049						mtsr = <&pio30 1 ALT1 BIDIR_PU>;
1050						scl = <&pio30 0 ALT1 OUT>;
1051					};
1052				};
1053
1054				pinctrl_spi4_4w_alt3_0: spi4-4w-alt3-0 {
1055					st,pins {
1056						mtsr = <&pio34 1 ALT3 OUT>;
1057						mrst = <&pio34 2 ALT3 IN>;
1058						scl = <&pio34 0 ALT3 OUT>;
1059					};
1060				};
1061
1062				pinctrl_spi4_3w_alt3_0: spi4-3w-alt3-0 {
1063					st,pins {
1064						mtsr = <&pio34 1 ALT3 BIDIR_PU>;
1065						scl = <&pio34 0 ALT3 OUT>;
1066					};
1067				};
1068			};
1069
1070			serial3 {
1071				pinctrl_serial3: serial3-0 {
1072					st,pins {
1073						tx = <&pio31 3 ALT1 OUT>;
1074						rx = <&pio31 4 ALT1 IN>;
1075					};
1076				};
1077			};
1078		};
1079
1080		pin-controller-flash {
1081			#address-cells = <1>;
1082			#size-cells = <1>;
1083			compatible = "st,stih407-flash-pinctrl";
1084			st,syscfg = <&syscfg_flash>;
1085			reg = <0x0923f080 0x4>;
1086			reg-names = "irqmux";
1087			interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>;
1088			interrupts-names = "irqmux";
1089			ranges = <0 0x09230000 0x3000>;
1090
1091			pio40: gpio@09230000 {
1092				gpio-controller;
1093				#gpio-cells = <1>;
1094				interrupt-controller;
1095				#interrupt-cells = <2>;
1096				reg = <0 0x100>;
1097				st,bank-name = "PIO40";
1098			};
1099			pio41: gpio@09231000 {
1100				gpio-controller;
1101				#gpio-cells = <1>;
1102				interrupt-controller;
1103				#interrupt-cells = <2>;
1104				reg = <0x1000 0x100>;
1105				st,bank-name = "PIO41";
1106			};
1107			pio42: gpio@09232000 {
1108				gpio-controller;
1109				#gpio-cells = <1>;
1110				interrupt-controller;
1111				#interrupt-cells = <2>;
1112				reg = <0x2000 0x100>;
1113				st,bank-name = "PIO42";
1114			};
1115
1116			mmc0 {
1117				pinctrl_mmc0: mmc0-0 {
1118					st,pins {
1119						emmc_clk = <&pio40 6 ALT1 BIDIR>;
1120						emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
1121						emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
1122						emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
1123						emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
1124						emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
1125						emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
1126						emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
1127						emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
1128						emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
1129					};
1130				};
1131				pinctrl_sd0: sd0-0 {
1132					st,pins {
1133						sd_clk = <&pio40 6 ALT1 BIDIR>;
1134						sd_cmd = <&pio40 7 ALT1 BIDIR_PU>;
1135						sd_dat0 = <&pio41 0 ALT1 BIDIR_PU>;
1136						sd_dat1 = <&pio41 1 ALT1 BIDIR_PU>;
1137						sd_dat2 = <&pio41 2 ALT1 BIDIR_PU>;
1138						sd_dat3 = <&pio41 3 ALT1 BIDIR_PU>;
1139						sd_led = <&pio42 0 ALT2 OUT>;
1140						sd_pwren = <&pio42 2 ALT2 OUT>;
1141						sd_vsel = <&pio42 3 ALT2 OUT>;
1142						sd_cd = <&pio42 4 ALT2 IN>;
1143						sd_wp = <&pio42 5 ALT2 IN>;
1144					};
1145				};
1146			};
1147
1148			fsm {
1149				pinctrl_fsm: fsm {
1150					st,pins {
1151						spi-fsm-clk = <&pio40 1 ALT1 OUT>;
1152						spi-fsm-cs = <&pio40 0 ALT1 OUT>;
1153						spi-fsm-mosi = <&pio40 2 ALT1 OUT>;
1154						spi-fsm-miso = <&pio40 3 ALT1 IN>;
1155						spi-fsm-hol = <&pio40 5 ALT1 OUT>;
1156						spi-fsm-wp = <&pio40 4 ALT1 OUT>;
1157					};
1158				};
1159			};
1160
1161			nand {
1162				pinctrl_nand: nand {
1163					st,pins {
1164						nand_cs1 = <&pio40 6 ALT3 OUT>;
1165						nand_cs0 = <&pio40 7 ALT3 OUT>;
1166						nand_d0 = <&pio41 0 ALT3 BIDIR>;
1167						nand_d1 = <&pio41 1 ALT3 BIDIR>;
1168						nand_d2 = <&pio41 2 ALT3 BIDIR>;
1169						nand_d3 = <&pio41 3 ALT3 BIDIR>;
1170						nand_d4 = <&pio41 4 ALT3 BIDIR>;
1171						nand_d5 = <&pio41 5 ALT3 BIDIR>;
1172						nand_d6 = <&pio41 6 ALT3 BIDIR>;
1173						nand_d7 = <&pio41 7 ALT3 BIDIR>;
1174						nand_we = <&pio42 0 ALT3 OUT>;
1175						nand_dqs = <&pio42 1 ALT3 OUT>;
1176						nand_ale = <&pio42 2 ALT3 OUT>;
1177						nand_cle = <&pio42 3 ALT3 OUT>;
1178						nand_rnb = <&pio42 4 ALT3 IN>;
1179						nand_oe = <&pio42 5 ALT3 OUT>;
1180					};
1181				};
1182			};
1183		};
1184	};
1185};
1186