1/* 2 * Device Tree Source for the r8a7791 SoC 3 * 4 * Copyright (C) 2013-2015 Renesas Electronics Corporation 5 * Copyright (C) 2013-2014 Renesas Solutions Corp. 6 * Copyright (C) 2014 Cogent Embedded Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 */ 12 13#include <dt-bindings/clock/r8a7791-clock.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16 17/ { 18 compatible = "renesas,r8a7791"; 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 i2c5 = &i2c5; 30 i2c6 = &i2c6; 31 i2c7 = &i2c7; 32 i2c8 = &i2c8; 33 spi0 = &qspi; 34 spi1 = &msiof0; 35 spi2 = &msiof1; 36 spi3 = &msiof2; 37 vin0 = &vin0; 38 vin1 = &vin1; 39 vin2 = &vin2; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 cpu0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a15"; 49 reg = <0>; 50 clock-frequency = <1500000000>; 51 voltage-tolerance = <1>; /* 1% */ 52 clocks = <&cpg_clocks R8A7791_CLK_Z>; 53 clock-latency = <300000>; /* 300 us */ 54 55 /* kHz - uV - OPPs unknown yet */ 56 operating-points = <1500000 1000000>, 57 <1312500 1000000>, 58 <1125000 1000000>, 59 < 937500 1000000>, 60 < 750000 1000000>, 61 < 375000 1000000>; 62 }; 63 64 cpu1: cpu@1 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a15"; 67 reg = <1>; 68 clock-frequency = <1500000000>; 69 }; 70 }; 71 72 gic: interrupt-controller@f1001000 { 73 compatible = "arm,gic-400"; 74 #interrupt-cells = <3>; 75 #address-cells = <0>; 76 interrupt-controller; 77 reg = <0 0xf1001000 0 0x1000>, 78 <0 0xf1002000 0 0x1000>, 79 <0 0xf1004000 0 0x2000>, 80 <0 0xf1006000 0 0x2000>; 81 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 82 }; 83 84 gpio0: gpio@e6050000 { 85 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 86 reg = <0 0xe6050000 0 0x50>; 87 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 88 #gpio-cells = <2>; 89 gpio-controller; 90 gpio-ranges = <&pfc 0 0 32>; 91 #interrupt-cells = <2>; 92 interrupt-controller; 93 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; 94 power-domains = <&cpg_clocks>; 95 }; 96 97 gpio1: gpio@e6051000 { 98 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 99 reg = <0 0xe6051000 0 0x50>; 100 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; 101 #gpio-cells = <2>; 102 gpio-controller; 103 gpio-ranges = <&pfc 0 32 32>; 104 #interrupt-cells = <2>; 105 interrupt-controller; 106 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; 107 power-domains = <&cpg_clocks>; 108 }; 109 110 gpio2: gpio@e6052000 { 111 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 112 reg = <0 0xe6052000 0 0x50>; 113 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 114 #gpio-cells = <2>; 115 gpio-controller; 116 gpio-ranges = <&pfc 0 64 32>; 117 #interrupt-cells = <2>; 118 interrupt-controller; 119 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; 120 power-domains = <&cpg_clocks>; 121 }; 122 123 gpio3: gpio@e6053000 { 124 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 125 reg = <0 0xe6053000 0 0x50>; 126 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 127 #gpio-cells = <2>; 128 gpio-controller; 129 gpio-ranges = <&pfc 0 96 32>; 130 #interrupt-cells = <2>; 131 interrupt-controller; 132 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; 133 power-domains = <&cpg_clocks>; 134 }; 135 136 gpio4: gpio@e6054000 { 137 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 138 reg = <0 0xe6054000 0 0x50>; 139 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 140 #gpio-cells = <2>; 141 gpio-controller; 142 gpio-ranges = <&pfc 0 128 32>; 143 #interrupt-cells = <2>; 144 interrupt-controller; 145 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; 146 power-domains = <&cpg_clocks>; 147 }; 148 149 gpio5: gpio@e6055000 { 150 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 151 reg = <0 0xe6055000 0 0x50>; 152 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 153 #gpio-cells = <2>; 154 gpio-controller; 155 gpio-ranges = <&pfc 0 160 32>; 156 #interrupt-cells = <2>; 157 interrupt-controller; 158 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; 159 power-domains = <&cpg_clocks>; 160 }; 161 162 gpio6: gpio@e6055400 { 163 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 164 reg = <0 0xe6055400 0 0x50>; 165 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 166 #gpio-cells = <2>; 167 gpio-controller; 168 gpio-ranges = <&pfc 0 192 32>; 169 #interrupt-cells = <2>; 170 interrupt-controller; 171 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; 172 power-domains = <&cpg_clocks>; 173 }; 174 175 gpio7: gpio@e6055800 { 176 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 177 reg = <0 0xe6055800 0 0x50>; 178 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 179 #gpio-cells = <2>; 180 gpio-controller; 181 gpio-ranges = <&pfc 0 224 26>; 182 #interrupt-cells = <2>; 183 interrupt-controller; 184 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; 185 power-domains = <&cpg_clocks>; 186 }; 187 188 thermal@e61f0000 { 189 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal"; 190 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; 191 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 192 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; 193 power-domains = <&cpg_clocks>; 194 }; 195 196 timer { 197 compatible = "arm,armv7-timer"; 198 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 199 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 200 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 201 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 202 }; 203 204 cmt0: timer@ffca0000 { 205 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; 206 reg = <0 0xffca0000 0 0x1004>; 207 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, 208 <0 143 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&mstp1_clks R8A7791_CLK_CMT0>; 210 clock-names = "fck"; 211 power-domains = <&cpg_clocks>; 212 213 renesas,channels-mask = <0x60>; 214 215 status = "disabled"; 216 }; 217 218 cmt1: timer@e6130000 { 219 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; 220 reg = <0 0xe6130000 0 0x1004>; 221 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, 222 <0 121 IRQ_TYPE_LEVEL_HIGH>, 223 <0 122 IRQ_TYPE_LEVEL_HIGH>, 224 <0 123 IRQ_TYPE_LEVEL_HIGH>, 225 <0 124 IRQ_TYPE_LEVEL_HIGH>, 226 <0 125 IRQ_TYPE_LEVEL_HIGH>, 227 <0 126 IRQ_TYPE_LEVEL_HIGH>, 228 <0 127 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&mstp3_clks R8A7791_CLK_CMT1>; 230 clock-names = "fck"; 231 power-domains = <&cpg_clocks>; 232 233 renesas,channels-mask = <0xff>; 234 235 status = "disabled"; 236 }; 237 238 irqc0: interrupt-controller@e61c0000 { 239 compatible = "renesas,irqc-r8a7791", "renesas,irqc"; 240 #interrupt-cells = <2>; 241 interrupt-controller; 242 reg = <0 0xe61c0000 0 0x200>; 243 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, 244 <0 1 IRQ_TYPE_LEVEL_HIGH>, 245 <0 2 IRQ_TYPE_LEVEL_HIGH>, 246 <0 3 IRQ_TYPE_LEVEL_HIGH>, 247 <0 12 IRQ_TYPE_LEVEL_HIGH>, 248 <0 13 IRQ_TYPE_LEVEL_HIGH>, 249 <0 14 IRQ_TYPE_LEVEL_HIGH>, 250 <0 15 IRQ_TYPE_LEVEL_HIGH>, 251 <0 16 IRQ_TYPE_LEVEL_HIGH>, 252 <0 17 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&mstp4_clks R8A7791_CLK_IRQC>; 254 power-domains = <&cpg_clocks>; 255 }; 256 257 dmac0: dma-controller@e6700000 { 258 compatible = "renesas,rcar-dmac"; 259 reg = <0 0xe6700000 0 0x20000>; 260 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH 261 0 200 IRQ_TYPE_LEVEL_HIGH 262 0 201 IRQ_TYPE_LEVEL_HIGH 263 0 202 IRQ_TYPE_LEVEL_HIGH 264 0 203 IRQ_TYPE_LEVEL_HIGH 265 0 204 IRQ_TYPE_LEVEL_HIGH 266 0 205 IRQ_TYPE_LEVEL_HIGH 267 0 206 IRQ_TYPE_LEVEL_HIGH 268 0 207 IRQ_TYPE_LEVEL_HIGH 269 0 208 IRQ_TYPE_LEVEL_HIGH 270 0 209 IRQ_TYPE_LEVEL_HIGH 271 0 210 IRQ_TYPE_LEVEL_HIGH 272 0 211 IRQ_TYPE_LEVEL_HIGH 273 0 212 IRQ_TYPE_LEVEL_HIGH 274 0 213 IRQ_TYPE_LEVEL_HIGH 275 0 214 IRQ_TYPE_LEVEL_HIGH>; 276 interrupt-names = "error", 277 "ch0", "ch1", "ch2", "ch3", 278 "ch4", "ch5", "ch6", "ch7", 279 "ch8", "ch9", "ch10", "ch11", 280 "ch12", "ch13", "ch14"; 281 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; 282 clock-names = "fck"; 283 power-domains = <&cpg_clocks>; 284 #dma-cells = <1>; 285 dma-channels = <15>; 286 }; 287 288 dmac1: dma-controller@e6720000 { 289 compatible = "renesas,rcar-dmac"; 290 reg = <0 0xe6720000 0 0x20000>; 291 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH 292 0 216 IRQ_TYPE_LEVEL_HIGH 293 0 217 IRQ_TYPE_LEVEL_HIGH 294 0 218 IRQ_TYPE_LEVEL_HIGH 295 0 219 IRQ_TYPE_LEVEL_HIGH 296 0 308 IRQ_TYPE_LEVEL_HIGH 297 0 309 IRQ_TYPE_LEVEL_HIGH 298 0 310 IRQ_TYPE_LEVEL_HIGH 299 0 311 IRQ_TYPE_LEVEL_HIGH 300 0 312 IRQ_TYPE_LEVEL_HIGH 301 0 313 IRQ_TYPE_LEVEL_HIGH 302 0 314 IRQ_TYPE_LEVEL_HIGH 303 0 315 IRQ_TYPE_LEVEL_HIGH 304 0 316 IRQ_TYPE_LEVEL_HIGH 305 0 317 IRQ_TYPE_LEVEL_HIGH 306 0 318 IRQ_TYPE_LEVEL_HIGH>; 307 interrupt-names = "error", 308 "ch0", "ch1", "ch2", "ch3", 309 "ch4", "ch5", "ch6", "ch7", 310 "ch8", "ch9", "ch10", "ch11", 311 "ch12", "ch13", "ch14"; 312 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; 313 clock-names = "fck"; 314 power-domains = <&cpg_clocks>; 315 #dma-cells = <1>; 316 dma-channels = <15>; 317 }; 318 319 audma0: dma-controller@ec700000 { 320 compatible = "renesas,rcar-dmac"; 321 reg = <0 0xec700000 0 0x10000>; 322 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH 323 0 320 IRQ_TYPE_LEVEL_HIGH 324 0 321 IRQ_TYPE_LEVEL_HIGH 325 0 322 IRQ_TYPE_LEVEL_HIGH 326 0 323 IRQ_TYPE_LEVEL_HIGH 327 0 324 IRQ_TYPE_LEVEL_HIGH 328 0 325 IRQ_TYPE_LEVEL_HIGH 329 0 326 IRQ_TYPE_LEVEL_HIGH 330 0 327 IRQ_TYPE_LEVEL_HIGH 331 0 328 IRQ_TYPE_LEVEL_HIGH 332 0 329 IRQ_TYPE_LEVEL_HIGH 333 0 330 IRQ_TYPE_LEVEL_HIGH 334 0 331 IRQ_TYPE_LEVEL_HIGH 335 0 332 IRQ_TYPE_LEVEL_HIGH>; 336 interrupt-names = "error", 337 "ch0", "ch1", "ch2", "ch3", 338 "ch4", "ch5", "ch6", "ch7", 339 "ch8", "ch9", "ch10", "ch11", 340 "ch12"; 341 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>; 342 clock-names = "fck"; 343 power-domains = <&cpg_clocks>; 344 #dma-cells = <1>; 345 dma-channels = <13>; 346 }; 347 348 audma1: dma-controller@ec720000 { 349 compatible = "renesas,rcar-dmac"; 350 reg = <0 0xec720000 0 0x10000>; 351 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH 352 0 333 IRQ_TYPE_LEVEL_HIGH 353 0 334 IRQ_TYPE_LEVEL_HIGH 354 0 335 IRQ_TYPE_LEVEL_HIGH 355 0 336 IRQ_TYPE_LEVEL_HIGH 356 0 337 IRQ_TYPE_LEVEL_HIGH 357 0 338 IRQ_TYPE_LEVEL_HIGH 358 0 339 IRQ_TYPE_LEVEL_HIGH 359 0 340 IRQ_TYPE_LEVEL_HIGH 360 0 341 IRQ_TYPE_LEVEL_HIGH 361 0 342 IRQ_TYPE_LEVEL_HIGH 362 0 343 IRQ_TYPE_LEVEL_HIGH 363 0 344 IRQ_TYPE_LEVEL_HIGH 364 0 345 IRQ_TYPE_LEVEL_HIGH>; 365 interrupt-names = "error", 366 "ch0", "ch1", "ch2", "ch3", 367 "ch4", "ch5", "ch6", "ch7", 368 "ch8", "ch9", "ch10", "ch11", 369 "ch12"; 370 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>; 371 clock-names = "fck"; 372 power-domains = <&cpg_clocks>; 373 #dma-cells = <1>; 374 dma-channels = <13>; 375 }; 376 377 usb_dmac0: dma-controller@e65a0000 { 378 compatible = "renesas,usb-dmac"; 379 reg = <0 0xe65a0000 0 0x100>; 380 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH 381 0 109 IRQ_TYPE_LEVEL_HIGH>; 382 interrupt-names = "ch0", "ch1"; 383 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>; 384 power-domains = <&cpg_clocks>; 385 #dma-cells = <1>; 386 dma-channels = <2>; 387 }; 388 389 usb_dmac1: dma-controller@e65b0000 { 390 compatible = "renesas,usb-dmac"; 391 reg = <0 0xe65b0000 0 0x100>; 392 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH 393 0 110 IRQ_TYPE_LEVEL_HIGH>; 394 interrupt-names = "ch0", "ch1"; 395 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>; 396 power-domains = <&cpg_clocks>; 397 #dma-cells = <1>; 398 dma-channels = <2>; 399 }; 400 401 /* The memory map in the User's Manual maps the cores to bus numbers */ 402 i2c0: i2c@e6508000 { 403 #address-cells = <1>; 404 #size-cells = <0>; 405 compatible = "renesas,i2c-r8a7791"; 406 reg = <0 0xe6508000 0 0x40>; 407 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&mstp9_clks R8A7791_CLK_I2C0>; 409 power-domains = <&cpg_clocks>; 410 status = "disabled"; 411 }; 412 413 i2c1: i2c@e6518000 { 414 #address-cells = <1>; 415 #size-cells = <0>; 416 compatible = "renesas,i2c-r8a7791"; 417 reg = <0 0xe6518000 0 0x40>; 418 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&mstp9_clks R8A7791_CLK_I2C1>; 420 power-domains = <&cpg_clocks>; 421 status = "disabled"; 422 }; 423 424 i2c2: i2c@e6530000 { 425 #address-cells = <1>; 426 #size-cells = <0>; 427 compatible = "renesas,i2c-r8a7791"; 428 reg = <0 0xe6530000 0 0x40>; 429 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&mstp9_clks R8A7791_CLK_I2C2>; 431 power-domains = <&cpg_clocks>; 432 status = "disabled"; 433 }; 434 435 i2c3: i2c@e6540000 { 436 #address-cells = <1>; 437 #size-cells = <0>; 438 compatible = "renesas,i2c-r8a7791"; 439 reg = <0 0xe6540000 0 0x40>; 440 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&mstp9_clks R8A7791_CLK_I2C3>; 442 power-domains = <&cpg_clocks>; 443 status = "disabled"; 444 }; 445 446 i2c4: i2c@e6520000 { 447 #address-cells = <1>; 448 #size-cells = <0>; 449 compatible = "renesas,i2c-r8a7791"; 450 reg = <0 0xe6520000 0 0x40>; 451 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&mstp9_clks R8A7791_CLK_I2C4>; 453 power-domains = <&cpg_clocks>; 454 status = "disabled"; 455 }; 456 457 i2c5: i2c@e6528000 { 458 /* doesn't need pinmux */ 459 #address-cells = <1>; 460 #size-cells = <0>; 461 compatible = "renesas,i2c-r8a7791"; 462 reg = <0 0xe6528000 0 0x40>; 463 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&mstp9_clks R8A7791_CLK_I2C5>; 465 power-domains = <&cpg_clocks>; 466 status = "disabled"; 467 }; 468 469 i2c6: i2c@e60b0000 { 470 /* doesn't need pinmux */ 471 #address-cells = <1>; 472 #size-cells = <0>; 473 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; 474 reg = <0 0xe60b0000 0 0x425>; 475 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; 477 dmas = <&dmac0 0x77>, <&dmac0 0x78>; 478 dma-names = "tx", "rx"; 479 power-domains = <&cpg_clocks>; 480 status = "disabled"; 481 }; 482 483 i2c7: i2c@e6500000 { 484 #address-cells = <1>; 485 #size-cells = <0>; 486 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; 487 reg = <0 0xe6500000 0 0x425>; 488 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&mstp3_clks R8A7791_CLK_IIC0>; 490 dmas = <&dmac0 0x61>, <&dmac0 0x62>; 491 dma-names = "tx", "rx"; 492 power-domains = <&cpg_clocks>; 493 status = "disabled"; 494 }; 495 496 i2c8: i2c@e6510000 { 497 #address-cells = <1>; 498 #size-cells = <0>; 499 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; 500 reg = <0 0xe6510000 0 0x425>; 501 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&mstp3_clks R8A7791_CLK_IIC1>; 503 dmas = <&dmac0 0x65>, <&dmac0 0x66>; 504 dma-names = "tx", "rx"; 505 power-domains = <&cpg_clocks>; 506 status = "disabled"; 507 }; 508 509 pfc: pfc@e6060000 { 510 compatible = "renesas,pfc-r8a7791"; 511 reg = <0 0xe6060000 0 0x250>; 512 #gpio-range-cells = <3>; 513 }; 514 515 mmcif0: mmc@ee200000 { 516 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif"; 517 reg = <0 0xee200000 0 0x80>; 518 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; 520 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; 521 dma-names = "tx", "rx"; 522 power-domains = <&cpg_clocks>; 523 reg-io-width = <4>; 524 status = "disabled"; 525 max-frequency = <97500000>; 526 }; 527 528 sdhi0: sd@ee100000 { 529 compatible = "renesas,sdhi-r8a7791"; 530 reg = <0 0xee100000 0 0x328>; 531 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; 533 dmas = <&dmac1 0xcd>, <&dmac1 0xce>; 534 dma-names = "tx", "rx"; 535 power-domains = <&cpg_clocks>; 536 status = "disabled"; 537 }; 538 539 sdhi1: sd@ee140000 { 540 compatible = "renesas,sdhi-r8a7791"; 541 reg = <0 0xee140000 0 0x100>; 542 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; 544 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; 545 dma-names = "tx", "rx"; 546 power-domains = <&cpg_clocks>; 547 status = "disabled"; 548 }; 549 550 sdhi2: sd@ee160000 { 551 compatible = "renesas,sdhi-r8a7791"; 552 reg = <0 0xee160000 0 0x100>; 553 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; 555 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; 556 dma-names = "tx", "rx"; 557 power-domains = <&cpg_clocks>; 558 status = "disabled"; 559 }; 560 561 scifa0: serial@e6c40000 { 562 compatible = "renesas,scifa-r8a7791", "renesas,scifa"; 563 reg = <0 0xe6c40000 0 64>; 564 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; 566 clock-names = "sci_ick"; 567 dmas = <&dmac0 0x21>, <&dmac0 0x22>; 568 dma-names = "tx", "rx"; 569 power-domains = <&cpg_clocks>; 570 status = "disabled"; 571 }; 572 573 scifa1: serial@e6c50000 { 574 compatible = "renesas,scifa-r8a7791", "renesas,scifa"; 575 reg = <0 0xe6c50000 0 64>; 576 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; 578 clock-names = "sci_ick"; 579 dmas = <&dmac0 0x25>, <&dmac0 0x26>; 580 dma-names = "tx", "rx"; 581 power-domains = <&cpg_clocks>; 582 status = "disabled"; 583 }; 584 585 scifa2: serial@e6c60000 { 586 compatible = "renesas,scifa-r8a7791", "renesas,scifa"; 587 reg = <0 0xe6c60000 0 64>; 588 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; 590 clock-names = "sci_ick"; 591 dmas = <&dmac0 0x27>, <&dmac0 0x28>; 592 dma-names = "tx", "rx"; 593 power-domains = <&cpg_clocks>; 594 status = "disabled"; 595 }; 596 597 scifa3: serial@e6c70000 { 598 compatible = "renesas,scifa-r8a7791", "renesas,scifa"; 599 reg = <0 0xe6c70000 0 64>; 600 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; 602 clock-names = "sci_ick"; 603 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>; 604 dma-names = "tx", "rx"; 605 power-domains = <&cpg_clocks>; 606 status = "disabled"; 607 }; 608 609 scifa4: serial@e6c78000 { 610 compatible = "renesas,scifa-r8a7791", "renesas,scifa"; 611 reg = <0 0xe6c78000 0 64>; 612 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; 614 clock-names = "sci_ick"; 615 dmas = <&dmac0 0x1f>, <&dmac0 0x20>; 616 dma-names = "tx", "rx"; 617 power-domains = <&cpg_clocks>; 618 status = "disabled"; 619 }; 620 621 scifa5: serial@e6c80000 { 622 compatible = "renesas,scifa-r8a7791", "renesas,scifa"; 623 reg = <0 0xe6c80000 0 64>; 624 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; 626 clock-names = "sci_ick"; 627 dmas = <&dmac0 0x23>, <&dmac0 0x24>; 628 dma-names = "tx", "rx"; 629 power-domains = <&cpg_clocks>; 630 status = "disabled"; 631 }; 632 633 scifb0: serial@e6c20000 { 634 compatible = "renesas,scifb-r8a7791", "renesas,scifb"; 635 reg = <0 0xe6c20000 0 64>; 636 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; 638 clock-names = "sci_ick"; 639 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>; 640 dma-names = "tx", "rx"; 641 power-domains = <&cpg_clocks>; 642 status = "disabled"; 643 }; 644 645 scifb1: serial@e6c30000 { 646 compatible = "renesas,scifb-r8a7791", "renesas,scifb"; 647 reg = <0 0xe6c30000 0 64>; 648 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; 650 clock-names = "sci_ick"; 651 dmas = <&dmac0 0x19>, <&dmac0 0x1a>; 652 dma-names = "tx", "rx"; 653 power-domains = <&cpg_clocks>; 654 status = "disabled"; 655 }; 656 657 scifb2: serial@e6ce0000 { 658 compatible = "renesas,scifb-r8a7791", "renesas,scifb"; 659 reg = <0 0xe6ce0000 0 64>; 660 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; 662 clock-names = "sci_ick"; 663 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>; 664 dma-names = "tx", "rx"; 665 power-domains = <&cpg_clocks>; 666 status = "disabled"; 667 }; 668 669 scif0: serial@e6e60000 { 670 compatible = "renesas,scif-r8a7791", "renesas,scif"; 671 reg = <0 0xe6e60000 0 64>; 672 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>; 674 clock-names = "sci_ick"; 675 dmas = <&dmac0 0x29>, <&dmac0 0x2a>; 676 dma-names = "tx", "rx"; 677 power-domains = <&cpg_clocks>; 678 status = "disabled"; 679 }; 680 681 scif1: serial@e6e68000 { 682 compatible = "renesas,scif-r8a7791", "renesas,scif"; 683 reg = <0 0xe6e68000 0 64>; 684 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>; 686 clock-names = "sci_ick"; 687 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>; 688 dma-names = "tx", "rx"; 689 power-domains = <&cpg_clocks>; 690 status = "disabled"; 691 }; 692 693 scif2: serial@e6e58000 { 694 compatible = "renesas,scif-r8a7791", "renesas,scif"; 695 reg = <0 0xe6e58000 0 64>; 696 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>; 698 clock-names = "sci_ick"; 699 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; 700 dma-names = "tx", "rx"; 701 power-domains = <&cpg_clocks>; 702 status = "disabled"; 703 }; 704 705 scif3: serial@e6ea8000 { 706 compatible = "renesas,scif-r8a7791", "renesas,scif"; 707 reg = <0 0xe6ea8000 0 64>; 708 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 709 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>; 710 clock-names = "sci_ick"; 711 dmas = <&dmac0 0x2f>, <&dmac0 0x30>; 712 dma-names = "tx", "rx"; 713 power-domains = <&cpg_clocks>; 714 status = "disabled"; 715 }; 716 717 scif4: serial@e6ee0000 { 718 compatible = "renesas,scif-r8a7791", "renesas,scif"; 719 reg = <0 0xe6ee0000 0 64>; 720 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>; 722 clock-names = "sci_ick"; 723 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>; 724 dma-names = "tx", "rx"; 725 power-domains = <&cpg_clocks>; 726 status = "disabled"; 727 }; 728 729 scif5: serial@e6ee8000 { 730 compatible = "renesas,scif-r8a7791", "renesas,scif"; 731 reg = <0 0xe6ee8000 0 64>; 732 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 733 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>; 734 clock-names = "sci_ick"; 735 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>; 736 dma-names = "tx", "rx"; 737 power-domains = <&cpg_clocks>; 738 status = "disabled"; 739 }; 740 741 hscif0: serial@e62c0000 { 742 compatible = "renesas,hscif-r8a7791", "renesas,hscif"; 743 reg = <0 0xe62c0000 0 96>; 744 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>; 746 clock-names = "sci_ick"; 747 dmas = <&dmac0 0x39>, <&dmac0 0x3a>; 748 dma-names = "tx", "rx"; 749 power-domains = <&cpg_clocks>; 750 status = "disabled"; 751 }; 752 753 hscif1: serial@e62c8000 { 754 compatible = "renesas,hscif-r8a7791", "renesas,hscif"; 755 reg = <0 0xe62c8000 0 96>; 756 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>; 758 clock-names = "sci_ick"; 759 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>; 760 dma-names = "tx", "rx"; 761 power-domains = <&cpg_clocks>; 762 status = "disabled"; 763 }; 764 765 hscif2: serial@e62d0000 { 766 compatible = "renesas,hscif-r8a7791", "renesas,hscif"; 767 reg = <0 0xe62d0000 0 96>; 768 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>; 770 clock-names = "sci_ick"; 771 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>; 772 dma-names = "tx", "rx"; 773 power-domains = <&cpg_clocks>; 774 status = "disabled"; 775 }; 776 777 ether: ethernet@ee700000 { 778 compatible = "renesas,ether-r8a7791"; 779 reg = <0 0xee700000 0 0x400>; 780 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&mstp8_clks R8A7791_CLK_ETHER>; 782 power-domains = <&cpg_clocks>; 783 phy-mode = "rmii"; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 status = "disabled"; 787 }; 788 789 sata0: sata@ee300000 { 790 compatible = "renesas,sata-r8a7791"; 791 reg = <0 0xee300000 0 0x2000>; 792 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 793 clocks = <&mstp8_clks R8A7791_CLK_SATA0>; 794 power-domains = <&cpg_clocks>; 795 status = "disabled"; 796 }; 797 798 sata1: sata@ee500000 { 799 compatible = "renesas,sata-r8a7791"; 800 reg = <0 0xee500000 0 0x2000>; 801 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&mstp8_clks R8A7791_CLK_SATA1>; 803 power-domains = <&cpg_clocks>; 804 status = "disabled"; 805 }; 806 807 hsusb: usb@e6590000 { 808 compatible = "renesas,usbhs-r8a7791"; 809 reg = <0 0xe6590000 0 0x100>; 810 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; 812 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 813 <&usb_dmac1 0>, <&usb_dmac1 1>; 814 dma-names = "ch0", "ch1", "ch2", "ch3"; 815 power-domains = <&cpg_clocks>; 816 renesas,buswait = <4>; 817 phys = <&usb0 1>; 818 phy-names = "usb"; 819 status = "disabled"; 820 }; 821 822 usbphy: usb-phy@e6590100 { 823 compatible = "renesas,usb-phy-r8a7791"; 824 reg = <0 0xe6590100 0 0x100>; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; 828 clock-names = "usbhs"; 829 power-domains = <&cpg_clocks>; 830 status = "disabled"; 831 832 usb0: usb-channel@0 { 833 reg = <0>; 834 #phy-cells = <1>; 835 }; 836 usb2: usb-channel@2 { 837 reg = <2>; 838 #phy-cells = <1>; 839 }; 840 }; 841 842 vin0: video@e6ef0000 { 843 compatible = "renesas,vin-r8a7791"; 844 reg = <0 0xe6ef0000 0 0x1000>; 845 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&mstp8_clks R8A7791_CLK_VIN0>; 847 power-domains = <&cpg_clocks>; 848 status = "disabled"; 849 }; 850 851 vin1: video@e6ef1000 { 852 compatible = "renesas,vin-r8a7791"; 853 reg = <0 0xe6ef1000 0 0x1000>; 854 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&mstp8_clks R8A7791_CLK_VIN1>; 856 power-domains = <&cpg_clocks>; 857 status = "disabled"; 858 }; 859 860 vin2: video@e6ef2000 { 861 compatible = "renesas,vin-r8a7791"; 862 reg = <0 0xe6ef2000 0 0x1000>; 863 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&mstp8_clks R8A7791_CLK_VIN2>; 865 power-domains = <&cpg_clocks>; 866 status = "disabled"; 867 }; 868 869 vsp1@fe928000 { 870 compatible = "renesas,vsp1"; 871 reg = <0 0xfe928000 0 0x8000>; 872 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; 874 power-domains = <&cpg_clocks>; 875 876 renesas,has-lut; 877 renesas,has-sru; 878 renesas,#rpf = <5>; 879 renesas,#uds = <3>; 880 renesas,#wpf = <4>; 881 }; 882 883 vsp1@fe930000 { 884 compatible = "renesas,vsp1"; 885 reg = <0 0xfe930000 0 0x8000>; 886 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; 888 power-domains = <&cpg_clocks>; 889 890 renesas,has-lif; 891 renesas,has-lut; 892 renesas,#rpf = <4>; 893 renesas,#uds = <1>; 894 renesas,#wpf = <4>; 895 }; 896 897 vsp1@fe938000 { 898 compatible = "renesas,vsp1"; 899 reg = <0 0xfe938000 0 0x8000>; 900 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; 902 power-domains = <&cpg_clocks>; 903 904 renesas,has-lif; 905 renesas,has-lut; 906 renesas,#rpf = <4>; 907 renesas,#uds = <1>; 908 renesas,#wpf = <4>; 909 }; 910 911 du: display@feb00000 { 912 compatible = "renesas,du-r8a7791"; 913 reg = <0 0xfeb00000 0 0x40000>, 914 <0 0xfeb90000 0 0x1c>; 915 reg-names = "du", "lvds.0"; 916 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, 917 <0 268 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&mstp7_clks R8A7791_CLK_DU0>, 919 <&mstp7_clks R8A7791_CLK_DU1>, 920 <&mstp7_clks R8A7791_CLK_LVDS0>; 921 clock-names = "du.0", "du.1", "lvds.0"; 922 status = "disabled"; 923 924 ports { 925 #address-cells = <1>; 926 #size-cells = <0>; 927 928 port@0 { 929 reg = <0>; 930 du_out_rgb: endpoint { 931 }; 932 }; 933 port@1 { 934 reg = <1>; 935 du_out_lvds0: endpoint { 936 }; 937 }; 938 }; 939 }; 940 941 can0: can@e6e80000 { 942 compatible = "renesas,can-r8a7791"; 943 reg = <0 0xe6e80000 0 0x1000>; 944 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, 946 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; 947 clock-names = "clkp1", "clkp2", "can_clk"; 948 power-domains = <&cpg_clocks>; 949 status = "disabled"; 950 }; 951 952 can1: can@e6e88000 { 953 compatible = "renesas,can-r8a7791"; 954 reg = <0 0xe6e88000 0 0x1000>; 955 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, 957 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; 958 clock-names = "clkp1", "clkp2", "can_clk"; 959 power-domains = <&cpg_clocks>; 960 status = "disabled"; 961 }; 962 963 jpu: jpeg-codec@fe980000 { 964 compatible = "renesas,jpu-r8a7791"; 965 reg = <0 0xfe980000 0 0x10300>; 966 interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&mstp1_clks R8A7791_CLK_JPU>; 968 power-domains = <&cpg_clocks>; 969 }; 970 971 clocks { 972 #address-cells = <2>; 973 #size-cells = <2>; 974 ranges; 975 976 /* External root clock */ 977 extal_clk: extal_clk { 978 compatible = "fixed-clock"; 979 #clock-cells = <0>; 980 /* This value must be overriden by the board. */ 981 clock-frequency = <0>; 982 clock-output-names = "extal"; 983 }; 984 985 /* 986 * The external audio clocks are configured as 0 Hz fixed frequency clocks by 987 * default. Boards that provide audio clocks should override them. 988 */ 989 audio_clk_a: audio_clk_a { 990 compatible = "fixed-clock"; 991 #clock-cells = <0>; 992 clock-frequency = <0>; 993 clock-output-names = "audio_clk_a"; 994 }; 995 audio_clk_b: audio_clk_b { 996 compatible = "fixed-clock"; 997 #clock-cells = <0>; 998 clock-frequency = <0>; 999 clock-output-names = "audio_clk_b"; 1000 }; 1001 audio_clk_c: audio_clk_c { 1002 compatible = "fixed-clock"; 1003 #clock-cells = <0>; 1004 clock-frequency = <0>; 1005 clock-output-names = "audio_clk_c"; 1006 }; 1007 1008 /* External PCIe clock - can be overridden by the board */ 1009 pcie_bus_clk: pcie_bus_clk { 1010 compatible = "fixed-clock"; 1011 #clock-cells = <0>; 1012 clock-frequency = <100000000>; 1013 clock-output-names = "pcie_bus"; 1014 status = "disabled"; 1015 }; 1016 1017 /* External USB clock - can be overridden by the board */ 1018 usb_extal_clk: usb_extal_clk { 1019 compatible = "fixed-clock"; 1020 #clock-cells = <0>; 1021 clock-frequency = <48000000>; 1022 clock-output-names = "usb_extal"; 1023 }; 1024 1025 /* External CAN clock */ 1026 can_clk: can_clk { 1027 compatible = "fixed-clock"; 1028 #clock-cells = <0>; 1029 /* This value must be overridden by the board. */ 1030 clock-frequency = <0>; 1031 clock-output-names = "can_clk"; 1032 status = "disabled"; 1033 }; 1034 1035 /* Special CPG clocks */ 1036 cpg_clocks: cpg_clocks@e6150000 { 1037 compatible = "renesas,r8a7791-cpg-clocks", 1038 "renesas,rcar-gen2-cpg-clocks"; 1039 reg = <0 0xe6150000 0 0x1000>; 1040 clocks = <&extal_clk &usb_extal_clk>; 1041 #clock-cells = <1>; 1042 clock-output-names = "main", "pll0", "pll1", "pll3", 1043 "lb", "qspi", "sdh", "sd0", "z", 1044 "rcan", "adsp"; 1045 #power-domain-cells = <0>; 1046 }; 1047 1048 /* Variable factor clocks */ 1049 sd2_clk: sd2_clk@e6150078 { 1050 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 1051 reg = <0 0xe6150078 0 4>; 1052 clocks = <&pll1_div2_clk>; 1053 #clock-cells = <0>; 1054 clock-output-names = "sd2"; 1055 }; 1056 sd3_clk: sd3_clk@e615026c { 1057 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 1058 reg = <0 0xe615026c 0 4>; 1059 clocks = <&pll1_div2_clk>; 1060 #clock-cells = <0>; 1061 clock-output-names = "sd3"; 1062 }; 1063 mmc0_clk: mmc0_clk@e6150240 { 1064 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 1065 reg = <0 0xe6150240 0 4>; 1066 clocks = <&pll1_div2_clk>; 1067 #clock-cells = <0>; 1068 clock-output-names = "mmc0"; 1069 }; 1070 ssp_clk: ssp_clk@e6150248 { 1071 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 1072 reg = <0 0xe6150248 0 4>; 1073 clocks = <&pll1_div2_clk>; 1074 #clock-cells = <0>; 1075 clock-output-names = "ssp"; 1076 }; 1077 ssprs_clk: ssprs_clk@e615024c { 1078 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 1079 reg = <0 0xe615024c 0 4>; 1080 clocks = <&pll1_div2_clk>; 1081 #clock-cells = <0>; 1082 clock-output-names = "ssprs"; 1083 }; 1084 1085 /* Fixed factor clocks */ 1086 pll1_div2_clk: pll1_div2_clk { 1087 compatible = "fixed-factor-clock"; 1088 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1089 #clock-cells = <0>; 1090 clock-div = <2>; 1091 clock-mult = <1>; 1092 clock-output-names = "pll1_div2"; 1093 }; 1094 zg_clk: zg_clk { 1095 compatible = "fixed-factor-clock"; 1096 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1097 #clock-cells = <0>; 1098 clock-div = <3>; 1099 clock-mult = <1>; 1100 clock-output-names = "zg"; 1101 }; 1102 zx_clk: zx_clk { 1103 compatible = "fixed-factor-clock"; 1104 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1105 #clock-cells = <0>; 1106 clock-div = <3>; 1107 clock-mult = <1>; 1108 clock-output-names = "zx"; 1109 }; 1110 zs_clk: zs_clk { 1111 compatible = "fixed-factor-clock"; 1112 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1113 #clock-cells = <0>; 1114 clock-div = <6>; 1115 clock-mult = <1>; 1116 clock-output-names = "zs"; 1117 }; 1118 hp_clk: hp_clk { 1119 compatible = "fixed-factor-clock"; 1120 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1121 #clock-cells = <0>; 1122 clock-div = <12>; 1123 clock-mult = <1>; 1124 clock-output-names = "hp"; 1125 }; 1126 i_clk: i_clk { 1127 compatible = "fixed-factor-clock"; 1128 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1129 #clock-cells = <0>; 1130 clock-div = <2>; 1131 clock-mult = <1>; 1132 clock-output-names = "i"; 1133 }; 1134 b_clk: b_clk { 1135 compatible = "fixed-factor-clock"; 1136 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1137 #clock-cells = <0>; 1138 clock-div = <12>; 1139 clock-mult = <1>; 1140 clock-output-names = "b"; 1141 }; 1142 p_clk: p_clk { 1143 compatible = "fixed-factor-clock"; 1144 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1145 #clock-cells = <0>; 1146 clock-div = <24>; 1147 clock-mult = <1>; 1148 clock-output-names = "p"; 1149 }; 1150 cl_clk: cl_clk { 1151 compatible = "fixed-factor-clock"; 1152 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1153 #clock-cells = <0>; 1154 clock-div = <48>; 1155 clock-mult = <1>; 1156 clock-output-names = "cl"; 1157 }; 1158 m2_clk: m2_clk { 1159 compatible = "fixed-factor-clock"; 1160 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1161 #clock-cells = <0>; 1162 clock-div = <8>; 1163 clock-mult = <1>; 1164 clock-output-names = "m2"; 1165 }; 1166 imp_clk: imp_clk { 1167 compatible = "fixed-factor-clock"; 1168 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1169 #clock-cells = <0>; 1170 clock-div = <4>; 1171 clock-mult = <1>; 1172 clock-output-names = "imp"; 1173 }; 1174 rclk_clk: rclk_clk { 1175 compatible = "fixed-factor-clock"; 1176 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1177 #clock-cells = <0>; 1178 clock-div = <(48 * 1024)>; 1179 clock-mult = <1>; 1180 clock-output-names = "rclk"; 1181 }; 1182 oscclk_clk: oscclk_clk { 1183 compatible = "fixed-factor-clock"; 1184 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1185 #clock-cells = <0>; 1186 clock-div = <(12 * 1024)>; 1187 clock-mult = <1>; 1188 clock-output-names = "oscclk"; 1189 }; 1190 zb3_clk: zb3_clk { 1191 compatible = "fixed-factor-clock"; 1192 clocks = <&cpg_clocks R8A7791_CLK_PLL3>; 1193 #clock-cells = <0>; 1194 clock-div = <4>; 1195 clock-mult = <1>; 1196 clock-output-names = "zb3"; 1197 }; 1198 zb3d2_clk: zb3d2_clk { 1199 compatible = "fixed-factor-clock"; 1200 clocks = <&cpg_clocks R8A7791_CLK_PLL3>; 1201 #clock-cells = <0>; 1202 clock-div = <8>; 1203 clock-mult = <1>; 1204 clock-output-names = "zb3d2"; 1205 }; 1206 ddr_clk: ddr_clk { 1207 compatible = "fixed-factor-clock"; 1208 clocks = <&cpg_clocks R8A7791_CLK_PLL3>; 1209 #clock-cells = <0>; 1210 clock-div = <8>; 1211 clock-mult = <1>; 1212 clock-output-names = "ddr"; 1213 }; 1214 mp_clk: mp_clk { 1215 compatible = "fixed-factor-clock"; 1216 clocks = <&pll1_div2_clk>; 1217 #clock-cells = <0>; 1218 clock-div = <15>; 1219 clock-mult = <1>; 1220 clock-output-names = "mp"; 1221 }; 1222 cp_clk: cp_clk { 1223 compatible = "fixed-factor-clock"; 1224 clocks = <&extal_clk>; 1225 #clock-cells = <0>; 1226 clock-div = <2>; 1227 clock-mult = <1>; 1228 clock-output-names = "cp"; 1229 }; 1230 1231 /* Gate clocks */ 1232 mstp0_clks: mstp0_clks@e6150130 { 1233 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1234 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; 1235 clocks = <&mp_clk>; 1236 #clock-cells = <1>; 1237 clock-indices = <R8A7791_CLK_MSIOF0>; 1238 clock-output-names = "msiof0"; 1239 }; 1240 mstp1_clks: mstp1_clks@e6150134 { 1241 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1242 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 1243 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>, 1244 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, 1245 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, 1246 <&zs_clk>; 1247 #clock-cells = <1>; 1248 clock-indices = < 1249 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU 1250 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG 1251 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 1252 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 1253 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0 1254 R8A7791_CLK_VSP1_S 1255 >; 1256 clock-output-names = 1257 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg", 1258 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0", 1259 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy"; 1260 }; 1261 mstp2_clks: mstp2_clks@e6150138 { 1262 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1263 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 1264 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 1265 <&mp_clk>, <&mp_clk>, <&mp_clk>, 1266 <&zs_clk>, <&zs_clk>; 1267 #clock-cells = <1>; 1268 clock-indices = < 1269 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 1270 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 1271 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 1272 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 1273 >; 1274 clock-output-names = 1275 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", 1276 "scifb1", "msiof1", "scifb2", 1277 "sys-dmac1", "sys-dmac0"; 1278 }; 1279 mstp3_clks: mstp3_clks@e615013c { 1280 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1281 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 1282 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>, 1283 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, 1284 <&hp_clk>, <&hp_clk>; 1285 #clock-cells = <1>; 1286 clock-indices = < 1287 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 1288 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 1289 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 1290 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1 1291 >; 1292 clock-output-names = 1293 "tpu0", "sdhi2", "sdhi1", "sdhi0", 1294 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1", 1295 "usbdmac0", "usbdmac1"; 1296 }; 1297 mstp4_clks: mstp4_clks@e6150140 { 1298 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1299 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; 1300 clocks = <&cp_clk>; 1301 #clock-cells = <1>; 1302 clock-indices = <R8A7791_CLK_IRQC>; 1303 clock-output-names = "irqc"; 1304 }; 1305 mstp5_clks: mstp5_clks@e6150144 { 1306 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1307 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1308 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>, 1309 <&extal_clk>, <&p_clk>; 1310 #clock-cells = <1>; 1311 clock-indices = < 1312 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 1313 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL 1314 R8A7791_CLK_PWM 1315 >; 1316 clock-output-names = "audmac0", "audmac1", "adsp_mod", 1317 "thermal", "pwm"; 1318 }; 1319 mstp7_clks: mstp7_clks@e615014c { 1320 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1321 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; 1322 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, 1323 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, 1324 <&zx_clk>, <&zx_clk>, <&zx_clk>; 1325 #clock-cells = <1>; 1326 clock-indices = < 1327 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 1328 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 1329 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 1330 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 1331 R8A7791_CLK_LVDS0 1332 >; 1333 clock-output-names = 1334 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", 1335 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; 1336 }; 1337 mstp8_clks: mstp8_clks@e6150990 { 1338 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1339 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 1340 clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>, 1341 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>; 1342 #clock-cells = <1>; 1343 clock-indices = < 1344 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB 1345 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 1346 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 1347 >; 1348 clock-output-names = 1349 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether", 1350 "sata1", "sata0"; 1351 }; 1352 mstp9_clks: mstp9_clks@e6150994 { 1353 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1354 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; 1355 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, 1356 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, 1357 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, 1358 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, 1359 <&hp_clk>, <&hp_clk>; 1360 #clock-cells = <1>; 1361 clock-indices = < 1362 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 1363 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 1364 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 1365 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 1366 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 1367 >; 1368 clock-output-names = 1369 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", 1370 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", 1371 "i2c1", "i2c0"; 1372 }; 1373 mstp10_clks: mstp10_clks@e6150998 { 1374 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1375 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; 1376 clocks = <&p_clk>, 1377 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, 1378 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, 1379 <&p_clk>, 1380 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, 1381 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, 1382 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, 1383 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, 1384 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, 1385 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, 1386 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; 1387 1388 #clock-cells = <1>; 1389 clock-indices = < 1390 R8A7791_CLK_SSI_ALL 1391 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 1392 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 1393 R8A7791_CLK_SCU_ALL 1394 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 1395 R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0 1396 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 1397 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 1398 >; 1399 clock-output-names = 1400 "ssi-all", 1401 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", 1402 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", 1403 "scu-all", 1404 "scu-dvc1", "scu-dvc0", 1405 "scu-ctu1-mix1", "scu-ctu0-mix0", 1406 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", 1407 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; 1408 }; 1409 mstp11_clks: mstp11_clks@e615099c { 1410 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1411 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; 1412 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; 1413 #clock-cells = <1>; 1414 clock-indices = < 1415 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 1416 >; 1417 clock-output-names = "scifa3", "scifa4", "scifa5"; 1418 }; 1419 }; 1420 1421 qspi: spi@e6b10000 { 1422 compatible = "renesas,qspi-r8a7791", "renesas,qspi"; 1423 reg = <0 0xe6b10000 0 0x2c>; 1424 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; 1425 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; 1426 dmas = <&dmac0 0x17>, <&dmac0 0x18>; 1427 dma-names = "tx", "rx"; 1428 power-domains = <&cpg_clocks>; 1429 num-cs = <1>; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 status = "disabled"; 1433 }; 1434 1435 msiof0: spi@e6e20000 { 1436 compatible = "renesas,msiof-r8a7791"; 1437 reg = <0 0xe6e20000 0 0x0064>; 1438 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 1439 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; 1440 dmas = <&dmac0 0x51>, <&dmac0 0x52>; 1441 dma-names = "tx", "rx"; 1442 power-domains = <&cpg_clocks>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 status = "disabled"; 1446 }; 1447 1448 msiof1: spi@e6e10000 { 1449 compatible = "renesas,msiof-r8a7791"; 1450 reg = <0 0xe6e10000 0 0x0064>; 1451 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; 1452 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; 1453 dmas = <&dmac0 0x55>, <&dmac0 0x56>; 1454 dma-names = "tx", "rx"; 1455 power-domains = <&cpg_clocks>; 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 status = "disabled"; 1459 }; 1460 1461 msiof2: spi@e6e00000 { 1462 compatible = "renesas,msiof-r8a7791"; 1463 reg = <0 0xe6e00000 0 0x0064>; 1464 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; 1465 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; 1466 dmas = <&dmac0 0x41>, <&dmac0 0x42>; 1467 dma-names = "tx", "rx"; 1468 power-domains = <&cpg_clocks>; 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 status = "disabled"; 1472 }; 1473 1474 xhci: usb@ee000000 { 1475 compatible = "renesas,xhci-r8a7791"; 1476 reg = <0 0xee000000 0 0xc00>; 1477 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; 1478 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; 1479 power-domains = <&cpg_clocks>; 1480 phys = <&usb2 1>; 1481 phy-names = "usb"; 1482 status = "disabled"; 1483 }; 1484 1485 pci0: pci@ee090000 { 1486 compatible = "renesas,pci-r8a7791"; 1487 device_type = "pci"; 1488 reg = <0 0xee090000 0 0xc00>, 1489 <0 0xee080000 0 0x1100>; 1490 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 1491 clocks = <&mstp7_clks R8A7791_CLK_EHCI>; 1492 power-domains = <&cpg_clocks>; 1493 status = "disabled"; 1494 1495 bus-range = <0 0>; 1496 #address-cells = <3>; 1497 #size-cells = <2>; 1498 #interrupt-cells = <1>; 1499 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; 1500 interrupt-map-mask = <0xff00 0 0 0x7>; 1501 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 1502 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 1503 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; 1504 1505 usb@0,1 { 1506 reg = <0x800 0 0 0 0>; 1507 device_type = "pci"; 1508 phys = <&usb0 0>; 1509 phy-names = "usb"; 1510 }; 1511 1512 usb@0,2 { 1513 reg = <0x1000 0 0 0 0>; 1514 device_type = "pci"; 1515 phys = <&usb0 0>; 1516 phy-names = "usb"; 1517 }; 1518 }; 1519 1520 pci1: pci@ee0d0000 { 1521 compatible = "renesas,pci-r8a7791"; 1522 device_type = "pci"; 1523 reg = <0 0xee0d0000 0 0xc00>, 1524 <0 0xee0c0000 0 0x1100>; 1525 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; 1526 clocks = <&mstp7_clks R8A7791_CLK_EHCI>; 1527 power-domains = <&cpg_clocks>; 1528 status = "disabled"; 1529 1530 bus-range = <1 1>; 1531 #address-cells = <3>; 1532 #size-cells = <2>; 1533 #interrupt-cells = <1>; 1534 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; 1535 interrupt-map-mask = <0xff00 0 0 0x7>; 1536 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 1537 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 1538 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; 1539 1540 usb@0,1 { 1541 reg = <0x800 0 0 0 0>; 1542 device_type = "pci"; 1543 phys = <&usb2 0>; 1544 phy-names = "usb"; 1545 }; 1546 1547 usb@0,2 { 1548 reg = <0x1000 0 0 0 0>; 1549 device_type = "pci"; 1550 phys = <&usb2 0>; 1551 phy-names = "usb"; 1552 }; 1553 }; 1554 1555 pciec: pcie@fe000000 { 1556 compatible = "renesas,pcie-r8a7791"; 1557 reg = <0 0xfe000000 0 0x80000>; 1558 #address-cells = <3>; 1559 #size-cells = <2>; 1560 bus-range = <0x00 0xff>; 1561 device_type = "pci"; 1562 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 1563 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 1564 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 1565 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1566 /* Map all possible DDR as inbound ranges */ 1567 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 1568 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; 1569 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, 1570 <0 117 IRQ_TYPE_LEVEL_HIGH>, 1571 <0 118 IRQ_TYPE_LEVEL_HIGH>; 1572 #interrupt-cells = <1>; 1573 interrupt-map-mask = <0 0 0 0>; 1574 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; 1575 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; 1576 clock-names = "pcie", "pcie_bus"; 1577 power-domains = <&cpg_clocks>; 1578 status = "disabled"; 1579 }; 1580 1581 ipmmu_sy0: mmu@e6280000 { 1582 compatible = "renesas,ipmmu-vmsa"; 1583 reg = <0 0xe6280000 0 0x1000>; 1584 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, 1585 <0 224 IRQ_TYPE_LEVEL_HIGH>; 1586 #iommu-cells = <1>; 1587 status = "disabled"; 1588 }; 1589 1590 ipmmu_sy1: mmu@e6290000 { 1591 compatible = "renesas,ipmmu-vmsa"; 1592 reg = <0 0xe6290000 0 0x1000>; 1593 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; 1594 #iommu-cells = <1>; 1595 status = "disabled"; 1596 }; 1597 1598 ipmmu_ds: mmu@e6740000 { 1599 compatible = "renesas,ipmmu-vmsa"; 1600 reg = <0 0xe6740000 0 0x1000>; 1601 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, 1602 <0 199 IRQ_TYPE_LEVEL_HIGH>; 1603 #iommu-cells = <1>; 1604 status = "disabled"; 1605 }; 1606 1607 ipmmu_mp: mmu@ec680000 { 1608 compatible = "renesas,ipmmu-vmsa"; 1609 reg = <0 0xec680000 0 0x1000>; 1610 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; 1611 #iommu-cells = <1>; 1612 status = "disabled"; 1613 }; 1614 1615 ipmmu_mx: mmu@fe951000 { 1616 compatible = "renesas,ipmmu-vmsa"; 1617 reg = <0 0xfe951000 0 0x1000>; 1618 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 1619 <0 221 IRQ_TYPE_LEVEL_HIGH>; 1620 #iommu-cells = <1>; 1621 status = "disabled"; 1622 }; 1623 1624 ipmmu_rt: mmu@ffc80000 { 1625 compatible = "renesas,ipmmu-vmsa"; 1626 reg = <0 0xffc80000 0 0x1000>; 1627 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>; 1628 #iommu-cells = <1>; 1629 status = "disabled"; 1630 }; 1631 1632 ipmmu_gp: mmu@e62a0000 { 1633 compatible = "renesas,ipmmu-vmsa"; 1634 reg = <0 0xe62a0000 0 0x1000>; 1635 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>, 1636 <0 261 IRQ_TYPE_LEVEL_HIGH>; 1637 #iommu-cells = <1>; 1638 status = "disabled"; 1639 }; 1640 1641 rcar_sound: sound@ec500000 { 1642 /* 1643 * #sound-dai-cells is required 1644 * 1645 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1646 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1647 */ 1648 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2"; 1649 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1650 <0 0xec5a0000 0 0x100>, /* ADG */ 1651 <0 0xec540000 0 0x1000>, /* SSIU */ 1652 <0 0xec541000 0 0x280>, /* SSI */ 1653 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1654 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1655 1656 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, 1657 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, 1658 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>, 1659 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>, 1660 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>, 1661 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>, 1662 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>, 1663 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>, 1664 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, 1665 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, 1666 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, 1667 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, 1668 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, 1669 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, 1670 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; 1671 clock-names = "ssi-all", 1672 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", 1673 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", 1674 "src.9", "src.8", "src.7", "src.6", "src.5", 1675 "src.4", "src.3", "src.2", "src.1", "src.0", 1676 "ctu.0", "ctu.1", 1677 "mix.0", "mix.1", 1678 "dvc.0", "dvc.1", 1679 "clk_a", "clk_b", "clk_c", "clk_i"; 1680 power-domains = <&cpg_clocks>; 1681 1682 status = "disabled"; 1683 1684 rcar_sound,dvc { 1685 dvc0: dvc@0 { 1686 dmas = <&audma0 0xbc>; 1687 dma-names = "tx"; 1688 }; 1689 dvc1: dvc@1 { 1690 dmas = <&audma0 0xbe>; 1691 dma-names = "tx"; 1692 }; 1693 }; 1694 1695 rcar_sound,mix { 1696 mix0: mix@0 { }; 1697 mix1: mix@1 { }; 1698 }; 1699 1700 rcar_sound,ctu { 1701 ctu00: ctu@0 { }; 1702 ctu01: ctu@1 { }; 1703 ctu02: ctu@2 { }; 1704 ctu03: ctu@3 { }; 1705 ctu10: ctu@4 { }; 1706 ctu11: ctu@5 { }; 1707 ctu12: ctu@6 { }; 1708 ctu13: ctu@7 { }; 1709 }; 1710 1711 rcar_sound,src { 1712 src0: src@0 { 1713 interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; 1714 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1715 dma-names = "rx", "tx"; 1716 }; 1717 src1: src@1 { 1718 interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; 1719 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1720 dma-names = "rx", "tx"; 1721 }; 1722 src2: src@2 { 1723 interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; 1724 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1725 dma-names = "rx", "tx"; 1726 }; 1727 src3: src@3 { 1728 interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; 1729 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1730 dma-names = "rx", "tx"; 1731 }; 1732 src4: src@4 { 1733 interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; 1734 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1735 dma-names = "rx", "tx"; 1736 }; 1737 src5: src@5 { 1738 interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; 1739 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1740 dma-names = "rx", "tx"; 1741 }; 1742 src6: src@6 { 1743 interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; 1744 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1745 dma-names = "rx", "tx"; 1746 }; 1747 src7: src@7 { 1748 interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; 1749 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1750 dma-names = "rx", "tx"; 1751 }; 1752 src8: src@8 { 1753 interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; 1754 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1755 dma-names = "rx", "tx"; 1756 }; 1757 src9: src@9 { 1758 interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; 1759 dmas = <&audma0 0x97>, <&audma1 0xba>; 1760 dma-names = "rx", "tx"; 1761 }; 1762 }; 1763 1764 rcar_sound,ssi { 1765 ssi0: ssi@0 { 1766 interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; 1767 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; 1768 dma-names = "rx", "tx", "rxu", "txu"; 1769 }; 1770 ssi1: ssi@1 { 1771 interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; 1772 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; 1773 dma-names = "rx", "tx", "rxu", "txu"; 1774 }; 1775 ssi2: ssi@2 { 1776 interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; 1777 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; 1778 dma-names = "rx", "tx", "rxu", "txu"; 1779 }; 1780 ssi3: ssi@3 { 1781 interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; 1782 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; 1783 dma-names = "rx", "tx", "rxu", "txu"; 1784 }; 1785 ssi4: ssi@4 { 1786 interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; 1787 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; 1788 dma-names = "rx", "tx", "rxu", "txu"; 1789 }; 1790 ssi5: ssi@5 { 1791 interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; 1792 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; 1793 dma-names = "rx", "tx", "rxu", "txu"; 1794 }; 1795 ssi6: ssi@6 { 1796 interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; 1797 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; 1798 dma-names = "rx", "tx", "rxu", "txu"; 1799 }; 1800 ssi7: ssi@7 { 1801 interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; 1802 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; 1803 dma-names = "rx", "tx", "rxu", "txu"; 1804 }; 1805 ssi8: ssi@8 { 1806 interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; 1807 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; 1808 dma-names = "rx", "tx", "rxu", "txu"; 1809 }; 1810 ssi9: ssi@9 { 1811 interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; 1812 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; 1813 dma-names = "rx", "tx", "rxu", "txu"; 1814 }; 1815 }; 1816 }; 1817}; 1818