1/*
2 * Device Tree Source for the Porter board
3 *
4 * Copyright (C) 2015 Cogent Embedded, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2.  This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "r8a7791.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16	model = "Porter";
17	compatible = "renesas,porter", "renesas,r8a7791";
18
19	aliases {
20		serial0 = &scif0;
21	};
22
23	chosen {
24		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
25		stdout-path = &scif0;
26	};
27
28	memory@40000000 {
29		device_type = "memory";
30		reg = <0 0x40000000 0 0x40000000>;
31	};
32
33	memory@200000000 {
34		device_type = "memory";
35		reg = <2 0x00000000 0 0x40000000>;
36	};
37
38	vcc_sdhi0: regulator@0 {
39		compatible = "regulator-fixed";
40
41		regulator-name = "SDHI0 Vcc";
42		regulator-min-microvolt = <3300000>;
43		regulator-max-microvolt = <3300000>;
44		regulator-always-on;
45	};
46
47	vccq_sdhi0: regulator@1 {
48		compatible = "regulator-gpio";
49
50		regulator-name = "SDHI0 VccQ";
51		regulator-min-microvolt = <1800000>;
52		regulator-max-microvolt = <3300000>;
53
54		gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
55		gpios-states = <1>;
56		states = <3300000 1
57			  1800000 0>;
58	};
59
60	vcc_sdhi2: regulator@2 {
61		compatible = "regulator-fixed";
62
63		regulator-name = "SDHI2 Vcc";
64		regulator-min-microvolt = <3300000>;
65		regulator-max-microvolt = <3300000>;
66		regulator-always-on;
67	};
68
69	vccq_sdhi2: regulator@3 {
70		compatible = "regulator-gpio";
71
72		regulator-name = "SDHI2 VccQ";
73		regulator-min-microvolt = <1800000>;
74		regulator-max-microvolt = <3300000>;
75
76		gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
77		gpios-states = <1>;
78		states = <3300000 1
79			  1800000 0>;
80	};
81};
82
83&extal_clk {
84	clock-frequency = <20000000>;
85};
86
87&pfc {
88	scif0_pins: serial0 {
89		renesas,groups = "scif0_data_d";
90		renesas,function = "scif0";
91	};
92
93	ether_pins: ether {
94		renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
95		renesas,function = "eth";
96	};
97
98	phy1_pins: phy1 {
99		renesas,groups = "intc_irq0";
100		renesas,function = "intc";
101	};
102
103	sdhi0_pins: sd0 {
104		renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
105		renesas,function = "sdhi0";
106	};
107
108	sdhi2_pins: sd2 {
109		renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
110		renesas,function = "sdhi2";
111	};
112
113	qspi_pins: spi0 {
114		renesas,groups = "qspi_ctrl", "qspi_data4";
115		renesas,function = "qspi";
116	};
117
118	i2c2_pins: i2c2 {
119		renesas,groups = "i2c2";
120		renesas,function = "i2c2";
121	};
122
123	usb0_pins: usb0 {
124		renesas,groups = "usb0";
125		renesas,function = "usb0";
126	};
127
128	usb1_pins: usb1 {
129		renesas,groups = "usb1";
130		renesas,function = "usb1";
131	};
132
133	vin0_pins: vin0 {
134		renesas,groups = "vin0_data8", "vin0_clk";
135		renesas,function = "vin0";
136	};
137};
138
139&scif0 {
140	pinctrl-0 = <&scif0_pins>;
141	pinctrl-names = "default";
142
143	status = "okay";
144};
145
146&ether {
147	pinctrl-0 = <&ether_pins &phy1_pins>;
148	pinctrl-names = "default";
149
150	phy-handle = <&phy1>;
151	renesas,ether-link-active-low;
152	status = "ok";
153
154	phy1: ethernet-phy@1 {
155		reg = <1>;
156		interrupt-parent = <&irqc0>;
157		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
158		micrel,led-mode = <1>;
159	};
160};
161
162&sdhi0 {
163	pinctrl-0 = <&sdhi0_pins>;
164	pinctrl-names = "default";
165
166	vmmc-supply = <&vcc_sdhi0>;
167	vqmmc-supply = <&vccq_sdhi0>;
168	cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
169	wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
170	status = "okay";
171};
172
173&sdhi2 {
174	pinctrl-0 = <&sdhi2_pins>;
175	pinctrl-names = "default";
176
177	vmmc-supply = <&vcc_sdhi2>;
178	vqmmc-supply = <&vccq_sdhi2>;
179	cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
180	status = "okay";
181};
182
183&qspi {
184	pinctrl-0 = <&qspi_pins>;
185	pinctrl-names = "default";
186
187	status = "okay";
188
189	flash@0 {
190		#address-cells = <1>;
191		#size-cells = <1>;
192		compatible = "spansion,s25fl512s", "jedec,spi-nor";
193		reg = <0>;
194		spi-max-frequency = <30000000>;
195		spi-tx-bus-width = <4>;
196		spi-rx-bus-width = <4>;
197		m25p,fast-read;
198
199		partition@0 {
200			label = "loader_prg";
201			reg = <0x00000000 0x00040000>;
202			read-only;
203		};
204		partition@40000 {
205			label = "user_prg";
206			reg = <0x00040000 0x00400000>;
207			read-only;
208		};
209		partition@440000 {
210			label = "flash_fs";
211			reg = <0x00440000 0x03bc0000>;
212		};
213	};
214};
215
216&i2c2 {
217	pinctrl-0 = <&i2c2_pins>;
218	pinctrl-names = "default";
219
220	status = "okay";
221	clock-frequency = <400000>;
222
223	composite-in@20 {
224		compatible = "adi,adv7180";
225		reg = <0x20>;
226		remote = <&vin0>;
227
228		port {
229			adv7180: endpoint {
230				bus-width = <8>;
231				remote-endpoint = <&vin0ep>;
232			};
233		};
234	};
235};
236
237&sata0 {
238	status = "okay";
239};
240
241/* composite video input */
242&vin0 {
243	status = "ok";
244	pinctrl-0 = <&vin0_pins>;
245	pinctrl-names = "default";
246
247	port {
248		#address-cells = <1>;
249		#size-cells = <0>;
250
251		vin0ep: endpoint {
252			remote-endpoint = <&adv7180>;
253			bus-width = <8>;
254		};
255	};
256};
257
258&pci0 {
259	pinctrl-0 = <&usb0_pins>;
260	pinctrl-names = "default";
261
262	status = "okay";
263};
264
265&pci1 {
266	pinctrl-0 = <&usb1_pins>;
267	pinctrl-names = "default";
268
269	status = "okay";
270};
271
272&usbphy {
273	status = "okay";
274};
275
276&pcie_bus_clk {
277	status = "okay";
278};
279
280&pciec {
281	status = "okay";
282};
283