1/* 2 * Device Tree Source for Renesas r8a7779 3 * 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * Copyright (C) 2013 Simon Horman 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12/include/ "skeleton.dtsi" 13 14#include <dt-bindings/clock/r8a7779-clock.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/interrupt-controller/irq.h> 17 18/ { 19 compatible = "renesas,r8a7779"; 20 interrupt-parent = <&gic>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a9"; 29 reg = <0>; 30 clock-frequency = <1000000000>; 31 }; 32 cpu@1 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a9"; 35 reg = <1>; 36 clock-frequency = <1000000000>; 37 }; 38 cpu@2 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a9"; 41 reg = <2>; 42 clock-frequency = <1000000000>; 43 }; 44 cpu@3 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a9"; 47 reg = <3>; 48 clock-frequency = <1000000000>; 49 }; 50 }; 51 52 aliases { 53 spi0 = &hspi0; 54 spi1 = &hspi1; 55 spi2 = &hspi2; 56 }; 57 58 gic: interrupt-controller@f0001000 { 59 compatible = "arm,cortex-a9-gic"; 60 #interrupt-cells = <3>; 61 interrupt-controller; 62 reg = <0xf0001000 0x1000>, 63 <0xf0000100 0x100>; 64 }; 65 66 timer@f0000600 { 67 compatible = "arm,cortex-a9-twd-timer"; 68 reg = <0xf0000600 0x20>; 69 interrupts = <GIC_PPI 13 70 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 71 clocks = <&cpg_clocks R8A7779_CLK_ZS>; 72 }; 73 74 gpio0: gpio@ffc40000 { 75 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 76 reg = <0xffc40000 0x2c>; 77 interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>; 78 #gpio-cells = <2>; 79 gpio-controller; 80 gpio-ranges = <&pfc 0 0 32>; 81 #interrupt-cells = <2>; 82 interrupt-controller; 83 }; 84 85 gpio1: gpio@ffc41000 { 86 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 87 reg = <0xffc41000 0x2c>; 88 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>; 89 #gpio-cells = <2>; 90 gpio-controller; 91 gpio-ranges = <&pfc 0 32 32>; 92 #interrupt-cells = <2>; 93 interrupt-controller; 94 }; 95 96 gpio2: gpio@ffc42000 { 97 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 98 reg = <0xffc42000 0x2c>; 99 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; 100 #gpio-cells = <2>; 101 gpio-controller; 102 gpio-ranges = <&pfc 0 64 32>; 103 #interrupt-cells = <2>; 104 interrupt-controller; 105 }; 106 107 gpio3: gpio@ffc43000 { 108 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 109 reg = <0xffc43000 0x2c>; 110 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; 111 #gpio-cells = <2>; 112 gpio-controller; 113 gpio-ranges = <&pfc 0 96 32>; 114 #interrupt-cells = <2>; 115 interrupt-controller; 116 }; 117 118 gpio4: gpio@ffc44000 { 119 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 120 reg = <0xffc44000 0x2c>; 121 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; 122 #gpio-cells = <2>; 123 gpio-controller; 124 gpio-ranges = <&pfc 0 128 32>; 125 #interrupt-cells = <2>; 126 interrupt-controller; 127 }; 128 129 gpio5: gpio@ffc45000 { 130 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 131 reg = <0xffc45000 0x2c>; 132 interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>; 133 #gpio-cells = <2>; 134 gpio-controller; 135 gpio-ranges = <&pfc 0 160 32>; 136 #interrupt-cells = <2>; 137 interrupt-controller; 138 }; 139 140 gpio6: gpio@ffc46000 { 141 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 142 reg = <0xffc46000 0x2c>; 143 interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>; 144 #gpio-cells = <2>; 145 gpio-controller; 146 gpio-ranges = <&pfc 0 192 9>; 147 #interrupt-cells = <2>; 148 interrupt-controller; 149 }; 150 151 irqpin0: interrupt-controller@fe78001c { 152 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; 153 #interrupt-cells = <2>; 154 status = "disabled"; 155 interrupt-controller; 156 reg = <0xfe78001c 4>, 157 <0xfe780010 4>, 158 <0xfe780024 4>, 159 <0xfe780044 4>, 160 <0xfe780064 4>, 161 <0xfe780000 4>; 162 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH 163 0 28 IRQ_TYPE_LEVEL_HIGH 164 0 29 IRQ_TYPE_LEVEL_HIGH 165 0 30 IRQ_TYPE_LEVEL_HIGH>; 166 sense-bitfield-width = <2>; 167 }; 168 169 i2c0: i2c@ffc70000 { 170 #address-cells = <1>; 171 #size-cells = <0>; 172 compatible = "renesas,i2c-r8a7779"; 173 reg = <0xffc70000 0x1000>; 174 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&mstp0_clks R8A7779_CLK_I2C0>; 176 power-domains = <&cpg_clocks>; 177 status = "disabled"; 178 }; 179 180 i2c1: i2c@ffc71000 { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 compatible = "renesas,i2c-r8a7779"; 184 reg = <0xffc71000 0x1000>; 185 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&mstp0_clks R8A7779_CLK_I2C1>; 187 power-domains = <&cpg_clocks>; 188 status = "disabled"; 189 }; 190 191 i2c2: i2c@ffc72000 { 192 #address-cells = <1>; 193 #size-cells = <0>; 194 compatible = "renesas,i2c-r8a7779"; 195 reg = <0xffc72000 0x1000>; 196 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&mstp0_clks R8A7779_CLK_I2C2>; 198 power-domains = <&cpg_clocks>; 199 status = "disabled"; 200 }; 201 202 i2c3: i2c@ffc73000 { 203 #address-cells = <1>; 204 #size-cells = <0>; 205 compatible = "renesas,i2c-r8a7779"; 206 reg = <0xffc73000 0x1000>; 207 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 208 clocks = <&mstp0_clks R8A7779_CLK_I2C3>; 209 power-domains = <&cpg_clocks>; 210 status = "disabled"; 211 }; 212 213 scif0: serial@ffe40000 { 214 compatible = "renesas,scif-r8a7779", "renesas,scif"; 215 reg = <0xffe40000 0x100>; 216 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>; 218 clock-names = "sci_ick"; 219 power-domains = <&cpg_clocks>; 220 status = "disabled"; 221 }; 222 223 scif1: serial@ffe41000 { 224 compatible = "renesas,scif-r8a7779", "renesas,scif"; 225 reg = <0xffe41000 0x100>; 226 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>; 228 clock-names = "sci_ick"; 229 power-domains = <&cpg_clocks>; 230 status = "disabled"; 231 }; 232 233 scif2: serial@ffe42000 { 234 compatible = "renesas,scif-r8a7779", "renesas,scif"; 235 reg = <0xffe42000 0x100>; 236 interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>; 238 clock-names = "sci_ick"; 239 power-domains = <&cpg_clocks>; 240 status = "disabled"; 241 }; 242 243 scif3: serial@ffe43000 { 244 compatible = "renesas,scif-r8a7779", "renesas,scif"; 245 reg = <0xffe43000 0x100>; 246 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>; 248 clock-names = "sci_ick"; 249 power-domains = <&cpg_clocks>; 250 status = "disabled"; 251 }; 252 253 scif4: serial@ffe44000 { 254 compatible = "renesas,scif-r8a7779", "renesas,scif"; 255 reg = <0xffe44000 0x100>; 256 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>; 258 clock-names = "sci_ick"; 259 power-domains = <&cpg_clocks>; 260 status = "disabled"; 261 }; 262 263 scif5: serial@ffe45000 { 264 compatible = "renesas,scif-r8a7779", "renesas,scif"; 265 reg = <0xffe45000 0x100>; 266 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>; 268 clock-names = "sci_ick"; 269 power-domains = <&cpg_clocks>; 270 status = "disabled"; 271 }; 272 273 pfc: pfc@fffc0000 { 274 compatible = "renesas,pfc-r8a7779"; 275 reg = <0xfffc0000 0x23c>; 276 }; 277 278 thermal@ffc48000 { 279 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; 280 reg = <0xffc48000 0x38>; 281 }; 282 283 tmu0: timer@ffd80000 { 284 compatible = "renesas,tmu-r8a7779", "renesas,tmu"; 285 reg = <0xffd80000 0x30>; 286 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, 287 <0 33 IRQ_TYPE_LEVEL_HIGH>, 288 <0 34 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&mstp0_clks R8A7779_CLK_TMU0>; 290 clock-names = "fck"; 291 power-domains = <&cpg_clocks>; 292 293 #renesas,channels = <3>; 294 295 status = "disabled"; 296 }; 297 298 tmu1: timer@ffd81000 { 299 compatible = "renesas,tmu-r8a7779", "renesas,tmu"; 300 reg = <0xffd81000 0x30>; 301 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, 302 <0 37 IRQ_TYPE_LEVEL_HIGH>, 303 <0 38 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&mstp0_clks R8A7779_CLK_TMU1>; 305 clock-names = "fck"; 306 power-domains = <&cpg_clocks>; 307 308 #renesas,channels = <3>; 309 310 status = "disabled"; 311 }; 312 313 tmu2: timer@ffd82000 { 314 compatible = "renesas,tmu-r8a7779", "renesas,tmu"; 315 reg = <0xffd82000 0x30>; 316 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, 317 <0 41 IRQ_TYPE_LEVEL_HIGH>, 318 <0 42 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&mstp0_clks R8A7779_CLK_TMU2>; 320 clock-names = "fck"; 321 power-domains = <&cpg_clocks>; 322 323 #renesas,channels = <3>; 324 325 status = "disabled"; 326 }; 327 328 sata: sata@fc600000 { 329 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; 330 reg = <0xfc600000 0x2000>; 331 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&mstp1_clks R8A7779_CLK_SATA>; 333 power-domains = <&cpg_clocks>; 334 }; 335 336 sdhi0: sd@ffe4c000 { 337 compatible = "renesas,sdhi-r8a7779"; 338 reg = <0xffe4c000 0x100>; 339 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; 341 power-domains = <&cpg_clocks>; 342 status = "disabled"; 343 }; 344 345 sdhi1: sd@ffe4d000 { 346 compatible = "renesas,sdhi-r8a7779"; 347 reg = <0xffe4d000 0x100>; 348 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; 350 power-domains = <&cpg_clocks>; 351 status = "disabled"; 352 }; 353 354 sdhi2: sd@ffe4e000 { 355 compatible = "renesas,sdhi-r8a7779"; 356 reg = <0xffe4e000 0x100>; 357 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; 359 power-domains = <&cpg_clocks>; 360 status = "disabled"; 361 }; 362 363 sdhi3: sd@ffe4f000 { 364 compatible = "renesas,sdhi-r8a7779"; 365 reg = <0xffe4f000 0x100>; 366 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; 368 power-domains = <&cpg_clocks>; 369 status = "disabled"; 370 }; 371 372 hspi0: spi@fffc7000 { 373 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 374 reg = <0xfffc7000 0x18>; 375 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 379 power-domains = <&cpg_clocks>; 380 status = "disabled"; 381 }; 382 383 hspi1: spi@fffc8000 { 384 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 385 reg = <0xfffc8000 0x18>; 386 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 390 power-domains = <&cpg_clocks>; 391 status = "disabled"; 392 }; 393 394 hspi2: spi@fffc6000 { 395 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 396 reg = <0xfffc6000 0x18>; 397 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 401 power-domains = <&cpg_clocks>; 402 status = "disabled"; 403 }; 404 405 du: display@fff80000 { 406 compatible = "renesas,du-r8a7779"; 407 reg = <0 0xfff80000 0 0x40000>; 408 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&mstp1_clks R8A7779_CLK_DU>; 410 power-domains = <&cpg_clocks>; 411 status = "disabled"; 412 413 ports { 414 #address-cells = <1>; 415 #size-cells = <0>; 416 417 port@0 { 418 reg = <0>; 419 du_out_rgb0: endpoint { 420 }; 421 }; 422 port@1 { 423 reg = <1>; 424 du_out_rgb1: endpoint { 425 }; 426 }; 427 }; 428 }; 429 430 clocks { 431 #address-cells = <1>; 432 #size-cells = <1>; 433 ranges; 434 435 /* External root clock */ 436 extal_clk: extal_clk { 437 compatible = "fixed-clock"; 438 #clock-cells = <0>; 439 /* This value must be overriden by the board. */ 440 clock-frequency = <0>; 441 clock-output-names = "extal"; 442 }; 443 444 /* Special CPG clocks */ 445 cpg_clocks: clocks@ffc80000 { 446 compatible = "renesas,r8a7779-cpg-clocks"; 447 reg = <0xffc80000 0x30>; 448 clocks = <&extal_clk>; 449 #clock-cells = <1>; 450 clock-output-names = "plla", "z", "zs", "s", 451 "s1", "p", "b", "out"; 452 #power-domain-cells = <0>; 453 }; 454 455 /* Fixed factor clocks */ 456 i_clk: i_clk { 457 compatible = "fixed-factor-clock"; 458 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 459 #clock-cells = <0>; 460 clock-div = <2>; 461 clock-mult = <1>; 462 clock-output-names = "i"; 463 }; 464 s3_clk: s3_clk { 465 compatible = "fixed-factor-clock"; 466 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 467 #clock-cells = <0>; 468 clock-div = <8>; 469 clock-mult = <1>; 470 clock-output-names = "s3"; 471 }; 472 s4_clk: s4_clk { 473 compatible = "fixed-factor-clock"; 474 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 475 #clock-cells = <0>; 476 clock-div = <16>; 477 clock-mult = <1>; 478 clock-output-names = "s4"; 479 }; 480 g_clk: g_clk { 481 compatible = "fixed-factor-clock"; 482 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 483 #clock-cells = <0>; 484 clock-div = <24>; 485 clock-mult = <1>; 486 clock-output-names = "g"; 487 }; 488 489 /* Gate clocks */ 490 mstp0_clks: clocks@ffc80030 { 491 compatible = "renesas,r8a7779-mstp-clocks", 492 "renesas,cpg-mstp-clocks"; 493 reg = <0xffc80030 4>; 494 clocks = <&cpg_clocks R8A7779_CLK_S>, 495 <&cpg_clocks R8A7779_CLK_P>, 496 <&cpg_clocks R8A7779_CLK_P>, 497 <&cpg_clocks R8A7779_CLK_P>, 498 <&cpg_clocks R8A7779_CLK_S>, 499 <&cpg_clocks R8A7779_CLK_S>, 500 <&cpg_clocks R8A7779_CLK_P>, 501 <&cpg_clocks R8A7779_CLK_P>, 502 <&cpg_clocks R8A7779_CLK_P>, 503 <&cpg_clocks R8A7779_CLK_P>, 504 <&cpg_clocks R8A7779_CLK_P>, 505 <&cpg_clocks R8A7779_CLK_P>, 506 <&cpg_clocks R8A7779_CLK_P>, 507 <&cpg_clocks R8A7779_CLK_P>, 508 <&cpg_clocks R8A7779_CLK_P>, 509 <&cpg_clocks R8A7779_CLK_P>; 510 #clock-cells = <1>; 511 clock-indices = < 512 R8A7779_CLK_HSPI R8A7779_CLK_TMU2 513 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 514 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 515 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4 516 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 517 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0 518 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 519 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0 520 >; 521 clock-output-names = 522 "hspi", "tmu2", "tmu1", "tmu0", "hscif1", 523 "hscif0", "scif5", "scif4", "scif3", "scif2", 524 "scif1", "scif0", "i2c3", "i2c2", "i2c1", 525 "i2c0"; 526 }; 527 mstp1_clks: clocks@ffc80034 { 528 compatible = "renesas,r8a7779-mstp-clocks", 529 "renesas,cpg-mstp-clocks"; 530 reg = <0xffc80034 4>, <0xffc80044 4>; 531 clocks = <&cpg_clocks R8A7779_CLK_P>, 532 <&cpg_clocks R8A7779_CLK_P>, 533 <&cpg_clocks R8A7779_CLK_S>, 534 <&cpg_clocks R8A7779_CLK_S>, 535 <&cpg_clocks R8A7779_CLK_S>, 536 <&cpg_clocks R8A7779_CLK_S>, 537 <&cpg_clocks R8A7779_CLK_P>, 538 <&cpg_clocks R8A7779_CLK_P>, 539 <&cpg_clocks R8A7779_CLK_P>, 540 <&cpg_clocks R8A7779_CLK_S>; 541 #clock-cells = <1>; 542 clock-indices = < 543 R8A7779_CLK_USB01 R8A7779_CLK_USB2 544 R8A7779_CLK_DU R8A7779_CLK_VIN2 545 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 546 R8A7779_CLK_ETHER R8A7779_CLK_SATA 547 R8A7779_CLK_PCIE R8A7779_CLK_VIN3 548 >; 549 clock-output-names = 550 "usb01", "usb2", 551 "du", "vin2", 552 "vin1", "vin0", 553 "ether", "sata", 554 "pcie", "vin3"; 555 }; 556 mstp3_clks: clocks@ffc8003c { 557 compatible = "renesas,r8a7779-mstp-clocks", 558 "renesas,cpg-mstp-clocks"; 559 reg = <0xffc8003c 4>; 560 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, 561 <&s4_clk>, <&s4_clk>; 562 #clock-cells = <1>; 563 clock-indices = < 564 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 565 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 566 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 567 >; 568 clock-output-names = 569 "sdhi3", "sdhi2", "sdhi1", "sdhi0", 570 "mmc1", "mmc0"; 571 }; 572 }; 573}; 574