1/* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/input/input.h> 15 16/ { 17 chosen { 18 stdout-path = &uart1; 19 }; 20 21 memory { 22 reg = <0x10000000 0x40000000>; 23 }; 24 25 regulators { 26 compatible = "simple-bus"; 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 reg_usb_otg_vbus: regulator@0 { 31 compatible = "regulator-fixed"; 32 reg = <0>; 33 regulator-name = "usb_otg_vbus"; 34 regulator-min-microvolt = <5000000>; 35 regulator-max-microvolt = <5000000>; 36 gpio = <&gpio3 22 0>; 37 enable-active-high; 38 vin-supply = <&swbst_reg>; 39 }; 40 41 reg_usb_h1_vbus: regulator@1 { 42 compatible = "regulator-fixed"; 43 reg = <1>; 44 regulator-name = "usb_h1_vbus"; 45 regulator-min-microvolt = <5000000>; 46 regulator-max-microvolt = <5000000>; 47 gpio = <&gpio1 29 0>; 48 enable-active-high; 49 vin-supply = <&swbst_reg>; 50 }; 51 52 reg_audio: regulator@2 { 53 compatible = "regulator-fixed"; 54 reg = <2>; 55 regulator-name = "wm8962-supply"; 56 gpio = <&gpio4 10 0>; 57 enable-active-high; 58 }; 59 60 reg_pcie: regulator@3 { 61 compatible = "regulator-fixed"; 62 reg = <3>; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_pcie_reg>; 65 regulator-name = "MPCIE_3V3"; 66 regulator-min-microvolt = <3300000>; 67 regulator-max-microvolt = <3300000>; 68 gpio = <&gpio3 19 0>; 69 regulator-always-on; 70 enable-active-high; 71 }; 72 }; 73 74 gpio-keys { 75 compatible = "gpio-keys"; 76 pinctrl-names = "default"; 77 pinctrl-0 = <&pinctrl_gpio_keys>; 78 79 power { 80 label = "Power Button"; 81 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; 82 gpio-key,wakeup; 83 linux,code = <KEY_POWER>; 84 }; 85 86 volume-up { 87 label = "Volume Up"; 88 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 89 gpio-key,wakeup; 90 linux,code = <KEY_VOLUMEUP>; 91 }; 92 93 volume-down { 94 label = "Volume Down"; 95 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; 96 gpio-key,wakeup; 97 linux,code = <KEY_VOLUMEDOWN>; 98 }; 99 }; 100 101 sound { 102 compatible = "fsl,imx6q-sabresd-wm8962", 103 "fsl,imx-audio-wm8962"; 104 model = "wm8962-audio"; 105 ssi-controller = <&ssi2>; 106 audio-codec = <&codec>; 107 audio-routing = 108 "Headphone Jack", "HPOUTL", 109 "Headphone Jack", "HPOUTR", 110 "Ext Spk", "SPKOUTL", 111 "Ext Spk", "SPKOUTR", 112 "AMIC", "MICBIAS", 113 "IN3R", "AMIC"; 114 mux-int-port = <2>; 115 mux-ext-port = <3>; 116 }; 117 118 backlight { 119 compatible = "pwm-backlight"; 120 pwms = <&pwm1 0 5000000>; 121 brightness-levels = <0 4 8 16 32 64 128 255>; 122 default-brightness-level = <7>; 123 status = "okay"; 124 }; 125 126 leds { 127 compatible = "gpio-leds"; 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_gpio_leds>; 130 131 red { 132 gpios = <&gpio1 2 0>; 133 default-state = "on"; 134 }; 135 }; 136}; 137 138&audmux { 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_audmux>; 141 status = "okay"; 142}; 143 144&clks { 145 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 146 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 147 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 148 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 149}; 150 151&ecspi1 { 152 fsl,spi-num-chipselects = <1>; 153 cs-gpios = <&gpio4 9 0>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_ecspi1>; 156 status = "okay"; 157 158 flash: m25p80@0 { 159 #address-cells = <1>; 160 #size-cells = <1>; 161 compatible = "st,m25p32", "jedec,spi-nor"; 162 spi-max-frequency = <20000000>; 163 reg = <0>; 164 }; 165}; 166 167&fec { 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_enet>; 170 phy-mode = "rgmii"; 171 phy-reset-gpios = <&gpio1 25 0>; 172 status = "okay"; 173}; 174 175&hdmi { 176 ddc-i2c-bus = <&i2c2>; 177 status = "okay"; 178}; 179 180&i2c1 { 181 clock-frequency = <100000>; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_i2c1>; 184 status = "okay"; 185 186 codec: wm8962@1a { 187 compatible = "wlf,wm8962"; 188 reg = <0x1a>; 189 clocks = <&clks IMX6QDL_CLK_CKO>; 190 DCVDD-supply = <®_audio>; 191 DBVDD-supply = <®_audio>; 192 AVDD-supply = <®_audio>; 193 CPVDD-supply = <®_audio>; 194 MICVDD-supply = <®_audio>; 195 PLLVDD-supply = <®_audio>; 196 SPKVDD1-supply = <®_audio>; 197 SPKVDD2-supply = <®_audio>; 198 gpio-cfg = < 199 0x0000 /* 0:Default */ 200 0x0000 /* 1:Default */ 201 0x0013 /* 2:FN_DMICCLK */ 202 0x0000 /* 3:Default */ 203 0x8014 /* 4:FN_DMICCDAT */ 204 0x0000 /* 5:Default */ 205 >; 206 }; 207}; 208 209&i2c2 { 210 clock-frequency = <100000>; 211 pinctrl-names = "default"; 212 pinctrl-0 = <&pinctrl_i2c2>; 213 status = "okay"; 214 215 pmic: pfuze100@08 { 216 compatible = "fsl,pfuze100"; 217 reg = <0x08>; 218 219 regulators { 220 sw1a_reg: sw1ab { 221 regulator-min-microvolt = <300000>; 222 regulator-max-microvolt = <1875000>; 223 regulator-boot-on; 224 regulator-always-on; 225 regulator-ramp-delay = <6250>; 226 }; 227 228 sw1c_reg: sw1c { 229 regulator-min-microvolt = <300000>; 230 regulator-max-microvolt = <1875000>; 231 regulator-boot-on; 232 regulator-always-on; 233 regulator-ramp-delay = <6250>; 234 }; 235 236 sw2_reg: sw2 { 237 regulator-min-microvolt = <800000>; 238 regulator-max-microvolt = <3300000>; 239 regulator-boot-on; 240 regulator-always-on; 241 }; 242 243 sw3a_reg: sw3a { 244 regulator-min-microvolt = <400000>; 245 regulator-max-microvolt = <1975000>; 246 regulator-boot-on; 247 regulator-always-on; 248 }; 249 250 sw3b_reg: sw3b { 251 regulator-min-microvolt = <400000>; 252 regulator-max-microvolt = <1975000>; 253 regulator-boot-on; 254 regulator-always-on; 255 }; 256 257 sw4_reg: sw4 { 258 regulator-min-microvolt = <800000>; 259 regulator-max-microvolt = <3300000>; 260 }; 261 262 swbst_reg: swbst { 263 regulator-min-microvolt = <5000000>; 264 regulator-max-microvolt = <5150000>; 265 }; 266 267 snvs_reg: vsnvs { 268 regulator-min-microvolt = <1000000>; 269 regulator-max-microvolt = <3000000>; 270 regulator-boot-on; 271 regulator-always-on; 272 }; 273 274 vref_reg: vrefddr { 275 regulator-boot-on; 276 regulator-always-on; 277 }; 278 279 vgen1_reg: vgen1 { 280 regulator-min-microvolt = <800000>; 281 regulator-max-microvolt = <1550000>; 282 }; 283 284 vgen2_reg: vgen2 { 285 regulator-min-microvolt = <800000>; 286 regulator-max-microvolt = <1550000>; 287 }; 288 289 vgen3_reg: vgen3 { 290 regulator-min-microvolt = <1800000>; 291 regulator-max-microvolt = <3300000>; 292 }; 293 294 vgen4_reg: vgen4 { 295 regulator-min-microvolt = <1800000>; 296 regulator-max-microvolt = <3300000>; 297 regulator-always-on; 298 }; 299 300 vgen5_reg: vgen5 { 301 regulator-min-microvolt = <1800000>; 302 regulator-max-microvolt = <3300000>; 303 regulator-always-on; 304 }; 305 306 vgen6_reg: vgen6 { 307 regulator-min-microvolt = <1800000>; 308 regulator-max-microvolt = <3300000>; 309 regulator-always-on; 310 }; 311 }; 312 }; 313}; 314 315&i2c3 { 316 clock-frequency = <100000>; 317 pinctrl-names = "default"; 318 pinctrl-0 = <&pinctrl_i2c3>; 319 status = "okay"; 320 321 egalax_ts@04 { 322 compatible = "eeti,egalax_ts"; 323 reg = <0x04>; 324 interrupt-parent = <&gpio6>; 325 interrupts = <7 2>; 326 wakeup-gpios = <&gpio6 7 0>; 327 }; 328}; 329 330&iomuxc { 331 pinctrl-names = "default"; 332 pinctrl-0 = <&pinctrl_hog>; 333 334 imx6qdl-sabresd { 335 pinctrl_hog: hoggrp { 336 fsl,pins = < 337 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 338 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 339 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 340 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 341 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 342 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 343 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 344 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 345 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 346 >; 347 }; 348 349 pinctrl_audmux: audmuxgrp { 350 fsl,pins = < 351 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 352 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 353 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 354 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 355 >; 356 }; 357 358 pinctrl_ecspi1: ecspi1grp { 359 fsl,pins = < 360 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 361 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 362 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 363 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0 364 >; 365 }; 366 367 pinctrl_enet: enetgrp { 368 fsl,pins = < 369 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 370 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 371 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 372 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 373 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 374 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 375 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 376 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 377 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 378 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 379 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 380 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 381 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 382 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 383 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 384 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 385 >; 386 }; 387 388 pinctrl_gpio_keys: gpio_keysgrp { 389 fsl,pins = < 390 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 391 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 392 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 393 >; 394 }; 395 396 pinctrl_i2c1: i2c1grp { 397 fsl,pins = < 398 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 399 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 400 >; 401 }; 402 403 pinctrl_i2c2: i2c2grp { 404 fsl,pins = < 405 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 406 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 407 >; 408 }; 409 410 pinctrl_i2c3: i2c3grp { 411 fsl,pins = < 412 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 413 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 414 >; 415 }; 416 417 pinctrl_pcie: pciegrp { 418 fsl,pins = < 419 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 420 >; 421 }; 422 423 pinctrl_pcie_reg: pciereggrp { 424 fsl,pins = < 425 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 426 >; 427 }; 428 429 pinctrl_pwm1: pwm1grp { 430 fsl,pins = < 431 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 432 >; 433 }; 434 435 pinctrl_uart1: uart1grp { 436 fsl,pins = < 437 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 438 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 439 >; 440 }; 441 442 pinctrl_usbotg: usbotggrp { 443 fsl,pins = < 444 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 445 >; 446 }; 447 448 pinctrl_usdhc2: usdhc2grp { 449 fsl,pins = < 450 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 451 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 452 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 453 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 454 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 455 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 456 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 457 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 458 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 459 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 460 >; 461 }; 462 463 pinctrl_usdhc3: usdhc3grp { 464 fsl,pins = < 465 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 466 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 467 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 468 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 469 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 470 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 471 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 472 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 473 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 474 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 475 >; 476 }; 477 478 pinctrl_usdhc4: usdhc4grp { 479 fsl,pins = < 480 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 481 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 482 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 483 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 484 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 485 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 486 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 487 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 488 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 489 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 490 >; 491 }; 492 }; 493 494 gpio_leds { 495 pinctrl_gpio_leds: gpioledsgrp { 496 fsl,pins = < 497 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 498 >; 499 }; 500 }; 501}; 502 503&ldb { 504 status = "okay"; 505 506 lvds-channel@1 { 507 fsl,data-mapping = "spwg"; 508 fsl,data-width = <18>; 509 status = "okay"; 510 511 display-timings { 512 native-mode = <&timing0>; 513 timing0: hsd100pxn1 { 514 clock-frequency = <65000000>; 515 hactive = <1024>; 516 vactive = <768>; 517 hback-porch = <220>; 518 hfront-porch = <40>; 519 vback-porch = <21>; 520 vfront-porch = <7>; 521 hsync-len = <60>; 522 vsync-len = <10>; 523 }; 524 }; 525 }; 526}; 527 528&pcie { 529 pinctrl-names = "default"; 530 pinctrl-0 = <&pinctrl_pcie>; 531 reset-gpio = <&gpio7 12 0>; 532 status = "okay"; 533}; 534 535&pwm1 { 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pinctrl_pwm1>; 538 status = "okay"; 539}; 540 541&snvs_poweroff { 542 status = "okay"; 543}; 544 545&ssi2 { 546 status = "okay"; 547}; 548 549&uart1 { 550 pinctrl-names = "default"; 551 pinctrl-0 = <&pinctrl_uart1>; 552 status = "okay"; 553}; 554 555&usbh1 { 556 vbus-supply = <®_usb_h1_vbus>; 557 status = "okay"; 558}; 559 560&usbotg { 561 vbus-supply = <®_usb_otg_vbus>; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&pinctrl_usbotg>; 564 disable-over-current; 565 status = "okay"; 566}; 567 568&usdhc2 { 569 pinctrl-names = "default"; 570 pinctrl-0 = <&pinctrl_usdhc2>; 571 bus-width = <8>; 572 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 573 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; 574 status = "okay"; 575}; 576 577&usdhc3 { 578 pinctrl-names = "default"; 579 pinctrl-0 = <&pinctrl_usdhc3>; 580 bus-width = <8>; 581 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 582 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 583 status = "okay"; 584}; 585 586&usdhc4 { 587 pinctrl-names = "default"; 588 pinctrl-0 = <&pinctrl_usdhc4>; 589 bus-width = <8>; 590 non-removable; 591 no-1-8-v; 592 status = "okay"; 593}; 594