1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15	/* these are used by bootloader for disabling nodes */
16	aliases {
17		led0 = &led0;
18		led1 = &led1;
19		nand = &gpmi;
20		usb0 = &usbh1;
21		usb1 = &usbotg;
22	};
23
24	chosen {
25		bootargs = "console=ttymxc1,115200";
26	};
27
28	leds {
29		compatible = "gpio-leds";
30		pinctrl-names = "default";
31		pinctrl-0 = <&pinctrl_gpio_leds>;
32
33		led0: user1 {
34			label = "user1";
35			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
36			default-state = "on";
37			linux,default-trigger = "heartbeat";
38		};
39
40		led1: user2 {
41			label = "user2";
42			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
43			default-state = "off";
44		};
45	};
46
47	memory {
48		reg = <0x10000000 0x20000000>;
49	};
50
51	pps {
52		compatible = "pps-gpio";
53		pinctrl-names = "default";
54		pinctrl-0 = <&pinctrl_pps>;
55		gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
56		status = "okay";
57	};
58
59	regulators {
60		compatible = "simple-bus";
61		#address-cells = <1>;
62		#size-cells = <0>;
63
64		reg_3p3v: regulator@0 {
65			compatible = "regulator-fixed";
66			reg = <0>;
67			regulator-name = "3P3V";
68			regulator-min-microvolt = <3300000>;
69			regulator-max-microvolt = <3300000>;
70			regulator-always-on;
71		};
72
73		reg_5p0v: regulator@1 {
74			compatible = "regulator-fixed";
75			reg = <1>;
76			regulator-name = "5P0V";
77			regulator-min-microvolt = <5000000>;
78			regulator-max-microvolt = <5000000>;
79			regulator-always-on;
80		};
81
82		reg_usb_otg_vbus: regulator@2 {
83			compatible = "regulator-fixed";
84			reg = <2>;
85			regulator-name = "usb_otg_vbus";
86			regulator-min-microvolt = <5000000>;
87			regulator-max-microvolt = <5000000>;
88			gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
89			enable-active-high;
90		};
91	};
92};
93
94&fec {
95	pinctrl-names = "default";
96	pinctrl-0 = <&pinctrl_enet>;
97	phy-mode = "rgmii-id";
98	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
99	status = "okay";
100};
101
102&gpmi {
103	pinctrl-names = "default";
104	pinctrl-0 = <&pinctrl_gpmi_nand>;
105	status = "okay";
106};
107
108&hdmi {
109	ddc-i2c-bus = <&i2c3>;
110	status = "okay";
111};
112
113&i2c1 {
114	clock-frequency = <100000>;
115	pinctrl-names = "default";
116	pinctrl-0 = <&pinctrl_i2c1>;
117	status = "okay";
118
119	eeprom1: eeprom@50 {
120		compatible = "atmel,24c02";
121		reg = <0x50>;
122		pagesize = <16>;
123	};
124
125	eeprom2: eeprom@51 {
126		compatible = "atmel,24c02";
127		reg = <0x51>;
128		pagesize = <16>;
129	};
130
131	eeprom3: eeprom@52 {
132		compatible = "atmel,24c02";
133		reg = <0x52>;
134		pagesize = <16>;
135	};
136
137	eeprom4: eeprom@53 {
138		compatible = "atmel,24c02";
139		reg = <0x53>;
140		pagesize = <16>;
141	};
142
143	gpio: pca9555@23 {
144		compatible = "nxp,pca9555";
145		reg = <0x23>;
146		gpio-controller;
147		#gpio-cells = <2>;
148	};
149
150	rtc: ds1672@68 {
151		compatible = "dallas,ds1672";
152		reg = <0x68>;
153	};
154};
155
156&i2c2 {
157	clock-frequency = <100000>;
158	pinctrl-names = "default";
159	pinctrl-0 = <&pinctrl_i2c2>;
160	status = "okay";
161};
162
163&i2c3 {
164	clock-frequency = <100000>;
165	pinctrl-names = "default";
166	pinctrl-0 = <&pinctrl_i2c3>;
167	status = "okay";
168};
169
170&pcie {
171	pinctrl-names = "default";
172	pinctrl-0 = <&pinctrl_pcie>;
173	reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
174	status = "okay";
175};
176
177&uart1 {
178	pinctrl-names = "default";
179	pinctrl-0 = <&pinctrl_uart1>;
180	status = "okay";
181};
182
183&uart2 {
184	pinctrl-names = "default";
185	pinctrl-0 = <&pinctrl_uart2>;
186	status = "okay";
187};
188
189&uart3 {
190	pinctrl-names = "default";
191	pinctrl-0 = <&pinctrl_uart3>;
192	status = "okay";
193};
194
195&uart5 {
196	pinctrl-names = "default";
197	pinctrl-0 = <&pinctrl_uart5>;
198	status = "okay";
199};
200
201&usbotg {
202	vbus-supply = <&reg_usb_otg_vbus>;
203	pinctrl-names = "default";
204	pinctrl-0 = <&pinctrl_usbotg>;
205	disable-over-current;
206	status = "okay";
207};
208
209&usbh1 {
210	status = "okay";
211};
212
213&iomuxc {
214	imx6qdl-gw51xx {
215		pinctrl_enet: enetgrp {
216			fsl,pins = <
217				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
218				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
219				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
220				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
221				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
222				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
223				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
224				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
225				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
226				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
227				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
228				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
229				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
230				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
231				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
232				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
233				MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x1b0b0 /* PHY Reset */
234			>;
235		};
236
237		pinctrl_gpio_leds: gpioledsgrp {
238			fsl,pins = <
239				MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
240				MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
241			>;
242		};
243
244		pinctrl_gpmi_nand: gpminandgrp {
245			fsl,pins = <
246				MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
247				MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
248				MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
249				MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
250				MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
251				MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
252				MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
253				MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
254				MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
255				MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
256				MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
257				MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
258				MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
259				MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
260				MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
261			>;
262		};
263
264		pinctrl_i2c1: i2c1grp {
265			fsl,pins = <
266				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
267				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
268			>;
269		};
270
271		pinctrl_i2c2: i2c2grp {
272			fsl,pins = <
273				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
274				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
275			>;
276		};
277
278		pinctrl_i2c3: i2c3grp {
279			fsl,pins = <
280				MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
281				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
282			>;
283		};
284
285		pinctrl_pcie: pciegrp {
286			fsl,pins = <
287				MX6QDL_PAD_GPIO_0__GPIO1_IO00		0x1b0b0
288			>;
289		};
290
291		pinctrl_pps: ppsgrp {
292			fsl,pins = <
293				MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x1b0b1
294			>;
295		};
296
297		pinctrl_uart1: uart1grp {
298			fsl,pins = <
299				MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
300				MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
301			>;
302		};
303
304		pinctrl_uart2: uart2grp {
305			fsl,pins = <
306				MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
307				MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
308			>;
309		};
310
311		pinctrl_uart3: uart3grp {
312			fsl,pins = <
313				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
314				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
315			>;
316		};
317
318		pinctrl_uart5: uart5grp {
319			fsl,pins = <
320				MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
321				MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
322			>;
323		};
324
325		pinctrl_usbotg: usbotggrp {
326			fsl,pins = <
327				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
328				MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x1b0b0 /* OTG_PWR_EN */
329			>;
330		};
331	};
332};
333