1/*
2 * Copyright 2011-2012 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18
19/* First 4KB has pen for secondary cores. */
20/memreserve/ 0x00000000 0x0001000;
21
22/ {
23	model = "Calxeda Highbank";
24	compatible = "calxeda,highbank";
25	#address-cells = <1>;
26	#size-cells = <1>;
27	clock-ranges;
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		cpu@900 {
34			compatible = "arm,cortex-a9";
35			device_type = "cpu";
36			reg = <0x900>;
37			next-level-cache = <&L2>;
38			clocks = <&a9pll>;
39			clock-names = "cpu";
40			operating-points = <
41				/* kHz    ignored */
42				 1300000  1000000
43				 1200000  1000000
44				 1100000  1000000
45				  800000  1000000
46				  400000  1000000
47				  200000  1000000
48			>;
49			clock-latency = <100000>;
50		};
51
52		cpu@901 {
53			compatible = "arm,cortex-a9";
54			device_type = "cpu";
55			reg = <0x901>;
56			next-level-cache = <&L2>;
57			clocks = <&a9pll>;
58			clock-names = "cpu";
59		};
60
61		cpu@902 {
62			compatible = "arm,cortex-a9";
63			device_type = "cpu";
64			reg = <0x902>;
65			next-level-cache = <&L2>;
66			clocks = <&a9pll>;
67			clock-names = "cpu";
68		};
69
70		cpu@903 {
71			compatible = "arm,cortex-a9";
72			device_type = "cpu";
73			reg = <0x903>;
74			next-level-cache = <&L2>;
75			clocks = <&a9pll>;
76			clock-names = "cpu";
77		};
78	};
79
80	memory {
81		name = "memory";
82		device_type = "memory";
83		reg = <0x00000000 0xff900000>;
84	};
85
86	soc {
87		ranges = <0x00000000 0x00000000 0xffffffff>;
88
89		memory-controller@fff00000 {
90			compatible = "calxeda,hb-ddr-ctrl";
91			reg = <0xfff00000 0x1000>;
92			interrupts = <0 91 4>;
93		};
94
95		timer@fff10600 {
96			compatible = "arm,cortex-a9-twd-timer";
97			reg = <0xfff10600 0x20>;
98			interrupts = <1 13 0xf01>;
99			clocks = <&a9periphclk>;
100		};
101
102		watchdog@fff10620 {
103			compatible = "arm,cortex-a9-twd-wdt";
104			reg = <0xfff10620 0x20>;
105			interrupts = <1 14 0xf01>;
106			clocks = <&a9periphclk>;
107		};
108
109		intc: interrupt-controller@fff11000 {
110			compatible = "arm,cortex-a9-gic";
111			#interrupt-cells = <3>;
112			#size-cells = <0>;
113			#address-cells = <1>;
114			interrupt-controller;
115			reg = <0xfff11000 0x1000>,
116			      <0xfff10100 0x100>;
117		};
118
119		L2: l2-cache {
120			compatible = "arm,pl310-cache";
121			reg = <0xfff12000 0x1000>;
122			interrupts = <0 70 4>;
123			cache-unified;
124			cache-level = <2>;
125		};
126
127		pmu {
128			compatible = "arm,cortex-a9-pmu";
129			interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
130		};
131
132
133		sregs@fff3c200 {
134			compatible = "calxeda,hb-sregs-l2-ecc";
135			reg = <0xfff3c200 0x100>;
136			interrupts = <0 71 4  0 72 4>;
137		};
138
139	};
140};
141
142/include/ "ecx-common.dtsi"
143