1/*
2 * Samsung's Exynos4412 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 *		http://www.samsung.com
6 *
7 * Samsung's Exynos4412 SoC device nodes are listed in this file. Exynos4412
8 * based board files can include this file and provide values for board specfic
9 * bindings.
10 *
11 * Note: This file does not include device nodes for all the controllers in
12 * Exynos4412 SoC. As device tree coverage for Exynos4412 increases, additional
13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18*/
19
20#include "exynos4x12.dtsi"
21
22/ {
23	compatible = "samsung,exynos4412", "samsung,exynos4";
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		cpu0: cpu@A00 {
30			device_type = "cpu";
31			compatible = "arm,cortex-a9";
32			reg = <0xA00>;
33			clocks = <&clock CLK_ARM_CLK>;
34			clock-names = "cpu";
35			operating-points-v2 = <&cpu0_opp_table>;
36			cooling-min-level = <13>;
37			cooling-max-level = <7>;
38			#cooling-cells = <2>; /* min followed by max */
39		};
40
41		cpu@A01 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a9";
44			reg = <0xA01>;
45			operating-points-v2 = <&cpu0_opp_table>;
46		};
47
48		cpu@A02 {
49			device_type = "cpu";
50			compatible = "arm,cortex-a9";
51			reg = <0xA02>;
52			operating-points-v2 = <&cpu0_opp_table>;
53		};
54
55		cpu@A03 {
56			device_type = "cpu";
57			compatible = "arm,cortex-a9";
58			reg = <0xA03>;
59			operating-points-v2 = <&cpu0_opp_table>;
60		};
61	};
62
63	cpu0_opp_table: opp_table0 {
64		compatible = "operating-points-v2";
65		opp-shared;
66
67		opp00 {
68			opp-hz = /bits/ 64 <200000000>;
69			opp-microvolt = <900000>;
70			clock-latency-ns = <200000>;
71		};
72		opp01 {
73			opp-hz = /bits/ 64 <300000000>;
74			opp-microvolt = <900000>;
75			clock-latency-ns = <200000>;
76		};
77		opp02 {
78			opp-hz = /bits/ 64 <400000000>;
79			opp-microvolt = <925000>;
80			clock-latency-ns = <200000>;
81		};
82		opp03 {
83			opp-hz = /bits/ 64 <500000000>;
84			opp-microvolt = <950000>;
85			clock-latency-ns = <200000>;
86		};
87		opp04 {
88			opp-hz = /bits/ 64 <600000000>;
89			opp-microvolt = <975000>;
90			clock-latency-ns = <200000>;
91		};
92		opp05 {
93			opp-hz = /bits/ 64 <700000000>;
94			opp-microvolt = <987500>;
95			clock-latency-ns = <200000>;
96		};
97		opp06 {
98			opp-hz = /bits/ 64 <800000000>;
99			opp-microvolt = <1000000>;
100			clock-latency-ns = <200000>;
101			opp-suspend;
102		};
103		opp07 {
104			opp-hz = /bits/ 64 <900000000>;
105			opp-microvolt = <1037500>;
106			clock-latency-ns = <200000>;
107		};
108		opp08 {
109			opp-hz = /bits/ 64 <1000000000>;
110			opp-microvolt = <1087500>;
111			clock-latency-ns = <200000>;
112		};
113		opp09 {
114			opp-hz = /bits/ 64 <1100000000>;
115			opp-microvolt = <1137500>;
116			clock-latency-ns = <200000>;
117		};
118		opp10 {
119			opp-hz = /bits/ 64 <1200000000>;
120			opp-microvolt = <1187500>;
121			clock-latency-ns = <200000>;
122		};
123		opp11 {
124			opp-hz = /bits/ 64 <1300000000>;
125			opp-microvolt = <1250000>;
126			clock-latency-ns = <200000>;
127		};
128		opp12 {
129			opp-hz = /bits/ 64 <1400000000>;
130			opp-microvolt = <1287500>;
131			clock-latency-ns = <200000>;
132		};
133		opp13 {
134			opp-hz = /bits/ 64 <1500000000>;
135			opp-microvolt = <1350000>;
136			clock-latency-ns = <200000>;
137			turbo-mode;
138		};
139	};
140
141	pmu {
142		interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
143	};
144};
145
146&pmu_system_controller {
147	compatible = "samsung,exynos4412-pmu", "syscon";
148};
149
150&combiner {
151	samsung,combiner-nr = <20>;
152};
153
154&gic {
155	cpu-offset = <0x4000>;
156};
157