1/* 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * Based on "omap4.dtsi" 8 */ 9 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/dra.h> 12 13#include "skeleton.dtsi" 14 15#define MAX_SOURCES 400 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 compatible = "ti,dra7xx"; 22 interrupt-parent = <&crossbar_mpu>; 23 24 aliases { 25 i2c0 = &i2c1; 26 i2c1 = &i2c2; 27 i2c2 = &i2c3; 28 i2c3 = &i2c4; 29 i2c4 = &i2c5; 30 serial0 = &uart1; 31 serial1 = &uart2; 32 serial2 = &uart3; 33 serial3 = &uart4; 34 serial4 = &uart5; 35 serial5 = &uart6; 36 serial6 = &uart7; 37 serial7 = &uart8; 38 serial8 = &uart9; 39 serial9 = &uart10; 40 ethernet0 = &cpsw_emac0; 41 ethernet1 = &cpsw_emac1; 42 d_can0 = &dcan1; 43 d_can1 = &dcan2; 44 }; 45 46 timer { 47 compatible = "arm,armv7-timer"; 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 52 interrupt-parent = <&gic>; 53 }; 54 55 gic: interrupt-controller@48211000 { 56 compatible = "arm,cortex-a15-gic"; 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 reg = <0x48211000 0x1000>, 60 <0x48212000 0x1000>, 61 <0x48214000 0x2000>, 62 <0x48216000 0x2000>; 63 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 64 interrupt-parent = <&gic>; 65 }; 66 67 wakeupgen: interrupt-controller@48281000 { 68 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 69 interrupt-controller; 70 #interrupt-cells = <3>; 71 reg = <0x48281000 0x1000>; 72 interrupt-parent = <&gic>; 73 }; 74 75 /* 76 * The soc node represents the soc top level view. It is used for IPs 77 * that are not memory mapped in the MPU view or for the MPU itself. 78 */ 79 soc { 80 compatible = "ti,omap-infra"; 81 mpu { 82 compatible = "ti,omap5-mpu"; 83 ti,hwmods = "mpu"; 84 }; 85 }; 86 87 /* 88 * XXX: Use a flat representation of the SOC interconnect. 89 * The real OMAP interconnect network is quite complex. 90 * Since it will not bring real advantage to represent that in DT for 91 * the moment, just use a fake OCP bus entry to represent the whole bus 92 * hierarchy. 93 */ 94 ocp { 95 compatible = "ti,dra7-l3-noc", "simple-bus"; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 ranges; 99 ti,hwmods = "l3_main_1", "l3_main_2"; 100 reg = <0x44000000 0x1000000>, 101 <0x45000000 0x1000>; 102 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 103 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 104 105 l4_cfg: l4@4a000000 { 106 compatible = "ti,dra7-l4-cfg", "simple-bus"; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges = <0 0x4a000000 0x22c000>; 110 111 scm: scm@2000 { 112 compatible = "ti,dra7-scm-core", "simple-bus"; 113 reg = <0x2000 0x2000>; 114 #address-cells = <1>; 115 #size-cells = <1>; 116 ranges = <0 0x2000 0x2000>; 117 118 scm_conf: scm_conf@0 { 119 compatible = "syscon", "simple-bus"; 120 reg = <0x0 0x1400>; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges = <0 0x0 0x1400>; 124 125 pbias_regulator: pbias_regulator { 126 compatible = "ti,pbias-dra7", "ti,pbias-omap"; 127 reg = <0xe00 0x4>; 128 syscon = <&scm_conf>; 129 pbias_mmc_reg: pbias_mmc_omap5 { 130 regulator-name = "pbias_mmc_omap5"; 131 regulator-min-microvolt = <1800000>; 132 regulator-max-microvolt = <3000000>; 133 }; 134 }; 135 136 scm_conf_clocks: clocks { 137 #address-cells = <1>; 138 #size-cells = <0>; 139 }; 140 }; 141 142 dra7_pmx_core: pinmux@1400 { 143 compatible = "ti,dra7-padconf", 144 "pinctrl-single"; 145 reg = <0x1400 0x0468>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 #interrupt-cells = <1>; 149 interrupt-controller; 150 pinctrl-single,register-width = <32>; 151 pinctrl-single,function-mask = <0x3fffffff>; 152 }; 153 154 scm_conf1: scm_conf@1c04 { 155 compatible = "syscon"; 156 reg = <0x1c04 0x0020>; 157 }; 158 }; 159 160 cm_core_aon: cm_core_aon@5000 { 161 compatible = "ti,dra7-cm-core-aon"; 162 reg = <0x5000 0x2000>; 163 164 cm_core_aon_clocks: clocks { 165 #address-cells = <1>; 166 #size-cells = <0>; 167 }; 168 169 cm_core_aon_clockdomains: clockdomains { 170 }; 171 }; 172 173 cm_core: cm_core@8000 { 174 compatible = "ti,dra7-cm-core"; 175 reg = <0x8000 0x3000>; 176 177 cm_core_clocks: clocks { 178 #address-cells = <1>; 179 #size-cells = <0>; 180 }; 181 182 cm_core_clockdomains: clockdomains { 183 }; 184 }; 185 }; 186 187 l4_wkup: l4@4ae00000 { 188 compatible = "ti,dra7-l4-wkup", "simple-bus"; 189 #address-cells = <1>; 190 #size-cells = <1>; 191 ranges = <0 0x4ae00000 0x3f000>; 192 193 counter32k: counter@4000 { 194 compatible = "ti,omap-counter32k"; 195 reg = <0x4000 0x40>; 196 ti,hwmods = "counter_32k"; 197 }; 198 199 prm: prm@6000 { 200 compatible = "ti,dra7-prm"; 201 reg = <0x6000 0x3000>; 202 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 203 204 prm_clocks: clocks { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 }; 208 209 prm_clockdomains: clockdomains { 210 }; 211 }; 212 }; 213 214 axi@0 { 215 compatible = "simple-bus"; 216 #size-cells = <1>; 217 #address-cells = <1>; 218 ranges = <0x51000000 0x51000000 0x3000 219 0x0 0x20000000 0x10000000>; 220 pcie1: pcie@51000000 { 221 compatible = "ti,dra7-pcie"; 222 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; 223 reg-names = "rc_dbics", "ti_conf", "config"; 224 interrupts = <0 232 0x4>, <0 233 0x4>; 225 #address-cells = <3>; 226 #size-cells = <2>; 227 device_type = "pci"; 228 ranges = <0x81000000 0 0 0x03000 0 0x00010000 229 0x82000000 0 0x20013000 0x13000 0 0xffed000>; 230 #interrupt-cells = <1>; 231 num-lanes = <1>; 232 ti,hwmods = "pcie1"; 233 phys = <&pcie1_phy>; 234 phy-names = "pcie-phy0"; 235 interrupt-map-mask = <0 0 0 7>; 236 interrupt-map = <0 0 0 1 &pcie1_intc 1>, 237 <0 0 0 2 &pcie1_intc 2>, 238 <0 0 0 3 &pcie1_intc 3>, 239 <0 0 0 4 &pcie1_intc 4>; 240 pcie1_intc: interrupt-controller { 241 interrupt-controller; 242 #address-cells = <0>; 243 #interrupt-cells = <1>; 244 }; 245 }; 246 }; 247 248 axi@1 { 249 compatible = "simple-bus"; 250 #size-cells = <1>; 251 #address-cells = <1>; 252 ranges = <0x51800000 0x51800000 0x3000 253 0x0 0x30000000 0x10000000>; 254 status = "disabled"; 255 pcie@51000000 { 256 compatible = "ti,dra7-pcie"; 257 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; 258 reg-names = "rc_dbics", "ti_conf", "config"; 259 interrupts = <0 355 0x4>, <0 356 0x4>; 260 #address-cells = <3>; 261 #size-cells = <2>; 262 device_type = "pci"; 263 ranges = <0x81000000 0 0 0x03000 0 0x00010000 264 0x82000000 0 0x30013000 0x13000 0 0xffed000>; 265 #interrupt-cells = <1>; 266 num-lanes = <1>; 267 ti,hwmods = "pcie2"; 268 phys = <&pcie2_phy>; 269 phy-names = "pcie-phy0"; 270 interrupt-map-mask = <0 0 0 7>; 271 interrupt-map = <0 0 0 1 &pcie2_intc 1>, 272 <0 0 0 2 &pcie2_intc 2>, 273 <0 0 0 3 &pcie2_intc 3>, 274 <0 0 0 4 &pcie2_intc 4>; 275 pcie2_intc: interrupt-controller { 276 interrupt-controller; 277 #address-cells = <0>; 278 #interrupt-cells = <1>; 279 }; 280 }; 281 }; 282 283 bandgap: bandgap@4a0021e0 { 284 reg = <0x4a0021e0 0xc 285 0x4a00232c 0xc 286 0x4a002380 0x2c 287 0x4a0023C0 0x3c 288 0x4a002564 0x8 289 0x4a002574 0x50>; 290 compatible = "ti,dra752-bandgap"; 291 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 292 #thermal-sensor-cells = <1>; 293 }; 294 295 dsp1_system: dsp_system@40d00000 { 296 compatible = "syscon"; 297 reg = <0x40d00000 0x100>; 298 }; 299 300 sdma: dma-controller@4a056000 { 301 compatible = "ti,omap4430-sdma"; 302 reg = <0x4a056000 0x1000>; 303 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 307 #dma-cells = <1>; 308 dma-channels = <32>; 309 dma-requests = <127>; 310 }; 311 312 sdma_xbar: dma-router@4a002b78 { 313 compatible = "ti,dra7-dma-crossbar"; 314 reg = <0x4a002b78 0xfc>; 315 #dma-cells = <1>; 316 dma-requests = <205>; 317 ti,dma-safe-map = <0>; 318 dma-masters = <&sdma>; 319 }; 320 321 gpio1: gpio@4ae10000 { 322 compatible = "ti,omap4-gpio"; 323 reg = <0x4ae10000 0x200>; 324 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 325 ti,hwmods = "gpio1"; 326 gpio-controller; 327 #gpio-cells = <2>; 328 interrupt-controller; 329 #interrupt-cells = <2>; 330 }; 331 332 gpio2: gpio@48055000 { 333 compatible = "ti,omap4-gpio"; 334 reg = <0x48055000 0x200>; 335 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 336 ti,hwmods = "gpio2"; 337 gpio-controller; 338 #gpio-cells = <2>; 339 interrupt-controller; 340 #interrupt-cells = <2>; 341 }; 342 343 gpio3: gpio@48057000 { 344 compatible = "ti,omap4-gpio"; 345 reg = <0x48057000 0x200>; 346 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 347 ti,hwmods = "gpio3"; 348 gpio-controller; 349 #gpio-cells = <2>; 350 interrupt-controller; 351 #interrupt-cells = <2>; 352 }; 353 354 gpio4: gpio@48059000 { 355 compatible = "ti,omap4-gpio"; 356 reg = <0x48059000 0x200>; 357 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 358 ti,hwmods = "gpio4"; 359 gpio-controller; 360 #gpio-cells = <2>; 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 }; 364 365 gpio5: gpio@4805b000 { 366 compatible = "ti,omap4-gpio"; 367 reg = <0x4805b000 0x200>; 368 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 369 ti,hwmods = "gpio5"; 370 gpio-controller; 371 #gpio-cells = <2>; 372 interrupt-controller; 373 #interrupt-cells = <2>; 374 }; 375 376 gpio6: gpio@4805d000 { 377 compatible = "ti,omap4-gpio"; 378 reg = <0x4805d000 0x200>; 379 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 380 ti,hwmods = "gpio6"; 381 gpio-controller; 382 #gpio-cells = <2>; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 387 gpio7: gpio@48051000 { 388 compatible = "ti,omap4-gpio"; 389 reg = <0x48051000 0x200>; 390 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 391 ti,hwmods = "gpio7"; 392 gpio-controller; 393 #gpio-cells = <2>; 394 interrupt-controller; 395 #interrupt-cells = <2>; 396 }; 397 398 gpio8: gpio@48053000 { 399 compatible = "ti,omap4-gpio"; 400 reg = <0x48053000 0x200>; 401 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 402 ti,hwmods = "gpio8"; 403 gpio-controller; 404 #gpio-cells = <2>; 405 interrupt-controller; 406 #interrupt-cells = <2>; 407 }; 408 409 uart1: serial@4806a000 { 410 compatible = "ti,dra742-uart", "ti,omap4-uart"; 411 reg = <0x4806a000 0x100>; 412 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 413 ti,hwmods = "uart1"; 414 clock-frequency = <48000000>; 415 status = "disabled"; 416 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; 417 dma-names = "tx", "rx"; 418 }; 419 420 uart2: serial@4806c000 { 421 compatible = "ti,dra742-uart", "ti,omap4-uart"; 422 reg = <0x4806c000 0x100>; 423 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 424 ti,hwmods = "uart2"; 425 clock-frequency = <48000000>; 426 status = "disabled"; 427 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; 428 dma-names = "tx", "rx"; 429 }; 430 431 uart3: serial@48020000 { 432 compatible = "ti,dra742-uart", "ti,omap4-uart"; 433 reg = <0x48020000 0x100>; 434 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 435 ti,hwmods = "uart3"; 436 clock-frequency = <48000000>; 437 status = "disabled"; 438 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; 439 dma-names = "tx", "rx"; 440 }; 441 442 uart4: serial@4806e000 { 443 compatible = "ti,dra742-uart", "ti,omap4-uart"; 444 reg = <0x4806e000 0x100>; 445 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 446 ti,hwmods = "uart4"; 447 clock-frequency = <48000000>; 448 status = "disabled"; 449 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; 450 dma-names = "tx", "rx"; 451 }; 452 453 uart5: serial@48066000 { 454 compatible = "ti,dra742-uart", "ti,omap4-uart"; 455 reg = <0x48066000 0x100>; 456 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 457 ti,hwmods = "uart5"; 458 clock-frequency = <48000000>; 459 status = "disabled"; 460 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; 461 dma-names = "tx", "rx"; 462 }; 463 464 uart6: serial@48068000 { 465 compatible = "ti,dra742-uart", "ti,omap4-uart"; 466 reg = <0x48068000 0x100>; 467 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 468 ti,hwmods = "uart6"; 469 clock-frequency = <48000000>; 470 status = "disabled"; 471 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; 472 dma-names = "tx", "rx"; 473 }; 474 475 uart7: serial@48420000 { 476 compatible = "ti,dra742-uart", "ti,omap4-uart"; 477 reg = <0x48420000 0x100>; 478 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 479 ti,hwmods = "uart7"; 480 clock-frequency = <48000000>; 481 status = "disabled"; 482 }; 483 484 uart8: serial@48422000 { 485 compatible = "ti,dra742-uart", "ti,omap4-uart"; 486 reg = <0x48422000 0x100>; 487 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 488 ti,hwmods = "uart8"; 489 clock-frequency = <48000000>; 490 status = "disabled"; 491 }; 492 493 uart9: serial@48424000 { 494 compatible = "ti,dra742-uart", "ti,omap4-uart"; 495 reg = <0x48424000 0x100>; 496 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 497 ti,hwmods = "uart9"; 498 clock-frequency = <48000000>; 499 status = "disabled"; 500 }; 501 502 uart10: serial@4ae2b000 { 503 compatible = "ti,dra742-uart", "ti,omap4-uart"; 504 reg = <0x4ae2b000 0x100>; 505 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 506 ti,hwmods = "uart10"; 507 clock-frequency = <48000000>; 508 status = "disabled"; 509 }; 510 511 mailbox1: mailbox@4a0f4000 { 512 compatible = "ti,omap4-mailbox"; 513 reg = <0x4a0f4000 0x200>; 514 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 517 ti,hwmods = "mailbox1"; 518 #mbox-cells = <1>; 519 ti,mbox-num-users = <3>; 520 ti,mbox-num-fifos = <8>; 521 status = "disabled"; 522 }; 523 524 mailbox2: mailbox@4883a000 { 525 compatible = "ti,omap4-mailbox"; 526 reg = <0x4883a000 0x200>; 527 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 531 ti,hwmods = "mailbox2"; 532 #mbox-cells = <1>; 533 ti,mbox-num-users = <4>; 534 ti,mbox-num-fifos = <12>; 535 status = "disabled"; 536 }; 537 538 mailbox3: mailbox@4883c000 { 539 compatible = "ti,omap4-mailbox"; 540 reg = <0x4883c000 0x200>; 541 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 545 ti,hwmods = "mailbox3"; 546 #mbox-cells = <1>; 547 ti,mbox-num-users = <4>; 548 ti,mbox-num-fifos = <12>; 549 status = "disabled"; 550 }; 551 552 mailbox4: mailbox@4883e000 { 553 compatible = "ti,omap4-mailbox"; 554 reg = <0x4883e000 0x200>; 555 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 559 ti,hwmods = "mailbox4"; 560 #mbox-cells = <1>; 561 ti,mbox-num-users = <4>; 562 ti,mbox-num-fifos = <12>; 563 status = "disabled"; 564 }; 565 566 mailbox5: mailbox@48840000 { 567 compatible = "ti,omap4-mailbox"; 568 reg = <0x48840000 0x200>; 569 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 573 ti,hwmods = "mailbox5"; 574 #mbox-cells = <1>; 575 ti,mbox-num-users = <4>; 576 ti,mbox-num-fifos = <12>; 577 status = "disabled"; 578 }; 579 580 mailbox6: mailbox@48842000 { 581 compatible = "ti,omap4-mailbox"; 582 reg = <0x48842000 0x200>; 583 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 587 ti,hwmods = "mailbox6"; 588 #mbox-cells = <1>; 589 ti,mbox-num-users = <4>; 590 ti,mbox-num-fifos = <12>; 591 status = "disabled"; 592 }; 593 594 mailbox7: mailbox@48844000 { 595 compatible = "ti,omap4-mailbox"; 596 reg = <0x48844000 0x200>; 597 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 601 ti,hwmods = "mailbox7"; 602 #mbox-cells = <1>; 603 ti,mbox-num-users = <4>; 604 ti,mbox-num-fifos = <12>; 605 status = "disabled"; 606 }; 607 608 mailbox8: mailbox@48846000 { 609 compatible = "ti,omap4-mailbox"; 610 reg = <0x48846000 0x200>; 611 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 615 ti,hwmods = "mailbox8"; 616 #mbox-cells = <1>; 617 ti,mbox-num-users = <4>; 618 ti,mbox-num-fifos = <12>; 619 status = "disabled"; 620 }; 621 622 mailbox9: mailbox@4885e000 { 623 compatible = "ti,omap4-mailbox"; 624 reg = <0x4885e000 0x200>; 625 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 629 ti,hwmods = "mailbox9"; 630 #mbox-cells = <1>; 631 ti,mbox-num-users = <4>; 632 ti,mbox-num-fifos = <12>; 633 status = "disabled"; 634 }; 635 636 mailbox10: mailbox@48860000 { 637 compatible = "ti,omap4-mailbox"; 638 reg = <0x48860000 0x200>; 639 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 643 ti,hwmods = "mailbox10"; 644 #mbox-cells = <1>; 645 ti,mbox-num-users = <4>; 646 ti,mbox-num-fifos = <12>; 647 status = "disabled"; 648 }; 649 650 mailbox11: mailbox@48862000 { 651 compatible = "ti,omap4-mailbox"; 652 reg = <0x48862000 0x200>; 653 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 657 ti,hwmods = "mailbox11"; 658 #mbox-cells = <1>; 659 ti,mbox-num-users = <4>; 660 ti,mbox-num-fifos = <12>; 661 status = "disabled"; 662 }; 663 664 mailbox12: mailbox@48864000 { 665 compatible = "ti,omap4-mailbox"; 666 reg = <0x48864000 0x200>; 667 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 671 ti,hwmods = "mailbox12"; 672 #mbox-cells = <1>; 673 ti,mbox-num-users = <4>; 674 ti,mbox-num-fifos = <12>; 675 status = "disabled"; 676 }; 677 678 mailbox13: mailbox@48802000 { 679 compatible = "ti,omap4-mailbox"; 680 reg = <0x48802000 0x200>; 681 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; 685 ti,hwmods = "mailbox13"; 686 #mbox-cells = <1>; 687 ti,mbox-num-users = <4>; 688 ti,mbox-num-fifos = <12>; 689 status = "disabled"; 690 }; 691 692 timer1: timer@4ae18000 { 693 compatible = "ti,omap5430-timer"; 694 reg = <0x4ae18000 0x80>; 695 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 696 ti,hwmods = "timer1"; 697 ti,timer-alwon; 698 }; 699 700 timer2: timer@48032000 { 701 compatible = "ti,omap5430-timer"; 702 reg = <0x48032000 0x80>; 703 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 704 ti,hwmods = "timer2"; 705 }; 706 707 timer3: timer@48034000 { 708 compatible = "ti,omap5430-timer"; 709 reg = <0x48034000 0x80>; 710 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 711 ti,hwmods = "timer3"; 712 }; 713 714 timer4: timer@48036000 { 715 compatible = "ti,omap5430-timer"; 716 reg = <0x48036000 0x80>; 717 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 718 ti,hwmods = "timer4"; 719 }; 720 721 timer5: timer@48820000 { 722 compatible = "ti,omap5430-timer"; 723 reg = <0x48820000 0x80>; 724 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 725 ti,hwmods = "timer5"; 726 }; 727 728 timer6: timer@48822000 { 729 compatible = "ti,omap5430-timer"; 730 reg = <0x48822000 0x80>; 731 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 732 ti,hwmods = "timer6"; 733 }; 734 735 timer7: timer@48824000 { 736 compatible = "ti,omap5430-timer"; 737 reg = <0x48824000 0x80>; 738 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 739 ti,hwmods = "timer7"; 740 }; 741 742 timer8: timer@48826000 { 743 compatible = "ti,omap5430-timer"; 744 reg = <0x48826000 0x80>; 745 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 746 ti,hwmods = "timer8"; 747 }; 748 749 timer9: timer@4803e000 { 750 compatible = "ti,omap5430-timer"; 751 reg = <0x4803e000 0x80>; 752 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 753 ti,hwmods = "timer9"; 754 }; 755 756 timer10: timer@48086000 { 757 compatible = "ti,omap5430-timer"; 758 reg = <0x48086000 0x80>; 759 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 760 ti,hwmods = "timer10"; 761 }; 762 763 timer11: timer@48088000 { 764 compatible = "ti,omap5430-timer"; 765 reg = <0x48088000 0x80>; 766 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 767 ti,hwmods = "timer11"; 768 }; 769 770 timer13: timer@48828000 { 771 compatible = "ti,omap5430-timer"; 772 reg = <0x48828000 0x80>; 773 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 774 ti,hwmods = "timer13"; 775 status = "disabled"; 776 }; 777 778 timer14: timer@4882a000 { 779 compatible = "ti,omap5430-timer"; 780 reg = <0x4882a000 0x80>; 781 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 782 ti,hwmods = "timer14"; 783 status = "disabled"; 784 }; 785 786 timer15: timer@4882c000 { 787 compatible = "ti,omap5430-timer"; 788 reg = <0x4882c000 0x80>; 789 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 790 ti,hwmods = "timer15"; 791 status = "disabled"; 792 }; 793 794 timer16: timer@4882e000 { 795 compatible = "ti,omap5430-timer"; 796 reg = <0x4882e000 0x80>; 797 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 798 ti,hwmods = "timer16"; 799 status = "disabled"; 800 }; 801 802 wdt2: wdt@4ae14000 { 803 compatible = "ti,omap3-wdt"; 804 reg = <0x4ae14000 0x80>; 805 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 806 ti,hwmods = "wd_timer2"; 807 }; 808 809 hwspinlock: spinlock@4a0f6000 { 810 compatible = "ti,omap4-hwspinlock"; 811 reg = <0x4a0f6000 0x1000>; 812 ti,hwmods = "spinlock"; 813 #hwlock-cells = <1>; 814 }; 815 816 dmm@4e000000 { 817 compatible = "ti,omap5-dmm"; 818 reg = <0x4e000000 0x800>; 819 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 820 ti,hwmods = "dmm"; 821 }; 822 823 i2c1: i2c@48070000 { 824 compatible = "ti,omap4-i2c"; 825 reg = <0x48070000 0x100>; 826 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 ti,hwmods = "i2c1"; 830 status = "disabled"; 831 }; 832 833 i2c2: i2c@48072000 { 834 compatible = "ti,omap4-i2c"; 835 reg = <0x48072000 0x100>; 836 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 ti,hwmods = "i2c2"; 840 status = "disabled"; 841 }; 842 843 i2c3: i2c@48060000 { 844 compatible = "ti,omap4-i2c"; 845 reg = <0x48060000 0x100>; 846 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 ti,hwmods = "i2c3"; 850 status = "disabled"; 851 }; 852 853 i2c4: i2c@4807a000 { 854 compatible = "ti,omap4-i2c"; 855 reg = <0x4807a000 0x100>; 856 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 857 #address-cells = <1>; 858 #size-cells = <0>; 859 ti,hwmods = "i2c4"; 860 status = "disabled"; 861 }; 862 863 i2c5: i2c@4807c000 { 864 compatible = "ti,omap4-i2c"; 865 reg = <0x4807c000 0x100>; 866 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 ti,hwmods = "i2c5"; 870 status = "disabled"; 871 }; 872 873 mmc1: mmc@4809c000 { 874 compatible = "ti,omap4-hsmmc"; 875 reg = <0x4809c000 0x400>; 876 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 877 ti,hwmods = "mmc1"; 878 ti,dual-volt; 879 ti,needs-special-reset; 880 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>; 881 dma-names = "tx", "rx"; 882 status = "disabled"; 883 pbias-supply = <&pbias_mmc_reg>; 884 }; 885 886 mmc2: mmc@480b4000 { 887 compatible = "ti,omap4-hsmmc"; 888 reg = <0x480b4000 0x400>; 889 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 890 ti,hwmods = "mmc2"; 891 ti,needs-special-reset; 892 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; 893 dma-names = "tx", "rx"; 894 status = "disabled"; 895 }; 896 897 mmc3: mmc@480ad000 { 898 compatible = "ti,omap4-hsmmc"; 899 reg = <0x480ad000 0x400>; 900 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 901 ti,hwmods = "mmc3"; 902 ti,needs-special-reset; 903 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; 904 dma-names = "tx", "rx"; 905 status = "disabled"; 906 }; 907 908 mmc4: mmc@480d1000 { 909 compatible = "ti,omap4-hsmmc"; 910 reg = <0x480d1000 0x400>; 911 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 912 ti,hwmods = "mmc4"; 913 ti,needs-special-reset; 914 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; 915 dma-names = "tx", "rx"; 916 status = "disabled"; 917 }; 918 919 mmu0_dsp1: mmu@40d01000 { 920 compatible = "ti,dra7-dsp-iommu"; 921 reg = <0x40d01000 0x100>; 922 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 923 ti,hwmods = "mmu0_dsp1"; 924 #iommu-cells = <0>; 925 ti,syscon-mmuconfig = <&dsp1_system 0x0>; 926 status = "disabled"; 927 }; 928 929 mmu1_dsp1: mmu@40d02000 { 930 compatible = "ti,dra7-dsp-iommu"; 931 reg = <0x40d02000 0x100>; 932 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 933 ti,hwmods = "mmu1_dsp1"; 934 #iommu-cells = <0>; 935 ti,syscon-mmuconfig = <&dsp1_system 0x1>; 936 status = "disabled"; 937 }; 938 939 mmu_ipu1: mmu@58882000 { 940 compatible = "ti,dra7-iommu"; 941 reg = <0x58882000 0x100>; 942 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 943 ti,hwmods = "mmu_ipu1"; 944 #iommu-cells = <0>; 945 ti,iommu-bus-err-back; 946 status = "disabled"; 947 }; 948 949 mmu_ipu2: mmu@55082000 { 950 compatible = "ti,dra7-iommu"; 951 reg = <0x55082000 0x100>; 952 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 953 ti,hwmods = "mmu_ipu2"; 954 #iommu-cells = <0>; 955 ti,iommu-bus-err-back; 956 status = "disabled"; 957 }; 958 959 abb_mpu: regulator-abb-mpu { 960 compatible = "ti,abb-v3"; 961 regulator-name = "abb_mpu"; 962 #address-cells = <0>; 963 #size-cells = <0>; 964 clocks = <&sys_clkin1>; 965 ti,settling-time = <50>; 966 ti,clock-cycles = <16>; 967 968 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 969 <0x4ae06014 0x4>, <0x4a003b20 0xc>, 970 <0x4ae0c158 0x4>; 971 reg-names = "setup-address", "control-address", 972 "int-address", "efuse-address", 973 "ldo-address"; 974 ti,tranxdone-status-mask = <0x80>; 975 /* LDOVBBMPU_FBB_MUX_CTRL */ 976 ti,ldovbb-override-mask = <0x400>; 977 /* LDOVBBMPU_FBB_VSET_OUT */ 978 ti,ldovbb-vset-mask = <0x1F>; 979 980 /* 981 * NOTE: only FBB mode used but actual vset will 982 * determine final biasing 983 */ 984 ti,abb_info = < 985 /*uV ABB efuse rbb_m fbb_m vset_m*/ 986 1060000 0 0x0 0 0x02000000 0x01F00000 987 1160000 0 0x4 0 0x02000000 0x01F00000 988 1210000 0 0x8 0 0x02000000 0x01F00000 989 >; 990 }; 991 992 abb_ivahd: regulator-abb-ivahd { 993 compatible = "ti,abb-v3"; 994 regulator-name = "abb_ivahd"; 995 #address-cells = <0>; 996 #size-cells = <0>; 997 clocks = <&sys_clkin1>; 998 ti,settling-time = <50>; 999 ti,clock-cycles = <16>; 1000 1001 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 1002 <0x4ae06010 0x4>, <0x4a0025cc 0xc>, 1003 <0x4a002470 0x4>; 1004 reg-names = "setup-address", "control-address", 1005 "int-address", "efuse-address", 1006 "ldo-address"; 1007 ti,tranxdone-status-mask = <0x40000000>; 1008 /* LDOVBBIVA_FBB_MUX_CTRL */ 1009 ti,ldovbb-override-mask = <0x400>; 1010 /* LDOVBBIVA_FBB_VSET_OUT */ 1011 ti,ldovbb-vset-mask = <0x1F>; 1012 1013 /* 1014 * NOTE: only FBB mode used but actual vset will 1015 * determine final biasing 1016 */ 1017 ti,abb_info = < 1018 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1019 1055000 0 0x0 0 0x02000000 0x01F00000 1020 1150000 0 0x4 0 0x02000000 0x01F00000 1021 1250000 0 0x8 0 0x02000000 0x01F00000 1022 >; 1023 }; 1024 1025 abb_dspeve: regulator-abb-dspeve { 1026 compatible = "ti,abb-v3"; 1027 regulator-name = "abb_dspeve"; 1028 #address-cells = <0>; 1029 #size-cells = <0>; 1030 clocks = <&sys_clkin1>; 1031 ti,settling-time = <50>; 1032 ti,clock-cycles = <16>; 1033 1034 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 1035 <0x4ae06010 0x4>, <0x4a0025e0 0xc>, 1036 <0x4a00246c 0x4>; 1037 reg-names = "setup-address", "control-address", 1038 "int-address", "efuse-address", 1039 "ldo-address"; 1040 ti,tranxdone-status-mask = <0x20000000>; 1041 /* LDOVBBDSPEVE_FBB_MUX_CTRL */ 1042 ti,ldovbb-override-mask = <0x400>; 1043 /* LDOVBBDSPEVE_FBB_VSET_OUT */ 1044 ti,ldovbb-vset-mask = <0x1F>; 1045 1046 /* 1047 * NOTE: only FBB mode used but actual vset will 1048 * determine final biasing 1049 */ 1050 ti,abb_info = < 1051 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1052 1055000 0 0x0 0 0x02000000 0x01F00000 1053 1150000 0 0x4 0 0x02000000 0x01F00000 1054 1250000 0 0x8 0 0x02000000 0x01F00000 1055 >; 1056 }; 1057 1058 abb_gpu: regulator-abb-gpu { 1059 compatible = "ti,abb-v3"; 1060 regulator-name = "abb_gpu"; 1061 #address-cells = <0>; 1062 #size-cells = <0>; 1063 clocks = <&sys_clkin1>; 1064 ti,settling-time = <50>; 1065 ti,clock-cycles = <16>; 1066 1067 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 1068 <0x4ae06010 0x4>, <0x4a003b08 0xc>, 1069 <0x4ae0c154 0x4>; 1070 reg-names = "setup-address", "control-address", 1071 "int-address", "efuse-address", 1072 "ldo-address"; 1073 ti,tranxdone-status-mask = <0x10000000>; 1074 /* LDOVBBGPU_FBB_MUX_CTRL */ 1075 ti,ldovbb-override-mask = <0x400>; 1076 /* LDOVBBGPU_FBB_VSET_OUT */ 1077 ti,ldovbb-vset-mask = <0x1F>; 1078 1079 /* 1080 * NOTE: only FBB mode used but actual vset will 1081 * determine final biasing 1082 */ 1083 ti,abb_info = < 1084 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1085 1090000 0 0x0 0 0x02000000 0x01F00000 1086 1210000 0 0x4 0 0x02000000 0x01F00000 1087 1280000 0 0x8 0 0x02000000 0x01F00000 1088 >; 1089 }; 1090 1091 mcspi1: spi@48098000 { 1092 compatible = "ti,omap4-mcspi"; 1093 reg = <0x48098000 0x200>; 1094 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 ti,hwmods = "mcspi1"; 1098 ti,spi-num-cs = <4>; 1099 dmas = <&sdma_xbar 35>, 1100 <&sdma_xbar 36>, 1101 <&sdma_xbar 37>, 1102 <&sdma_xbar 38>, 1103 <&sdma_xbar 39>, 1104 <&sdma_xbar 40>, 1105 <&sdma_xbar 41>, 1106 <&sdma_xbar 42>; 1107 dma-names = "tx0", "rx0", "tx1", "rx1", 1108 "tx2", "rx2", "tx3", "rx3"; 1109 status = "disabled"; 1110 }; 1111 1112 mcspi2: spi@4809a000 { 1113 compatible = "ti,omap4-mcspi"; 1114 reg = <0x4809a000 0x200>; 1115 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 ti,hwmods = "mcspi2"; 1119 ti,spi-num-cs = <2>; 1120 dmas = <&sdma_xbar 43>, 1121 <&sdma_xbar 44>, 1122 <&sdma_xbar 45>, 1123 <&sdma_xbar 46>; 1124 dma-names = "tx0", "rx0", "tx1", "rx1"; 1125 status = "disabled"; 1126 }; 1127 1128 mcspi3: spi@480b8000 { 1129 compatible = "ti,omap4-mcspi"; 1130 reg = <0x480b8000 0x200>; 1131 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 ti,hwmods = "mcspi3"; 1135 ti,spi-num-cs = <2>; 1136 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; 1137 dma-names = "tx0", "rx0"; 1138 status = "disabled"; 1139 }; 1140 1141 mcspi4: spi@480ba000 { 1142 compatible = "ti,omap4-mcspi"; 1143 reg = <0x480ba000 0x200>; 1144 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 ti,hwmods = "mcspi4"; 1148 ti,spi-num-cs = <1>; 1149 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; 1150 dma-names = "tx0", "rx0"; 1151 status = "disabled"; 1152 }; 1153 1154 qspi: qspi@4b300000 { 1155 compatible = "ti,dra7xxx-qspi"; 1156 reg = <0x4b300000 0x100>; 1157 reg-names = "qspi_base"; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 ti,hwmods = "qspi"; 1161 clocks = <&qspi_gfclk_div>; 1162 clock-names = "fck"; 1163 num-cs = <4>; 1164 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1165 status = "disabled"; 1166 }; 1167 1168 omap_control_sata: control-phy@4a002374 { 1169 compatible = "ti,control-phy-pipe3"; 1170 reg = <0x4a002374 0x4>; 1171 reg-names = "power"; 1172 clocks = <&sys_clkin1>; 1173 clock-names = "sysclk"; 1174 }; 1175 1176 /* OCP2SCP3 */ 1177 ocp2scp@4a090000 { 1178 compatible = "ti,omap-ocp2scp"; 1179 #address-cells = <1>; 1180 #size-cells = <1>; 1181 ranges; 1182 reg = <0x4a090000 0x20>; 1183 ti,hwmods = "ocp2scp3"; 1184 sata_phy: phy@4A096000 { 1185 compatible = "ti,phy-pipe3-sata"; 1186 reg = <0x4A096000 0x80>, /* phy_rx */ 1187 <0x4A096400 0x64>, /* phy_tx */ 1188 <0x4A096800 0x40>; /* pll_ctrl */ 1189 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1190 ctrl-module = <&omap_control_sata>; 1191 clocks = <&sys_clkin1>, <&sata_ref_clk>; 1192 clock-names = "sysclk", "refclk"; 1193 syscon-pllreset = <&scm_conf 0x3fc>; 1194 #phy-cells = <0>; 1195 }; 1196 1197 pcie1_phy: pciephy@4a094000 { 1198 compatible = "ti,phy-pipe3-pcie"; 1199 reg = <0x4a094000 0x80>, /* phy_rx */ 1200 <0x4a094400 0x64>; /* phy_tx */ 1201 reg-names = "phy_rx", "phy_tx"; 1202 ctrl-module = <&omap_control_pcie1phy>; 1203 clocks = <&dpll_pcie_ref_ck>, 1204 <&dpll_pcie_ref_m2ldo_ck>, 1205 <&optfclk_pciephy1_32khz>, 1206 <&optfclk_pciephy1_clk>, 1207 <&optfclk_pciephy1_div_clk>, 1208 <&optfclk_pciephy_div>; 1209 clock-names = "dpll_ref", "dpll_ref_m2", 1210 "wkupclk", "refclk", 1211 "div-clk", "phy-div"; 1212 #phy-cells = <0>; 1213 }; 1214 1215 pcie2_phy: pciephy@4a095000 { 1216 compatible = "ti,phy-pipe3-pcie"; 1217 reg = <0x4a095000 0x80>, /* phy_rx */ 1218 <0x4a095400 0x64>; /* phy_tx */ 1219 reg-names = "phy_rx", "phy_tx"; 1220 ctrl-module = <&omap_control_pcie2phy>; 1221 clocks = <&dpll_pcie_ref_ck>, 1222 <&dpll_pcie_ref_m2ldo_ck>, 1223 <&optfclk_pciephy2_32khz>, 1224 <&optfclk_pciephy2_clk>, 1225 <&optfclk_pciephy2_div_clk>, 1226 <&optfclk_pciephy_div>; 1227 clock-names = "dpll_ref", "dpll_ref_m2", 1228 "wkupclk", "refclk", 1229 "div-clk", "phy-div"; 1230 #phy-cells = <0>; 1231 status = "disabled"; 1232 }; 1233 }; 1234 1235 sata: sata@4a141100 { 1236 compatible = "snps,dwc-ahci"; 1237 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 1238 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1239 phys = <&sata_phy>; 1240 phy-names = "sata-phy"; 1241 clocks = <&sata_ref_clk>; 1242 ti,hwmods = "sata"; 1243 }; 1244 1245 omap_control_pcie1phy: control-phy@0x4a003c40 { 1246 compatible = "ti,control-phy-pcie"; 1247 reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; 1248 reg-names = "power", "control_sma", "pcie_pcs"; 1249 clocks = <&sys_clkin1>; 1250 clock-names = "sysclk"; 1251 }; 1252 1253 omap_control_pcie2phy: control-pcie@0x4a003c44 { 1254 compatible = "ti,control-phy-pcie"; 1255 reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>; 1256 reg-names = "power", "control_sma", "pcie_pcs"; 1257 clocks = <&sys_clkin1>; 1258 clock-names = "sysclk"; 1259 status = "disabled"; 1260 }; 1261 1262 rtc: rtc@48838000 { 1263 compatible = "ti,am3352-rtc"; 1264 reg = <0x48838000 0x100>; 1265 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 1267 ti,hwmods = "rtcss"; 1268 clocks = <&sys_32k_ck>; 1269 }; 1270 1271 omap_control_usb2phy1: control-phy@4a002300 { 1272 compatible = "ti,control-phy-usb2"; 1273 reg = <0x4a002300 0x4>; 1274 reg-names = "power"; 1275 }; 1276 1277 omap_control_usb3phy1: control-phy@4a002370 { 1278 compatible = "ti,control-phy-pipe3"; 1279 reg = <0x4a002370 0x4>; 1280 reg-names = "power"; 1281 }; 1282 1283 omap_control_usb2phy2: control-phy@0x4a002e74 { 1284 compatible = "ti,control-phy-usb2-dra7"; 1285 reg = <0x4a002e74 0x4>; 1286 reg-names = "power"; 1287 }; 1288 1289 /* OCP2SCP1 */ 1290 ocp2scp@4a080000 { 1291 compatible = "ti,omap-ocp2scp"; 1292 #address-cells = <1>; 1293 #size-cells = <1>; 1294 ranges; 1295 reg = <0x4a080000 0x20>; 1296 ti,hwmods = "ocp2scp1"; 1297 1298 usb2_phy1: phy@4a084000 { 1299 compatible = "ti,omap-usb2"; 1300 reg = <0x4a084000 0x400>; 1301 ctrl-module = <&omap_control_usb2phy1>; 1302 clocks = <&usb_phy1_always_on_clk32k>, 1303 <&usb_otg_ss1_refclk960m>; 1304 clock-names = "wkupclk", 1305 "refclk"; 1306 #phy-cells = <0>; 1307 }; 1308 1309 usb2_phy2: phy@4a085000 { 1310 compatible = "ti,omap-usb2"; 1311 reg = <0x4a085000 0x400>; 1312 ctrl-module = <&omap_control_usb2phy2>; 1313 clocks = <&usb_phy2_always_on_clk32k>, 1314 <&usb_otg_ss2_refclk960m>; 1315 clock-names = "wkupclk", 1316 "refclk"; 1317 #phy-cells = <0>; 1318 }; 1319 1320 usb3_phy1: phy@4a084400 { 1321 compatible = "ti,omap-usb3"; 1322 reg = <0x4a084400 0x80>, 1323 <0x4a084800 0x64>, 1324 <0x4a084c00 0x40>; 1325 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1326 ctrl-module = <&omap_control_usb3phy1>; 1327 clocks = <&usb_phy3_always_on_clk32k>, 1328 <&sys_clkin1>, 1329 <&usb_otg_ss1_refclk960m>; 1330 clock-names = "wkupclk", 1331 "sysclk", 1332 "refclk"; 1333 #phy-cells = <0>; 1334 }; 1335 }; 1336 1337 omap_dwc3_1: omap_dwc3_1@48880000 { 1338 compatible = "ti,dwc3"; 1339 ti,hwmods = "usb_otg_ss1"; 1340 reg = <0x48880000 0x10000>; 1341 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1342 #address-cells = <1>; 1343 #size-cells = <1>; 1344 utmi-mode = <2>; 1345 ranges; 1346 usb1: usb@48890000 { 1347 compatible = "snps,dwc3"; 1348 reg = <0x48890000 0x17000>; 1349 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1352 interrupt-names = "peripheral", 1353 "host", 1354 "otg"; 1355 phys = <&usb2_phy1>, <&usb3_phy1>; 1356 phy-names = "usb2-phy", "usb3-phy"; 1357 tx-fifo-resize; 1358 maximum-speed = "super-speed"; 1359 dr_mode = "otg"; 1360 snps,dis_u3_susphy_quirk; 1361 snps,dis_u2_susphy_quirk; 1362 }; 1363 }; 1364 1365 omap_dwc3_2: omap_dwc3_2@488c0000 { 1366 compatible = "ti,dwc3"; 1367 ti,hwmods = "usb_otg_ss2"; 1368 reg = <0x488c0000 0x10000>; 1369 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1370 #address-cells = <1>; 1371 #size-cells = <1>; 1372 utmi-mode = <2>; 1373 ranges; 1374 usb2: usb@488d0000 { 1375 compatible = "snps,dwc3"; 1376 reg = <0x488d0000 0x17000>; 1377 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1380 interrupt-names = "peripheral", 1381 "host", 1382 "otg"; 1383 phys = <&usb2_phy2>; 1384 phy-names = "usb2-phy"; 1385 tx-fifo-resize; 1386 maximum-speed = "high-speed"; 1387 dr_mode = "otg"; 1388 snps,dis_u3_susphy_quirk; 1389 snps,dis_u2_susphy_quirk; 1390 }; 1391 }; 1392 1393 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 1394 omap_dwc3_3: omap_dwc3_3@48900000 { 1395 compatible = "ti,dwc3"; 1396 ti,hwmods = "usb_otg_ss3"; 1397 reg = <0x48900000 0x10000>; 1398 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1399 #address-cells = <1>; 1400 #size-cells = <1>; 1401 utmi-mode = <2>; 1402 ranges; 1403 status = "disabled"; 1404 usb3: usb@48910000 { 1405 compatible = "snps,dwc3"; 1406 reg = <0x48910000 0x17000>; 1407 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1410 interrupt-names = "peripheral", 1411 "host", 1412 "otg"; 1413 tx-fifo-resize; 1414 maximum-speed = "high-speed"; 1415 dr_mode = "otg"; 1416 snps,dis_u3_susphy_quirk; 1417 snps,dis_u2_susphy_quirk; 1418 }; 1419 }; 1420 1421 elm: elm@48078000 { 1422 compatible = "ti,am3352-elm"; 1423 reg = <0x48078000 0xfc0>; /* device IO registers */ 1424 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1425 ti,hwmods = "elm"; 1426 status = "disabled"; 1427 }; 1428 1429 gpmc: gpmc@50000000 { 1430 compatible = "ti,am3352-gpmc"; 1431 ti,hwmods = "gpmc"; 1432 reg = <0x50000000 0x37c>; /* device IO registers */ 1433 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1434 gpmc,num-cs = <8>; 1435 gpmc,num-waitpins = <2>; 1436 #address-cells = <2>; 1437 #size-cells = <1>; 1438 status = "disabled"; 1439 }; 1440 1441 atl: atl@4843c000 { 1442 compatible = "ti,dra7-atl"; 1443 reg = <0x4843c000 0x3ff>; 1444 ti,hwmods = "atl"; 1445 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, 1446 <&atl_clkin2_ck>, <&atl_clkin3_ck>; 1447 clocks = <&atl_gfclk_mux>; 1448 clock-names = "fck"; 1449 status = "disabled"; 1450 }; 1451 1452 mcasp3: mcasp@48468000 { 1453 compatible = "ti,dra7-mcasp-audio"; 1454 ti,hwmods = "mcasp3"; 1455 reg = <0x48468000 0x2000>; 1456 reg-names = "mpu"; 1457 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1459 interrupt-names = "tx", "rx"; 1460 dmas = <&sdma_xbar 133>, <&sdma_xbar 132>; 1461 dma-names = "tx", "rx"; 1462 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>; 1463 clock-names = "fck", "ahclkx"; 1464 status = "disabled"; 1465 }; 1466 1467 crossbar_mpu: crossbar@4a002a48 { 1468 compatible = "ti,irq-crossbar"; 1469 reg = <0x4a002a48 0x130>; 1470 interrupt-controller; 1471 interrupt-parent = <&wakeupgen>; 1472 #interrupt-cells = <3>; 1473 ti,max-irqs = <160>; 1474 ti,max-crossbar-sources = <MAX_SOURCES>; 1475 ti,reg-size = <2>; 1476 ti,irqs-reserved = <0 1 2 3 5 6 131 132>; 1477 ti,irqs-skip = <10 133 139 140>; 1478 ti,irqs-safe-map = <0>; 1479 }; 1480 1481 mac: ethernet@48484000 { 1482 compatible = "ti,dra7-cpsw","ti,cpsw"; 1483 ti,hwmods = "gmac"; 1484 clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; 1485 clock-names = "fck", "cpts"; 1486 cpdma_channels = <8>; 1487 ale_entries = <1024>; 1488 bd_ram_size = <0x2000>; 1489 no_bd_ram = <0>; 1490 rx_descs = <64>; 1491 mac_control = <0x20>; 1492 slaves = <2>; 1493 active_slave = <0>; 1494 cpts_clock_mult = <0x80000000>; 1495 cpts_clock_shift = <29>; 1496 reg = <0x48484000 0x1000 1497 0x48485200 0x2E00>; 1498 #address-cells = <1>; 1499 #size-cells = <1>; 1500 1501 /* 1502 * Do not allow gating of cpsw clock as workaround 1503 * for errata i877. Keeping internal clock disabled 1504 * causes the device switching characteristics 1505 * to degrade over time and eventually fail to meet 1506 * the data manual delay time/skew specs. 1507 */ 1508 ti,no-idle; 1509 1510 /* 1511 * rx_thresh_pend 1512 * rx_pend 1513 * tx_pend 1514 * misc_pend 1515 */ 1516 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 1520 ranges; 1521 syscon = <&scm_conf>; 1522 status = "disabled"; 1523 1524 davinci_mdio: mdio@48485000 { 1525 compatible = "ti,davinci_mdio"; 1526 #address-cells = <1>; 1527 #size-cells = <0>; 1528 ti,hwmods = "davinci_mdio"; 1529 bus_freq = <1000000>; 1530 reg = <0x48485000 0x100>; 1531 }; 1532 1533 cpsw_emac0: slave@48480200 { 1534 /* Filled in by U-Boot */ 1535 mac-address = [ 00 00 00 00 00 00 ]; 1536 }; 1537 1538 cpsw_emac1: slave@48480300 { 1539 /* Filled in by U-Boot */ 1540 mac-address = [ 00 00 00 00 00 00 ]; 1541 }; 1542 1543 phy_sel: cpsw-phy-sel@4a002554 { 1544 compatible = "ti,dra7xx-cpsw-phy-sel"; 1545 reg= <0x4a002554 0x4>; 1546 reg-names = "gmii-sel"; 1547 }; 1548 }; 1549 1550 dcan1: can@481cc000 { 1551 compatible = "ti,dra7-d_can"; 1552 ti,hwmods = "dcan1"; 1553 reg = <0x4ae3c000 0x2000>; 1554 syscon-raminit = <&scm_conf 0x558 0>; 1555 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1556 clocks = <&dcan1_sys_clk_mux>; 1557 status = "disabled"; 1558 }; 1559 1560 dcan2: can@481d0000 { 1561 compatible = "ti,dra7-d_can"; 1562 ti,hwmods = "dcan2"; 1563 reg = <0x48480000 0x2000>; 1564 syscon-raminit = <&scm_conf 0x558 1>; 1565 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1566 clocks = <&sys_clkin1>; 1567 status = "disabled"; 1568 }; 1569 1570 dss: dss@58000000 { 1571 compatible = "ti,dra7-dss"; 1572 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ 1573 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ 1574 status = "disabled"; 1575 ti,hwmods = "dss_core"; 1576 /* CTRL_CORE_DSS_PLL_CONTROL */ 1577 syscon-pll-ctrl = <&scm_conf 0x538>; 1578 #address-cells = <1>; 1579 #size-cells = <1>; 1580 ranges; 1581 1582 dispc@58001000 { 1583 compatible = "ti,dra7-dispc"; 1584 reg = <0x58001000 0x1000>; 1585 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1586 ti,hwmods = "dss_dispc"; 1587 clocks = <&dss_dss_clk>; 1588 clock-names = "fck"; 1589 /* CTRL_CORE_SMA_SW_1 */ 1590 syscon-pol = <&scm_conf 0x534>; 1591 }; 1592 1593 hdmi: encoder@58060000 { 1594 compatible = "ti,dra7-hdmi"; 1595 reg = <0x58040000 0x200>, 1596 <0x58040200 0x80>, 1597 <0x58040300 0x80>, 1598 <0x58060000 0x19000>; 1599 reg-names = "wp", "pll", "phy", "core"; 1600 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1601 status = "disabled"; 1602 ti,hwmods = "dss_hdmi"; 1603 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; 1604 clock-names = "fck", "sys_clk"; 1605 }; 1606 }; 1607 }; 1608 1609 thermal_zones: thermal-zones { 1610 #include "omap4-cpu-thermal.dtsi" 1611 #include "omap5-gpu-thermal.dtsi" 1612 #include "omap5-core-thermal.dtsi" 1613 }; 1614 1615}; 1616 1617&cpu_thermal { 1618 polling-delay = <500>; /* milliseconds */ 1619}; 1620 1621/include/ "dra7xx-clocks.dtsi" 1622