1/* 2 * Copyright (C) 2014 Antoine T��nart <antoine.tenart@free-electrons.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 * 13 * Or, alternatively, 14 * 15 * b) Permission is hereby granted, free of charge, to any person 16 * obtaining a copy of this software and associated documentation 17 * files (the "Software"), to deal in the Software without 18 * restriction, including without limitation the rights to use, 19 * copy, modify, merge, publish, distribute, sublicense, and/or 20 * sell copies of the Software, and to permit persons to whom the 21 * Software is furnished to do so, subject to the following 22 * conditions: 23 * 24 * The above copyright notice and this permission notice shall be 25 * included in all copies or substantial portions of the Software. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 29 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 31 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 32 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 33 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 34 * OTHER DEALINGS IN THE SOFTWARE. 35 */ 36 37#include <dt-bindings/clock/berlin2q.h> 38#include <dt-bindings/interrupt-controller/arm-gic.h> 39 40#include "skeleton.dtsi" 41 42/ { 43 model = "Marvell Armada 1500 pro (BG2-Q) SoC"; 44 compatible = "marvell,berlin2q", "marvell,berlin"; 45 46 aliases { 47 serial0 = &uart0; 48 serial1 = &uart1; 49 }; 50 51 cpus { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 enable-method = "marvell,berlin-smp"; 55 56 cpu@0 { 57 compatible = "arm,cortex-a9"; 58 device_type = "cpu"; 59 next-level-cache = <&l2>; 60 reg = <0>; 61 62 clocks = <&chip_clk CLKID_CPU>; 63 clock-latency = <100000>; 64 /* Can be modified by the bootloader */ 65 operating-points = < 66 /* kHz uV */ 67 1200000 1200000 68 1000000 1200000 69 800000 1200000 70 600000 1200000 71 >; 72 }; 73 74 cpu@1 { 75 compatible = "arm,cortex-a9"; 76 device_type = "cpu"; 77 next-level-cache = <&l2>; 78 reg = <1>; 79 }; 80 81 cpu@2 { 82 compatible = "arm,cortex-a9"; 83 device_type = "cpu"; 84 next-level-cache = <&l2>; 85 reg = <2>; 86 }; 87 88 cpu@3 { 89 compatible = "arm,cortex-a9"; 90 device_type = "cpu"; 91 next-level-cache = <&l2>; 92 reg = <3>; 93 }; 94 }; 95 96 refclk: oscillator { 97 compatible = "fixed-clock"; 98 #clock-cells = <0>; 99 clock-frequency = <25000000>; 100 }; 101 102 soc { 103 compatible = "simple-bus"; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 107 ranges = <0 0xf7000000 0x1000000>; 108 interrupt-parent = <&gic>; 109 110 pmu { 111 compatible = "arm,cortex-a9-pmu"; 112 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 116 }; 117 118 sdhci0: sdhci@ab0000 { 119 compatible = "mrvl,pxav3-mmc"; 120 reg = <0xab0000 0x200>; 121 clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; 122 clock-names = "io", "core"; 123 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 124 status = "disabled"; 125 }; 126 127 sdhci1: sdhci@ab0800 { 128 compatible = "mrvl,pxav3-mmc"; 129 reg = <0xab0800 0x200>; 130 clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; 131 clock-names = "io", "core"; 132 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 133 status = "disabled"; 134 }; 135 136 sdhci2: sdhci@ab1000 { 137 compatible = "mrvl,pxav3-mmc"; 138 reg = <0xab1000 0x200>; 139 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>; 141 clock-names = "io", "core"; 142 status = "disabled"; 143 }; 144 145 l2: l2-cache-controller@ac0000 { 146 compatible = "arm,pl310-cache"; 147 reg = <0xac0000 0x1000>; 148 cache-level = <2>; 149 arm,data-latency = <2 2 2>; 150 arm,tag-latency = <2 2 2>; 151 }; 152 153 scu: snoop-control-unit@ad0000 { 154 compatible = "arm,cortex-a9-scu"; 155 reg = <0xad0000 0x58>; 156 }; 157 158 local-timer@ad0600 { 159 compatible = "arm,cortex-a9-twd-timer"; 160 reg = <0xad0600 0x20>; 161 clocks = <&chip_clk CLKID_TWD>; 162 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 163 }; 164 165 gic: interrupt-controller@ad1000 { 166 compatible = "arm,cortex-a9-gic"; 167 reg = <0xad1000 0x1000>, <0xad0100 0x100>; 168 interrupt-controller; 169 #interrupt-cells = <3>; 170 }; 171 172 usb_phy2: phy@a2f400 { 173 compatible = "marvell,berlin2cd-usb-phy"; 174 reg = <0xa2f400 0x128>; 175 #phy-cells = <0>; 176 resets = <&chip_rst 0x104 14>; 177 status = "disabled"; 178 }; 179 180 usb2: usb@a30000 { 181 compatible = "chipidea,usb2"; 182 reg = <0xa30000 0x10000>; 183 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&chip_clk CLKID_USB2>; 185 phys = <&usb_phy2>; 186 phy-names = "usb-phy"; 187 status = "disabled"; 188 }; 189 190 usb_phy0: phy@b74000 { 191 compatible = "marvell,berlin2cd-usb-phy"; 192 reg = <0xb74000 0x128>; 193 #phy-cells = <0>; 194 resets = <&chip_rst 0x104 12>; 195 status = "disabled"; 196 }; 197 198 usb_phy1: phy@b78000 { 199 compatible = "marvell,berlin2cd-usb-phy"; 200 reg = <0xb78000 0x128>; 201 #phy-cells = <0>; 202 resets = <&chip_rst 0x104 13>; 203 status = "disabled"; 204 }; 205 206 eth0: ethernet@b90000 { 207 compatible = "marvell,pxa168-eth"; 208 reg = <0xb90000 0x10000>; 209 clocks = <&chip_clk CLKID_GETH0>; 210 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 211 /* set by bootloader */ 212 local-mac-address = [00 00 00 00 00 00]; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 phy-connection-type = "mii"; 216 phy-handle = <ðphy0>; 217 status = "disabled"; 218 219 ethphy0: ethernet-phy@0 { 220 reg = <0>; 221 }; 222 }; 223 224 cpu-ctrl@dd0000 { 225 compatible = "marvell,berlin-cpu-ctrl"; 226 reg = <0xdd0000 0x10000>; 227 }; 228 229 apb@e80000 { 230 compatible = "simple-bus"; 231 #address-cells = <1>; 232 #size-cells = <1>; 233 234 ranges = <0 0xe80000 0x10000>; 235 interrupt-parent = <&aic>; 236 237 gpio0: gpio@0400 { 238 compatible = "snps,dw-apb-gpio"; 239 reg = <0x0400 0x400>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 243 porta: gpio-port@0 { 244 compatible = "snps,dw-apb-gpio-port"; 245 gpio-controller; 246 #gpio-cells = <2>; 247 snps,nr-gpios = <32>; 248 reg = <0>; 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 interrupts = <0>; 252 }; 253 }; 254 255 gpio1: gpio@0800 { 256 compatible = "snps,dw-apb-gpio"; 257 reg = <0x0800 0x400>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 261 portb: gpio-port@1 { 262 compatible = "snps,dw-apb-gpio-port"; 263 gpio-controller; 264 #gpio-cells = <2>; 265 snps,nr-gpios = <32>; 266 reg = <0>; 267 interrupt-controller; 268 #interrupt-cells = <2>; 269 interrupts = <1>; 270 }; 271 }; 272 273 gpio2: gpio@0c00 { 274 compatible = "snps,dw-apb-gpio"; 275 reg = <0x0c00 0x400>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 279 portc: gpio-port@2 { 280 compatible = "snps,dw-apb-gpio-port"; 281 gpio-controller; 282 #gpio-cells = <2>; 283 snps,nr-gpios = <32>; 284 reg = <0>; 285 interrupt-controller; 286 #interrupt-cells = <2>; 287 interrupts = <2>; 288 }; 289 }; 290 291 gpio3: gpio@1000 { 292 compatible = "snps,dw-apb-gpio"; 293 reg = <0x1000 0x400>; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 297 portd: gpio-port@3 { 298 compatible = "snps,dw-apb-gpio-port"; 299 gpio-controller; 300 #gpio-cells = <2>; 301 snps,nr-gpios = <32>; 302 reg = <0>; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 interrupts = <3>; 306 }; 307 }; 308 309 i2c0: i2c@1400 { 310 compatible = "snps,designware-i2c"; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 reg = <0x1400 0x100>; 314 interrupt-parent = <&aic>; 315 interrupts = <4>; 316 clocks = <&chip_clk CLKID_CFG>; 317 pinctrl-0 = <&twsi0_pmux>; 318 pinctrl-names = "default"; 319 status = "disabled"; 320 }; 321 322 i2c1: i2c@1800 { 323 compatible = "snps,designware-i2c"; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 reg = <0x1800 0x100>; 327 interrupt-parent = <&aic>; 328 interrupts = <5>; 329 clocks = <&chip_clk CLKID_CFG>; 330 pinctrl-0 = <&twsi1_pmux>; 331 pinctrl-names = "default"; 332 status = "disabled"; 333 }; 334 335 timer0: timer@2c00 { 336 compatible = "snps,dw-apb-timer"; 337 reg = <0x2c00 0x14>; 338 clocks = <&chip_clk CLKID_CFG>; 339 clock-names = "timer"; 340 interrupts = <8>; 341 }; 342 343 timer1: timer@2c14 { 344 compatible = "snps,dw-apb-timer"; 345 reg = <0x2c14 0x14>; 346 clocks = <&chip_clk CLKID_CFG>; 347 clock-names = "timer"; 348 }; 349 350 timer2: timer@2c28 { 351 compatible = "snps,dw-apb-timer"; 352 reg = <0x2c28 0x14>; 353 clocks = <&chip_clk CLKID_CFG>; 354 clock-names = "timer"; 355 status = "disabled"; 356 }; 357 358 timer3: timer@2c3c { 359 compatible = "snps,dw-apb-timer"; 360 reg = <0x2c3c 0x14>; 361 clocks = <&chip_clk CLKID_CFG>; 362 clock-names = "timer"; 363 status = "disabled"; 364 }; 365 366 timer4: timer@2c50 { 367 compatible = "snps,dw-apb-timer"; 368 reg = <0x2c50 0x14>; 369 clocks = <&chip_clk CLKID_CFG>; 370 clock-names = "timer"; 371 status = "disabled"; 372 }; 373 374 timer5: timer@2c64 { 375 compatible = "snps,dw-apb-timer"; 376 reg = <0x2c64 0x14>; 377 clocks = <&chip_clk CLKID_CFG>; 378 clock-names = "timer"; 379 status = "disabled"; 380 }; 381 382 timer6: timer@2c78 { 383 compatible = "snps,dw-apb-timer"; 384 reg = <0x2c78 0x14>; 385 clocks = <&chip_clk CLKID_CFG>; 386 clock-names = "timer"; 387 status = "disabled"; 388 }; 389 390 timer7: timer@2c8c { 391 compatible = "snps,dw-apb-timer"; 392 reg = <0x2c8c 0x14>; 393 clocks = <&chip_clk CLKID_CFG>; 394 clock-names = "timer"; 395 status = "disabled"; 396 }; 397 398 aic: interrupt-controller@3800 { 399 compatible = "snps,dw-apb-ictl"; 400 reg = <0x3800 0x30>; 401 interrupt-controller; 402 #interrupt-cells = <1>; 403 interrupt-parent = <&gic>; 404 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 405 }; 406 }; 407 408 chip: chip-control@ea0000 { 409 compatible = "simple-mfd", "syscon"; 410 reg = <0xea0000 0x400>, <0xdd0170 0x10>; 411 412 chip_clk: clock { 413 compatible = "marvell,berlin2q-clk"; 414 #clock-cells = <1>; 415 clocks = <&refclk>; 416 clock-names = "refclk"; 417 }; 418 419 soc_pinctrl: pin-controller { 420 compatible = "marvell,berlin2q-soc-pinctrl"; 421 422 twsi0_pmux: twsi0-pmux { 423 groups = "G6"; 424 function = "twsi0"; 425 }; 426 427 twsi1_pmux: twsi1-pmux { 428 groups = "G7"; 429 function = "twsi1"; 430 }; 431 }; 432 433 chip_rst: reset { 434 compatible = "marvell,berlin2-reset"; 435 #reset-cells = <2>; 436 }; 437 }; 438 439 ahci: sata@e90000 { 440 compatible = "marvell,berlin2q-ahci", "generic-ahci"; 441 reg = <0xe90000 0x1000>; 442 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&chip_clk CLKID_SATA>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 447 sata0: sata-port@0 { 448 reg = <0>; 449 phys = <&sata_phy 0>; 450 status = "disabled"; 451 }; 452 453 sata1: sata-port@1 { 454 reg = <1>; 455 phys = <&sata_phy 1>; 456 status = "disabled"; 457 }; 458 }; 459 460 sata_phy: phy@e900a0 { 461 compatible = "marvell,berlin2q-sata-phy"; 462 reg = <0xe900a0 0x200>; 463 clocks = <&chip_clk CLKID_SATA>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 #phy-cells = <1>; 467 status = "disabled"; 468 469 sata-phy@0 { 470 reg = <0>; 471 }; 472 473 sata-phy@1 { 474 reg = <1>; 475 }; 476 }; 477 478 usb0: usb@ed0000 { 479 compatible = "chipidea,usb2"; 480 reg = <0xed0000 0x10000>; 481 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&chip_clk CLKID_USB0>; 483 phys = <&usb_phy0>; 484 phy-names = "usb-phy"; 485 status = "disabled"; 486 }; 487 488 usb1: usb@ee0000 { 489 compatible = "chipidea,usb2"; 490 reg = <0xee0000 0x10000>; 491 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&chip_clk CLKID_USB1>; 493 phys = <&usb_phy1>; 494 phy-names = "usb-phy"; 495 status = "disabled"; 496 }; 497 498 pwm: pwm@f20000 { 499 compatible = "marvell,berlin-pwm"; 500 reg = <0xf20000 0x40>; 501 clocks = <&chip_clk CLKID_CFG>; 502 #pwm-cells = <3>; 503 }; 504 505 apb@fc0000 { 506 compatible = "simple-bus"; 507 #address-cells = <1>; 508 #size-cells = <1>; 509 510 ranges = <0 0xfc0000 0x10000>; 511 interrupt-parent = <&sic>; 512 513 sm_gpio1: gpio@5000 { 514 compatible = "snps,dw-apb-gpio"; 515 reg = <0x5000 0x400>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 519 portf: gpio-port@5 { 520 compatible = "snps,dw-apb-gpio-port"; 521 gpio-controller; 522 #gpio-cells = <2>; 523 snps,nr-gpios = <32>; 524 reg = <0>; 525 }; 526 }; 527 528 i2c2: i2c@7000 { 529 compatible = "snps,designware-i2c"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 reg = <0x7000 0x100>; 533 interrupt-parent = <&sic>; 534 interrupts = <6>; 535 clocks = <&refclk>; 536 pinctrl-0 = <&twsi2_pmux>; 537 pinctrl-names = "default"; 538 status = "disabled"; 539 }; 540 541 i2c3: i2c@8000 { 542 compatible = "snps,designware-i2c"; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 reg = <0x8000 0x100>; 546 interrupt-parent = <&sic>; 547 interrupts = <7>; 548 clocks = <&refclk>; 549 pinctrl-0 = <&twsi3_pmux>; 550 pinctrl-names = "default"; 551 status = "disabled"; 552 }; 553 554 uart0: uart@9000 { 555 compatible = "snps,dw-apb-uart"; 556 reg = <0x9000 0x100>; 557 interrupt-parent = <&sic>; 558 interrupts = <8>; 559 clocks = <&refclk>; 560 reg-shift = <2>; 561 pinctrl-0 = <&uart0_pmux>; 562 pinctrl-names = "default"; 563 status = "disabled"; 564 }; 565 566 uart1: uart@a000 { 567 compatible = "snps,dw-apb-uart"; 568 reg = <0xa000 0x100>; 569 interrupt-parent = <&sic>; 570 interrupts = <9>; 571 clocks = <&refclk>; 572 reg-shift = <2>; 573 pinctrl-0 = <&uart1_pmux>; 574 pinctrl-names = "default"; 575 status = "disabled"; 576 }; 577 578 sm_gpio0: gpio@c000 { 579 compatible = "snps,dw-apb-gpio"; 580 reg = <0xc000 0x400>; 581 #address-cells = <1>; 582 #size-cells = <0>; 583 584 porte: gpio-port@4 { 585 compatible = "snps,dw-apb-gpio-port"; 586 gpio-controller; 587 #gpio-cells = <2>; 588 snps,nr-gpios = <32>; 589 reg = <0>; 590 }; 591 }; 592 593 sysctrl: pin-controller@d000 { 594 compatible = "simple-mfd", "syscon"; 595 reg = <0xd000 0x100>; 596 597 sys_pinctrl: pin-controller { 598 compatible = "marvell,berlin2q-system-pinctrl"; 599 600 uart0_pmux: uart0-pmux { 601 groups = "GSM12"; 602 function = "uart0"; 603 }; 604 605 uart1_pmux: uart1-pmux { 606 groups = "GSM14"; 607 function = "uart1"; 608 }; 609 610 twsi2_pmux: twsi2-pmux { 611 groups = "GSM13"; 612 function = "twsi2"; 613 }; 614 615 twsi3_pmux: twsi3-pmux { 616 groups = "GSM14"; 617 function = "twsi3"; 618 }; 619 }; 620 621 adc: adc { 622 compatible = "marvell,berlin2-adc"; 623 interrupts = <12>, <14>; 624 interrupt-names = "adc", "tsen"; 625 }; 626 }; 627 628 sic: interrupt-controller@e000 { 629 compatible = "snps,dw-apb-ictl"; 630 reg = <0xe000 0x30>; 631 interrupt-controller; 632 #interrupt-cells = <1>; 633 interrupt-parent = <&gic>; 634 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 635 }; 636 }; 637 }; 638}; 639