1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <dt-bindings/interrupt-controller/arm-gic.h> 34#include <dt-bindings/interrupt-controller/irq.h> 35#include <dt-bindings/clock/bcm-cygnus.h> 36 37#include "skeleton.dtsi" 38 39/ { 40 compatible = "brcm,cygnus"; 41 model = "Broadcom Cygnus SoC"; 42 interrupt-parent = <&gic>; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a9"; 51 next-level-cache = <&L2>; 52 reg = <0x0>; 53 }; 54 }; 55 56 /include/ "bcm-cygnus-clock.dtsi" 57 58 core { 59 compatible = "simple-bus"; 60 ranges = <0x00000000 0x19000000 0x1000000>; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 64 timer@20200 { 65 compatible = "arm,cortex-a9-global-timer"; 66 reg = <0x20200 0x100>; 67 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 68 clocks = <&periph_clk>; 69 }; 70 71 gic: interrupt-controller@21000 { 72 compatible = "arm,cortex-a9-gic"; 73 #interrupt-cells = <3>; 74 #address-cells = <0>; 75 interrupt-controller; 76 reg = <0x21000 0x1000>, 77 <0x20100 0x100>; 78 }; 79 80 L2: l2-cache { 81 compatible = "arm,pl310-cache"; 82 reg = <0x22000 0x1000>; 83 cache-unified; 84 cache-level = <2>; 85 }; 86 }; 87 88 axi { 89 compatible = "simple-bus"; 90 ranges; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 94 pinctrl: pinctrl@0x0301d0c8 { 95 compatible = "brcm,cygnus-pinmux"; 96 reg = <0x0301d0c8 0x30>, 97 <0x0301d24c 0x2c>; 98 }; 99 100 gpio_crmu: gpio@03024800 { 101 compatible = "brcm,cygnus-crmu-gpio"; 102 reg = <0x03024800 0x50>, 103 <0x03024008 0x18>; 104 #gpio-cells = <2>; 105 gpio-controller; 106 }; 107 108 i2c0: i2c@18008000 { 109 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; 110 reg = <0x18008000 0x100>; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>; 114 clock-frequency = <100000>; 115 status = "disabled"; 116 }; 117 118 wdt0: wdt@18009000 { 119 compatible = "arm,sp805" , "arm,primecell"; 120 reg = <0x18009000 0x1000>; 121 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 122 clocks = <&axi81_clk>; 123 clock-names = "apb_pclk"; 124 }; 125 126 gpio_ccm: gpio@1800a000 { 127 compatible = "brcm,cygnus-ccm-gpio"; 128 reg = <0x1800a000 0x50>, 129 <0x0301d164 0x20>; 130 #gpio-cells = <2>; 131 gpio-controller; 132 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 133 interrupt-controller; 134 }; 135 136 i2c1: i2c@1800b000 { 137 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; 138 reg = <0x1800b000 0x100>; 139 #address-cells = <1>; 140 #size-cells = <0>; 141 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>; 142 clock-frequency = <100000>; 143 status = "disabled"; 144 }; 145 146 pcie0: pcie@18012000 { 147 compatible = "brcm,iproc-pcie"; 148 reg = <0x18012000 0x1000>; 149 150 #interrupt-cells = <1>; 151 interrupt-map-mask = <0 0 0 0>; 152 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>; 153 154 linux,pci-domain = <0>; 155 156 bus-range = <0x00 0xff>; 157 158 #address-cells = <3>; 159 #size-cells = <2>; 160 device_type = "pci"; 161 ranges = <0x81000000 0 0 0x28000000 0 0x00010000 162 0x82000000 0 0x20000000 0x20000000 0 0x04000000>; 163 164 status = "disabled"; 165 }; 166 167 pcie1: pcie@18013000 { 168 compatible = "brcm,iproc-pcie"; 169 reg = <0x18013000 0x1000>; 170 171 #interrupt-cells = <1>; 172 interrupt-map-mask = <0 0 0 0>; 173 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>; 174 175 linux,pci-domain = <1>; 176 177 bus-range = <0x00 0xff>; 178 179 #address-cells = <3>; 180 #size-cells = <2>; 181 device_type = "pci"; 182 ranges = <0x81000000 0 0 0x48000000 0 0x00010000 183 0x82000000 0 0x40000000 0x40000000 0 0x04000000>; 184 185 status = "disabled"; 186 }; 187 188 uart0: serial@18020000 { 189 compatible = "snps,dw-apb-uart"; 190 reg = <0x18020000 0x100>; 191 reg-shift = <2>; 192 reg-io-width = <4>; 193 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&axi81_clk>; 195 clock-frequency = <100000000>; 196 status = "disabled"; 197 }; 198 199 uart1: serial@18021000 { 200 compatible = "snps,dw-apb-uart"; 201 reg = <0x18021000 0x100>; 202 reg-shift = <2>; 203 reg-io-width = <4>; 204 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&axi81_clk>; 206 clock-frequency = <100000000>; 207 status = "disabled"; 208 }; 209 210 uart2: serial@18022000 { 211 compatible = "snps,dw-apb-uart"; 212 reg = <0x18020000 0x100>; 213 reg-shift = <2>; 214 reg-io-width = <4>; 215 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&axi81_clk>; 217 clock-frequency = <100000000>; 218 status = "disabled"; 219 }; 220 221 uart3: serial@18023000 { 222 compatible = "snps,dw-apb-uart"; 223 reg = <0x18023000 0x100>; 224 reg-shift = <2>; 225 reg-io-width = <4>; 226 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&axi81_clk>; 228 clock-frequency = <100000000>; 229 status = "disabled"; 230 }; 231 232 nand: nand@18046000 { 233 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 234 reg = <0x18046000 0x600>, <0xf8105408 0x600>, 235 <0x18046f00 0x20>; 236 reg-names = "nand", "iproc-idm", "iproc-ext"; 237 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 238 239 #address-cells = <1>; 240 #size-cells = <0>; 241 242 brcm,nand-has-wp; 243 }; 244 245 gpio_asiu: gpio@180a5000 { 246 compatible = "brcm,cygnus-asiu-gpio"; 247 reg = <0x180a5000 0x668>; 248 #gpio-cells = <2>; 249 gpio-controller; 250 251 pinmux = <&pinctrl>; 252 253 interrupt-controller; 254 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 255 }; 256 257 touchscreen: tsc@180a6000 { 258 compatible = "brcm,iproc-touchscreen"; 259 reg = <0x180a6000 0x40>; 260 clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; 261 clock-names = "tsc_clk"; 262 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 263 status = "disabled"; 264 }; 265 }; 266}; 267