1/* 2 * Device Tree Include file for Marvell Armada 38x family of SoCs. 3 * 4 * Copyright (C) 2014 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * 10 * This file is dual-licensed: you can use it either under the terms 11 * of the GPL or the X11 license, at your option. Note that this dual 12 * licensing only applies to this file, and not this project as a 13 * whole. 14 * 15 * a) This file is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of the 18 * License, or (at your option) any later version. 19 * 20 * This file is distributed in the hope that it will be useful 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * Or, alternatively 26 * 27 * b) Permission is hereby granted, free of charge, to any person 28 * obtaining a copy of this software and associated documentation 29 * files (the "Software"), to deal in the Software without 30 * restriction, including without limitation the rights to use 31 * copy, modify, merge, publish, distribute, sublicense, and/or 32 * sell copies of the Software, and to permit persons to whom the 33 * Software is furnished to do so, subject to the following 34 * conditions: 35 * 36 * The above copyright notice and this permission notice shall be 37 * included in all copies or substantial portions of the Software. 38 * 39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 46 * OTHER DEALINGS IN THE SOFTWARE. 47 */ 48 49#include "skeleton.dtsi" 50#include <dt-bindings/interrupt-controller/arm-gic.h> 51#include <dt-bindings/interrupt-controller/irq.h> 52 53#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 54 55/ { 56 model = "Marvell Armada 38x family SoC"; 57 compatible = "marvell,armada380"; 58 59 aliases { 60 gpio0 = &gpio0; 61 gpio1 = &gpio1; 62 serial0 = &uart0; 63 serial1 = &uart1; 64 }; 65 66 pmu { 67 compatible = "arm,cortex-a9-pmu"; 68 interrupts-extended = <&mpic 3>; 69 }; 70 71 soc { 72 compatible = "marvell,armada380-mbus", "simple-bus"; 73 #address-cells = <2>; 74 #size-cells = <1>; 75 controller = <&mbusc>; 76 interrupt-parent = <&gic>; 77 pcie-mem-aperture = <0xe0000000 0x8000000>; 78 pcie-io-aperture = <0xe8000000 0x100000>; 79 80 bootrom { 81 compatible = "marvell,bootrom"; 82 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 83 }; 84 85 devbus-bootcs { 86 compatible = "marvell,mvebu-devbus"; 87 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; 88 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 clocks = <&coreclk 0>; 92 status = "disabled"; 93 }; 94 95 devbus-cs0 { 96 compatible = "marvell,mvebu-devbus"; 97 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; 98 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 clocks = <&coreclk 0>; 102 status = "disabled"; 103 }; 104 105 devbus-cs1 { 106 compatible = "marvell,mvebu-devbus"; 107 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; 108 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 clocks = <&coreclk 0>; 112 status = "disabled"; 113 }; 114 115 devbus-cs2 { 116 compatible = "marvell,mvebu-devbus"; 117 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; 118 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; 119 #address-cells = <1>; 120 #size-cells = <1>; 121 clocks = <&coreclk 0>; 122 status = "disabled"; 123 }; 124 125 devbus-cs3 { 126 compatible = "marvell,mvebu-devbus"; 127 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; 128 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 clocks = <&coreclk 0>; 132 status = "disabled"; 133 }; 134 135 internal-regs { 136 compatible = "simple-bus"; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 140 141 L2: cache-controller@8000 { 142 compatible = "arm,pl310-cache"; 143 reg = <0x8000 0x1000>; 144 cache-unified; 145 cache-level = <2>; 146 arm,double-linefill-incr = <1>; 147 arm,double-linefill-wrap = <0>; 148 arm,double-linefill = <1>; 149 prefetch-data = <1>; 150 }; 151 152 scu@c000 { 153 compatible = "arm,cortex-a9-scu"; 154 reg = <0xc000 0x58>; 155 }; 156 157 timer@c600 { 158 compatible = "arm,cortex-a9-twd-timer"; 159 reg = <0xc600 0x20>; 160 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 161 clocks = <&coreclk 2>; 162 }; 163 164 gic: interrupt-controller@d000 { 165 compatible = "arm,cortex-a9-gic"; 166 #interrupt-cells = <3>; 167 #size-cells = <0>; 168 interrupt-controller; 169 reg = <0xd000 0x1000>, 170 <0xc100 0x100>; 171 }; 172 173 spi0: spi@10600 { 174 compatible = "marvell,armada-380-spi", 175 "marvell,orion-spi"; 176 reg = <0x10600 0x50>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 cell-index = <0>; 180 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 181 clocks = <&coreclk 0>; 182 status = "disabled"; 183 }; 184 185 spi1: spi@10680 { 186 compatible = "marvell,armada-380-spi", 187 "marvell,orion-spi"; 188 reg = <0x10680 0x50>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 cell-index = <1>; 192 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&coreclk 0>; 194 status = "disabled"; 195 }; 196 197 i2c0: i2c@11000 { 198 compatible = "marvell,mv64xxx-i2c"; 199 reg = <0x11000 0x20>; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 203 timeout-ms = <1000>; 204 clocks = <&coreclk 0>; 205 status = "disabled"; 206 }; 207 208 i2c1: i2c@11100 { 209 compatible = "marvell,mv64xxx-i2c"; 210 reg = <0x11100 0x20>; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 214 timeout-ms = <1000>; 215 clocks = <&coreclk 0>; 216 status = "disabled"; 217 }; 218 219 uart0: serial@12000 { 220 compatible = "snps,dw-apb-uart"; 221 reg = <0x12000 0x100>; 222 reg-shift = <2>; 223 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 224 reg-io-width = <1>; 225 clocks = <&coreclk 0>; 226 status = "disabled"; 227 }; 228 229 uart1: serial@12100 { 230 compatible = "snps,dw-apb-uart"; 231 reg = <0x12100 0x100>; 232 reg-shift = <2>; 233 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 234 reg-io-width = <1>; 235 clocks = <&coreclk 0>; 236 status = "disabled"; 237 }; 238 239 pinctrl: pinctrl@18000 { 240 reg = <0x18000 0x20>; 241 242 ge0_rgmii_pins: ge-rgmii-pins-0 { 243 marvell,pins = "mpp6", "mpp7", "mpp8", 244 "mpp9", "mpp10", "mpp11", 245 "mpp12", "mpp13", "mpp14", 246 "mpp15", "mpp16", "mpp17"; 247 marvell,function = "ge0"; 248 }; 249 250 ge1_rgmii_pins: ge-rgmii-pins-1 { 251 marvell,pins = "mpp21", "mpp27", "mpp28", 252 "mpp29", "mpp30", "mpp31", 253 "mpp32", "mpp37", "mpp38", 254 "mpp39", "mpp40", "mpp41"; 255 marvell,function = "ge1"; 256 }; 257 258 i2c0_pins: i2c-pins-0 { 259 marvell,pins = "mpp2", "mpp3"; 260 marvell,function = "i2c0"; 261 }; 262 263 mdio_pins: mdio-pins { 264 marvell,pins = "mpp4", "mpp5"; 265 marvell,function = "ge"; 266 }; 267 268 ref_clk0_pins: ref-clk-pins-0 { 269 marvell,pins = "mpp45"; 270 marvell,function = "ref"; 271 }; 272 273 ref_clk1_pins: ref-clk-pins-1 { 274 marvell,pins = "mpp46"; 275 marvell,function = "ref"; 276 }; 277 278 spi0_pins: spi-pins-0 { 279 marvell,pins = "mpp22", "mpp23", "mpp24", 280 "mpp25"; 281 marvell,function = "spi0"; 282 }; 283 284 spi1_pins: spi-pins-1 { 285 marvell,pins = "mpp56", "mpp57", "mpp58", 286 "mpp59"; 287 marvell,function = "spi1"; 288 }; 289 290 uart0_pins: uart-pins-0 { 291 marvell,pins = "mpp0", "mpp1"; 292 marvell,function = "ua0"; 293 }; 294 295 uart1_pins: uart-pins-1 { 296 marvell,pins = "mpp19", "mpp20"; 297 marvell,function = "ua1"; 298 }; 299 300 sdhci_pins: sdhci-pins { 301 marvell,pins = "mpp48", "mpp49", "mpp50", 302 "mpp52", "mpp53", "mpp54", 303 "mpp55", "mpp57", "mpp58", 304 "mpp59"; 305 marvell,function = "sd0"; 306 }; 307 308 sata0_pins: sata-pins-0 { 309 marvell,pins = "mpp20"; 310 marvell,function = "sata0"; 311 }; 312 313 sata1_pins: sata-pins-1 { 314 marvell,pins = "mpp19"; 315 marvell,function = "sata1"; 316 }; 317 318 sata2_pins: sata-pins-2 { 319 marvell,pins = "mpp47"; 320 marvell,function = "sata2"; 321 }; 322 323 sata3_pins: sata-pins-3 { 324 marvell,pins = "mpp44"; 325 marvell,function = "sata3"; 326 }; 327 }; 328 329 gpio0: gpio@18100 { 330 compatible = "marvell,orion-gpio"; 331 reg = <0x18100 0x40>; 332 ngpios = <32>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 341 }; 342 343 gpio1: gpio@18140 { 344 compatible = "marvell,orion-gpio"; 345 reg = <0x18140 0x40>; 346 ngpios = <28>; 347 gpio-controller; 348 #gpio-cells = <2>; 349 interrupt-controller; 350 #interrupt-cells = <2>; 351 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 355 }; 356 357 system-controller@18200 { 358 compatible = "marvell,armada-380-system-controller", 359 "marvell,armada-370-xp-system-controller"; 360 reg = <0x18200 0x100>; 361 }; 362 363 gateclk: clock-gating-control@18220 { 364 compatible = "marvell,armada-380-gating-clock"; 365 reg = <0x18220 0x4>; 366 clocks = <&coreclk 0>; 367 #clock-cells = <1>; 368 }; 369 370 coreclk: mvebu-sar@18600 { 371 compatible = "marvell,armada-380-core-clock"; 372 reg = <0x18600 0x04>; 373 #clock-cells = <1>; 374 }; 375 376 mbusc: mbus-controller@20000 { 377 compatible = "marvell,mbus-controller"; 378 reg = <0x20000 0x100>, <0x20180 0x20>; 379 }; 380 381 mpic: interrupt-controller@20a00 { 382 compatible = "marvell,mpic"; 383 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 384 #interrupt-cells = <1>; 385 #size-cells = <1>; 386 interrupt-controller; 387 msi-controller; 388 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 389 }; 390 391 timer@20300 { 392 compatible = "marvell,armada-380-timer", 393 "marvell,armada-xp-timer"; 394 reg = <0x20300 0x30>, <0x21040 0x30>; 395 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 396 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 397 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 398 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 399 <&mpic 5>, 400 <&mpic 6>; 401 clocks = <&coreclk 2>, <&refclk>; 402 clock-names = "nbclk", "fixed"; 403 }; 404 405 watchdog@20300 { 406 compatible = "marvell,armada-380-wdt"; 407 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; 408 clocks = <&coreclk 2>, <&refclk>; 409 clock-names = "nbclk", "fixed"; 410 }; 411 412 cpurst@20800 { 413 compatible = "marvell,armada-370-cpu-reset"; 414 reg = <0x20800 0x10>; 415 }; 416 417 mpcore-soc-ctrl@20d20 { 418 compatible = "marvell,armada-380-mpcore-soc-ctrl"; 419 reg = <0x20d20 0x6c>; 420 }; 421 422 coherency-fabric@21010 { 423 compatible = "marvell,armada-380-coherency-fabric"; 424 reg = <0x21010 0x1c>; 425 }; 426 427 pmsu@22000 { 428 compatible = "marvell,armada-380-pmsu"; 429 reg = <0x22000 0x1000>; 430 }; 431 432 eth1: ethernet@30000 { 433 compatible = "marvell,armada-370-neta"; 434 reg = <0x30000 0x4000>; 435 interrupts-extended = <&mpic 10>; 436 clocks = <&gateclk 3>; 437 status = "disabled"; 438 }; 439 440 eth2: ethernet@34000 { 441 compatible = "marvell,armada-370-neta"; 442 reg = <0x34000 0x4000>; 443 interrupts-extended = <&mpic 12>; 444 clocks = <&gateclk 2>; 445 status = "disabled"; 446 }; 447 448 usb@58000 { 449 compatible = "marvell,orion-ehci"; 450 reg = <0x58000 0x500>; 451 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&gateclk 18>; 453 status = "disabled"; 454 }; 455 456 xor@60800 { 457 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 458 reg = <0x60800 0x100 459 0x60a00 0x100>; 460 clocks = <&gateclk 22>; 461 status = "okay"; 462 463 xor00 { 464 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 465 dmacap,memcpy; 466 dmacap,xor; 467 }; 468 xor01 { 469 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 470 dmacap,memcpy; 471 dmacap,xor; 472 dmacap,memset; 473 }; 474 }; 475 476 xor@60900 { 477 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 478 reg = <0x60900 0x100 479 0x60b00 0x100>; 480 clocks = <&gateclk 28>; 481 status = "okay"; 482 483 xor10 { 484 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 485 dmacap,memcpy; 486 dmacap,xor; 487 }; 488 xor11 { 489 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 490 dmacap,memcpy; 491 dmacap,xor; 492 dmacap,memset; 493 }; 494 }; 495 496 eth0: ethernet@70000 { 497 compatible = "marvell,armada-370-neta"; 498 reg = <0x70000 0x4000>; 499 interrupts-extended = <&mpic 8>; 500 clocks = <&gateclk 4>; 501 tx-csum-limit = <9800>; 502 status = "disabled"; 503 }; 504 505 mdio: mdio@72004 { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 compatible = "marvell,orion-mdio"; 509 reg = <0x72004 0x4>; 510 clocks = <&gateclk 4>; 511 }; 512 513 crypto@90000 { 514 compatible = "marvell,armada-38x-crypto"; 515 reg = <0x90000 0x10000>; 516 reg-names = "regs"; 517 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&gateclk 23>, <&gateclk 21>, 520 <&gateclk 14>, <&gateclk 16>; 521 clock-names = "cesa0", "cesa1", 522 "cesaz0", "cesaz1"; 523 marvell,crypto-srams = <&crypto_sram0>, 524 <&crypto_sram1>; 525 marvell,crypto-sram-size = <0x800>; 526 }; 527 528 rtc@a3800 { 529 compatible = "marvell,armada-380-rtc"; 530 reg = <0xa3800 0x20>, <0x184a0 0x0c>; 531 reg-names = "rtc", "rtc-soc"; 532 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 533 }; 534 535 sata@a8000 { 536 compatible = "marvell,armada-380-ahci"; 537 reg = <0xa8000 0x2000>; 538 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&gateclk 15>; 540 status = "disabled"; 541 }; 542 543 sata@e0000 { 544 compatible = "marvell,armada-380-ahci"; 545 reg = <0xe0000 0x2000>; 546 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&gateclk 30>; 548 status = "disabled"; 549 }; 550 551 coredivclk: clock@e4250 { 552 compatible = "marvell,armada-380-corediv-clock"; 553 reg = <0xe4250 0xc>; 554 #clock-cells = <1>; 555 clocks = <&mainpll>; 556 clock-output-names = "nand"; 557 }; 558 559 thermal@e8078 { 560 compatible = "marvell,armada380-thermal"; 561 reg = <0xe4078 0x4>, <0xe4074 0x4>; 562 status = "okay"; 563 }; 564 565 flash@d0000 { 566 compatible = "marvell,armada370-nand"; 567 reg = <0xd0000 0x54>; 568 #address-cells = <1>; 569 #size-cells = <1>; 570 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&coredivclk 0>; 572 status = "disabled"; 573 }; 574 575 sdhci@d8000 { 576 compatible = "marvell,armada-380-sdhci"; 577 reg-names = "sdhci", "mbus", "conf-sdio3"; 578 reg = <0xd8000 0x1000>, 579 <0xdc000 0x100>, 580 <0x18454 0x4>; 581 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&gateclk 17>; 583 mrvl,clk-delay-cycles = <0x1F>; 584 status = "disabled"; 585 }; 586 587 usb3@f0000 { 588 compatible = "marvell,armada-380-xhci"; 589 reg = <0xf0000 0x4000>,<0xf4000 0x4000>; 590 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&gateclk 9>; 592 status = "disabled"; 593 }; 594 595 usb3@f8000 { 596 compatible = "marvell,armada-380-xhci"; 597 reg = <0xf8000 0x4000>,<0xfc000 0x4000>; 598 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&gateclk 10>; 600 status = "disabled"; 601 }; 602 }; 603 604 crypto_sram0: sa-sram0 { 605 compatible = "mmio-sram"; 606 reg = <MBUS_ID(0x09, 0x19) 0 0x800>; 607 clocks = <&gateclk 23>; 608 #address-cells = <1>; 609 #size-cells = <1>; 610 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>; 611 }; 612 613 crypto_sram1: sa-sram1 { 614 compatible = "mmio-sram"; 615 reg = <MBUS_ID(0x09, 0x15) 0 0x800>; 616 clocks = <&gateclk 21>; 617 #address-cells = <1>; 618 #size-cells = <1>; 619 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>; 620 }; 621 }; 622 623 clocks { 624 /* 2 GHz fixed main PLL */ 625 mainpll: mainpll { 626 compatible = "fixed-clock"; 627 #clock-cells = <0>; 628 clock-frequency = <1000000000>; 629 }; 630 631 /* 25 MHz reference crystal */ 632 refclk: oscillator { 633 compatible = "fixed-clock"; 634 #clock-cells = <0>; 635 clock-frequency = <25000000>; 636 }; 637 }; 638}; 639