1config ARM 2 bool 3 default y 4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 5 select ARCH_HAS_ELF_RANDOMIZE 6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 7 select ARCH_HAVE_CUSTOM_GPIO_H 8 select ARCH_HAS_GCOV_PROFILE_ALL 9 select ARCH_MIGHT_HAVE_PC_PARPORT 10 select ARCH_SUPPORTS_ATOMIC_RMW 11 select ARCH_USE_BUILTIN_BSWAP 12 select ARCH_USE_CMPXCHG_LOCKREF 13 select ARCH_WANT_IPC_PARSE_VERSION 14 select BUILDTIME_EXTABLE_SORT if MMU 15 select CLONE_BACKWARDS 16 select CPU_PM if (SUSPEND || CPU_IDLE) 17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 18 select EDAC_SUPPORT 19 select EDAC_ATOMIC_SCRUB 20 select GENERIC_ALLOCATOR 21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 23 select GENERIC_IDLE_POLL_SETUP 24 select GENERIC_IRQ_PROBE 25 select GENERIC_IRQ_SHOW 26 select GENERIC_IRQ_SHOW_LEVEL 27 select GENERIC_PCI_IOMAP 28 select GENERIC_SCHED_CLOCK 29 select GENERIC_SMP_IDLE_THREAD 30 select GENERIC_STRNCPY_FROM_USER 31 select GENERIC_STRNLEN_USER 32 select HANDLE_DOMAIN_IRQ 33 select HARDIRQS_SW_RESEND 34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 38 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 39 select HAVE_ARCH_TRACEHOOK 40 select HAVE_BPF_JIT 41 select HAVE_CC_STACKPROTECTOR 42 select HAVE_CONTEXT_TRACKING 43 select HAVE_C_RECORDMCOUNT 44 select HAVE_DEBUG_KMEMLEAK 45 select HAVE_DMA_API_DEBUG 46 select HAVE_DMA_ATTRS 47 select HAVE_DMA_CONTIGUOUS if MMU 48 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 49 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 50 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 51 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 52 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 53 select HAVE_GENERIC_DMA_COHERENT 54 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 55 select HAVE_IDE if PCI || ISA || PCMCIA 56 select HAVE_IRQ_TIME_ACCOUNTING 57 select HAVE_KERNEL_GZIP 58 select HAVE_KERNEL_LZ4 59 select HAVE_KERNEL_LZMA 60 select HAVE_KERNEL_LZO 61 select HAVE_KERNEL_XZ 62 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 63 select HAVE_KRETPROBES if (HAVE_KPROBES) 64 select HAVE_MEMBLOCK 65 select HAVE_MOD_ARCH_SPECIFIC 66 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 67 select HAVE_OPTPROBES if !THUMB2_KERNEL 68 select HAVE_PERF_EVENTS 69 select HAVE_PERF_REGS 70 select HAVE_PERF_USER_STACK_DUMP 71 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 72 select HAVE_REGS_AND_STACK_ACCESS_API 73 select HAVE_SYSCALL_TRACEPOINTS 74 select HAVE_UID16 75 select HAVE_VIRT_CPU_ACCOUNTING_GEN 76 select IRQ_FORCED_THREADING 77 select MODULES_USE_ELF_REL 78 select NO_BOOTMEM 79 select OF_EARLY_FLATTREE if OF 80 select OF_RESERVED_MEM if OF 81 select OLD_SIGACTION 82 select OLD_SIGSUSPEND3 83 select PERF_USE_VMALLOC 84 select RTC_LIB 85 select SYS_SUPPORTS_APM_EMULATION 86 # Above selects are sorted alphabetically; please add new ones 87 # according to that. Thanks. 88 help 89 The ARM series is a line of low-power-consumption RISC chip designs 90 licensed by ARM Ltd and targeted at embedded applications and 91 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 92 manufactured, but legacy ARM-based PC hardware remains popular in 93 Europe. There is an ARM Linux project with a web page at 94 <http://www.arm.linux.org.uk/>. 95 96config ARM_HAS_SG_CHAIN 97 select ARCH_HAS_SG_CHAIN 98 bool 99 100config NEED_SG_DMA_LENGTH 101 bool 102 103config ARM_DMA_USE_IOMMU 104 bool 105 select ARM_HAS_SG_CHAIN 106 select NEED_SG_DMA_LENGTH 107 108if ARM_DMA_USE_IOMMU 109 110config ARM_DMA_IOMMU_ALIGNMENT 111 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 112 range 4 9 113 default 8 114 help 115 DMA mapping framework by default aligns all buffers to the smallest 116 PAGE_SIZE order which is greater than or equal to the requested buffer 117 size. This works well for buffers up to a few hundreds kilobytes, but 118 for larger buffers it just a waste of address space. Drivers which has 119 relatively small addressing window (like 64Mib) might run out of 120 virtual space with just a few allocations. 121 122 With this parameter you can specify the maximum PAGE_SIZE order for 123 DMA IOMMU buffers. Larger buffers will be aligned only to this 124 specified order. The order is expressed as a power of two multiplied 125 by the PAGE_SIZE. 126 127endif 128 129config MIGHT_HAVE_PCI 130 bool 131 132config SYS_SUPPORTS_APM_EMULATION 133 bool 134 135config HAVE_TCM 136 bool 137 select GENERIC_ALLOCATOR 138 139config HAVE_PROC_CPU 140 bool 141 142config NO_IOPORT_MAP 143 bool 144 145config EISA 146 bool 147 ---help--- 148 The Extended Industry Standard Architecture (EISA) bus was 149 developed as an open alternative to the IBM MicroChannel bus. 150 151 The EISA bus provided some of the features of the IBM MicroChannel 152 bus while maintaining backward compatibility with cards made for 153 the older ISA bus. The EISA bus saw limited use between 1988 and 154 1995 when it was made obsolete by the PCI bus. 155 156 Say Y here if you are building a kernel for an EISA-based machine. 157 158 Otherwise, say N. 159 160config SBUS 161 bool 162 163config STACKTRACE_SUPPORT 164 bool 165 default y 166 167config HAVE_LATENCYTOP_SUPPORT 168 bool 169 depends on !SMP 170 default y 171 172config LOCKDEP_SUPPORT 173 bool 174 default y 175 176config TRACE_IRQFLAGS_SUPPORT 177 bool 178 default !CPU_V7M 179 180config RWSEM_XCHGADD_ALGORITHM 181 bool 182 default y 183 184config ARCH_HAS_ILOG2_U32 185 bool 186 187config ARCH_HAS_ILOG2_U64 188 bool 189 190config ARCH_HAS_BANDGAP 191 bool 192 193config FIX_EARLYCON_MEM 194 def_bool y if MMU 195 196config GENERIC_HWEIGHT 197 bool 198 default y 199 200config GENERIC_CALIBRATE_DELAY 201 bool 202 default y 203 204config ARCH_MAY_HAVE_PC_FDC 205 bool 206 207config ZONE_DMA 208 bool 209 210config NEED_DMA_MAP_STATE 211 def_bool y 212 213config ARCH_SUPPORTS_UPROBES 214 def_bool y 215 216config ARCH_HAS_DMA_SET_COHERENT_MASK 217 bool 218 219config GENERIC_ISA_DMA 220 bool 221 222config FIQ 223 bool 224 225config NEED_RET_TO_USER 226 bool 227 228config ARCH_MTD_XIP 229 bool 230 231config VECTORS_BASE 232 hex 233 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 234 default DRAM_BASE if REMAP_VECTORS_TO_RAM 235 default 0x00000000 236 help 237 The base address of exception vectors. This must be two pages 238 in size. 239 240config ARM_PATCH_PHYS_VIRT 241 bool "Patch physical to virtual translations at runtime" if EMBEDDED 242 default y 243 depends on !XIP_KERNEL && MMU 244 depends on !ARCH_REALVIEW || !SPARSEMEM 245 help 246 Patch phys-to-virt and virt-to-phys translation functions at 247 boot and module load time according to the position of the 248 kernel in system memory. 249 250 This can only be used with non-XIP MMU kernels where the base 251 of physical memory is at a 16MB boundary. 252 253 Only disable this option if you know that you do not require 254 this feature (eg, building a kernel for a single machine) and 255 you need to shrink the kernel to the minimal size. 256 257config NEED_MACH_IO_H 258 bool 259 help 260 Select this when mach/io.h is required to provide special 261 definitions for this platform. The need for mach/io.h should 262 be avoided when possible. 263 264config NEED_MACH_MEMORY_H 265 bool 266 help 267 Select this when mach/memory.h is required to provide special 268 definitions for this platform. The need for mach/memory.h should 269 be avoided when possible. 270 271config PHYS_OFFSET 272 hex "Physical address of main memory" if MMU 273 depends on !ARM_PATCH_PHYS_VIRT 274 default DRAM_BASE if !MMU 275 default 0x00000000 if ARCH_EBSA110 || \ 276 ARCH_FOOTBRIDGE || \ 277 ARCH_INTEGRATOR || \ 278 ARCH_IOP13XX || \ 279 ARCH_KS8695 || \ 280 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET) 281 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 282 default 0x20000000 if ARCH_S5PV210 283 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET 284 default 0xc0000000 if ARCH_SA1100 285 help 286 Please provide the physical address corresponding to the 287 location of main memory in your system. 288 289config GENERIC_BUG 290 def_bool y 291 depends on BUG 292 293config PGTABLE_LEVELS 294 int 295 default 3 if ARM_LPAE 296 default 2 297 298source "init/Kconfig" 299 300source "kernel/Kconfig.freezer" 301 302menu "System Type" 303 304config MMU 305 bool "MMU-based Paged Memory Management Support" 306 default y 307 help 308 Select if you want MMU-based virtualised addressing space 309 support by paged memory management. If unsure, say 'Y'. 310 311# 312# The "ARM system type" choice list is ordered alphabetically by option 313# text. Please add new entries in the option alphabetic order. 314# 315choice 316 prompt "ARM system type" 317 default ARCH_VERSATILE if !MMU 318 default ARCH_MULTIPLATFORM if MMU 319 320config ARCH_MULTIPLATFORM 321 bool "Allow multiple platforms to be selected" 322 depends on MMU 323 select ARCH_WANT_OPTIONAL_GPIOLIB 324 select ARM_HAS_SG_CHAIN 325 select ARM_PATCH_PHYS_VIRT 326 select AUTO_ZRELADDR 327 select CLKSRC_OF 328 select COMMON_CLK 329 select GENERIC_CLOCKEVENTS 330 select MIGHT_HAVE_PCI 331 select MULTI_IRQ_HANDLER 332 select SPARSE_IRQ 333 select USE_OF 334 335config ARM_SINGLE_ARMV7M 336 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 337 depends on !MMU 338 select ARCH_WANT_OPTIONAL_GPIOLIB 339 select ARM_NVIC 340 select AUTO_ZRELADDR 341 select CLKSRC_OF 342 select COMMON_CLK 343 select CPU_V7M 344 select GENERIC_CLOCKEVENTS 345 select NO_IOPORT_MAP 346 select SPARSE_IRQ 347 select USE_OF 348 349config ARCH_REALVIEW 350 bool "ARM Ltd. RealView family" 351 select ARCH_WANT_OPTIONAL_GPIOLIB 352 select ARM_AMBA 353 select ARM_TIMER_SP804 354 select COMMON_CLK 355 select COMMON_CLK_VERSATILE 356 select GENERIC_CLOCKEVENTS 357 select GPIO_PL061 if GPIOLIB 358 select ICST 359 select NEED_MACH_MEMORY_H 360 select PLAT_VERSATILE 361 select PLAT_VERSATILE_SCHED_CLOCK 362 help 363 This enables support for ARM Ltd RealView boards. 364 365config ARCH_VERSATILE 366 bool "ARM Ltd. Versatile family" 367 select ARCH_WANT_OPTIONAL_GPIOLIB 368 select ARM_AMBA 369 select ARM_TIMER_SP804 370 select ARM_VIC 371 select CLKDEV_LOOKUP 372 select GENERIC_CLOCKEVENTS 373 select HAVE_MACH_CLKDEV 374 select ICST 375 select PLAT_VERSATILE 376 select PLAT_VERSATILE_CLOCK 377 select PLAT_VERSATILE_SCHED_CLOCK 378 select VERSATILE_FPGA_IRQ 379 help 380 This enables support for ARM Ltd Versatile board. 381 382config ARCH_CLPS711X 383 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based" 384 select ARCH_REQUIRE_GPIOLIB 385 select AUTO_ZRELADDR 386 select CLKSRC_MMIO 387 select COMMON_CLK 388 select CPU_ARM720T 389 select GENERIC_CLOCKEVENTS 390 select MFD_SYSCON 391 select SOC_BUS 392 help 393 Support for Cirrus Logic 711x/721x/731x based boards. 394 395config ARCH_GEMINI 396 bool "Cortina Systems Gemini" 397 select ARCH_REQUIRE_GPIOLIB 398 select CLKSRC_MMIO 399 select CPU_FA526 400 select GENERIC_CLOCKEVENTS 401 help 402 Support for the Cortina Systems Gemini family SoCs 403 404config ARCH_EBSA110 405 bool "EBSA-110" 406 select ARCH_USES_GETTIMEOFFSET 407 select CPU_SA110 408 select ISA 409 select NEED_MACH_IO_H 410 select NEED_MACH_MEMORY_H 411 select NO_IOPORT_MAP 412 help 413 This is an evaluation board for the StrongARM processor available 414 from Digital. It has limited hardware on-board, including an 415 Ethernet interface, two PCMCIA sockets, two serial ports and a 416 parallel port. 417 418config ARCH_EP93XX 419 bool "EP93xx-based" 420 select ARCH_HAS_HOLES_MEMORYMODEL 421 select ARCH_REQUIRE_GPIOLIB 422 select ARM_AMBA 423 select ARM_PATCH_PHYS_VIRT 424 select ARM_VIC 425 select AUTO_ZRELADDR 426 select CLKDEV_LOOKUP 427 select CLKSRC_MMIO 428 select CPU_ARM920T 429 select GENERIC_CLOCKEVENTS 430 help 431 This enables support for the Cirrus EP93xx series of CPUs. 432 433config ARCH_FOOTBRIDGE 434 bool "FootBridge" 435 select CPU_SA110 436 select FOOTBRIDGE 437 select GENERIC_CLOCKEVENTS 438 select HAVE_IDE 439 select NEED_MACH_IO_H if !MMU 440 select NEED_MACH_MEMORY_H 441 help 442 Support for systems based on the DC21285 companion chip 443 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 444 445config ARCH_NETX 446 bool "Hilscher NetX based" 447 select ARM_VIC 448 select CLKSRC_MMIO 449 select CPU_ARM926T 450 select GENERIC_CLOCKEVENTS 451 help 452 This enables support for systems based on the Hilscher NetX Soc 453 454config ARCH_IOP13XX 455 bool "IOP13xx-based" 456 depends on MMU 457 select CPU_XSC3 458 select NEED_MACH_MEMORY_H 459 select NEED_RET_TO_USER 460 select PCI 461 select PLAT_IOP 462 select VMSPLIT_1G 463 select SPARSE_IRQ 464 help 465 Support for Intel's IOP13XX (XScale) family of processors. 466 467config ARCH_IOP32X 468 bool "IOP32x-based" 469 depends on MMU 470 select ARCH_REQUIRE_GPIOLIB 471 select CPU_XSCALE 472 select GPIO_IOP 473 select NEED_RET_TO_USER 474 select PCI 475 select PLAT_IOP 476 help 477 Support for Intel's 80219 and IOP32X (XScale) family of 478 processors. 479 480config ARCH_IOP33X 481 bool "IOP33x-based" 482 depends on MMU 483 select ARCH_REQUIRE_GPIOLIB 484 select CPU_XSCALE 485 select GPIO_IOP 486 select NEED_RET_TO_USER 487 select PCI 488 select PLAT_IOP 489 help 490 Support for Intel's IOP33X (XScale) family of processors. 491 492config ARCH_IXP4XX 493 bool "IXP4xx-based" 494 depends on MMU 495 select ARCH_HAS_DMA_SET_COHERENT_MASK 496 select ARCH_REQUIRE_GPIOLIB 497 select ARCH_SUPPORTS_BIG_ENDIAN 498 select CLKSRC_MMIO 499 select CPU_XSCALE 500 select DMABOUNCE if PCI 501 select GENERIC_CLOCKEVENTS 502 select MIGHT_HAVE_PCI 503 select NEED_MACH_IO_H 504 select USB_EHCI_BIG_ENDIAN_DESC 505 select USB_EHCI_BIG_ENDIAN_MMIO 506 help 507 Support for Intel's IXP4XX (XScale) family of processors. 508 509config ARCH_DOVE 510 bool "Marvell Dove" 511 select ARCH_REQUIRE_GPIOLIB 512 select CPU_PJ4 513 select GENERIC_CLOCKEVENTS 514 select MIGHT_HAVE_PCI 515 select MVEBU_MBUS 516 select PINCTRL 517 select PINCTRL_DOVE 518 select PLAT_ORION_LEGACY 519 help 520 Support for the Marvell Dove SoC 88AP510 521 522config ARCH_MV78XX0 523 bool "Marvell MV78xx0" 524 select ARCH_REQUIRE_GPIOLIB 525 select CPU_FEROCEON 526 select GENERIC_CLOCKEVENTS 527 select MVEBU_MBUS 528 select PCI 529 select PLAT_ORION_LEGACY 530 help 531 Support for the following Marvell MV78xx0 series SoCs: 532 MV781x0, MV782x0. 533 534config ARCH_ORION5X 535 bool "Marvell Orion" 536 depends on MMU 537 select ARCH_REQUIRE_GPIOLIB 538 select CPU_FEROCEON 539 select GENERIC_CLOCKEVENTS 540 select MVEBU_MBUS 541 select PCI 542 select PLAT_ORION_LEGACY 543 select MULTI_IRQ_HANDLER 544 help 545 Support for the following Marvell Orion 5x series SoCs: 546 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 547 Orion-2 (5281), Orion-1-90 (6183). 548 549config ARCH_MMP 550 bool "Marvell PXA168/910/MMP2" 551 depends on MMU 552 select ARCH_REQUIRE_GPIOLIB 553 select CLKDEV_LOOKUP 554 select GENERIC_ALLOCATOR 555 select GENERIC_CLOCKEVENTS 556 select GPIO_PXA 557 select IRQ_DOMAIN 558 select MULTI_IRQ_HANDLER 559 select PINCTRL 560 select PLAT_PXA 561 select SPARSE_IRQ 562 help 563 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 564 565config ARCH_KS8695 566 bool "Micrel/Kendin KS8695" 567 select ARCH_REQUIRE_GPIOLIB 568 select CLKSRC_MMIO 569 select CPU_ARM922T 570 select GENERIC_CLOCKEVENTS 571 select NEED_MACH_MEMORY_H 572 help 573 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 574 System-on-Chip devices. 575 576config ARCH_W90X900 577 bool "Nuvoton W90X900 CPU" 578 select ARCH_REQUIRE_GPIOLIB 579 select CLKDEV_LOOKUP 580 select CLKSRC_MMIO 581 select CPU_ARM926T 582 select GENERIC_CLOCKEVENTS 583 help 584 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 585 At present, the w90x900 has been renamed nuc900, regarding 586 the ARM series product line, you can login the following 587 link address to know more. 588 589 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 590 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 591 592config ARCH_LPC32XX 593 bool "NXP LPC32XX" 594 select ARCH_REQUIRE_GPIOLIB 595 select ARM_AMBA 596 select CLKDEV_LOOKUP 597 select CLKSRC_MMIO 598 select CPU_ARM926T 599 select GENERIC_CLOCKEVENTS 600 select HAVE_IDE 601 select USE_OF 602 help 603 Support for the NXP LPC32XX family of processors 604 605config ARCH_PXA 606 bool "PXA2xx/PXA3xx-based" 607 depends on MMU 608 select ARCH_MTD_XIP 609 select ARCH_REQUIRE_GPIOLIB 610 select ARM_CPU_SUSPEND if PM 611 select AUTO_ZRELADDR 612 select COMMON_CLK 613 select CLKDEV_LOOKUP 614 select CLKSRC_MMIO 615 select CLKSRC_OF 616 select GENERIC_CLOCKEVENTS 617 select GPIO_PXA 618 select HAVE_IDE 619 select IRQ_DOMAIN 620 select MULTI_IRQ_HANDLER 621 select PLAT_PXA 622 select SPARSE_IRQ 623 help 624 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 625 626config ARCH_RPC 627 bool "RiscPC" 628 depends on MMU 629 select ARCH_ACORN 630 select ARCH_MAY_HAVE_PC_FDC 631 select ARCH_SPARSEMEM_ENABLE 632 select ARCH_USES_GETTIMEOFFSET 633 select CPU_SA110 634 select FIQ 635 select HAVE_IDE 636 select HAVE_PATA_PLATFORM 637 select ISA_DMA_API 638 select NEED_MACH_IO_H 639 select NEED_MACH_MEMORY_H 640 select NO_IOPORT_MAP 641 select VIRT_TO_BUS 642 help 643 On the Acorn Risc-PC, Linux can support the internal IDE disk and 644 CD-ROM interface, serial and parallel port, and the floppy drive. 645 646config ARCH_SA1100 647 bool "SA1100-based" 648 select ARCH_MTD_XIP 649 select ARCH_REQUIRE_GPIOLIB 650 select ARCH_SPARSEMEM_ENABLE 651 select CLKDEV_LOOKUP 652 select CLKSRC_MMIO 653 select CPU_FREQ 654 select CPU_SA1100 655 select GENERIC_CLOCKEVENTS 656 select HAVE_IDE 657 select IRQ_DOMAIN 658 select ISA 659 select MULTI_IRQ_HANDLER 660 select NEED_MACH_MEMORY_H 661 select SPARSE_IRQ 662 help 663 Support for StrongARM 11x0 based boards. 664 665config ARCH_S3C24XX 666 bool "Samsung S3C24XX SoCs" 667 select ARCH_REQUIRE_GPIOLIB 668 select ATAGS 669 select CLKDEV_LOOKUP 670 select CLKSRC_SAMSUNG_PWM 671 select GENERIC_CLOCKEVENTS 672 select GPIO_SAMSUNG 673 select HAVE_S3C2410_I2C if I2C 674 select HAVE_S3C2410_WATCHDOG if WATCHDOG 675 select HAVE_S3C_RTC if RTC_CLASS 676 select MULTI_IRQ_HANDLER 677 select NEED_MACH_IO_H 678 select SAMSUNG_ATAGS 679 help 680 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 681 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 682 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 683 Samsung SMDK2410 development board (and derivatives). 684 685config ARCH_S3C64XX 686 bool "Samsung S3C64XX" 687 select ARCH_REQUIRE_GPIOLIB 688 select ARM_AMBA 689 select ARM_VIC 690 select ATAGS 691 select CLKDEV_LOOKUP 692 select CLKSRC_SAMSUNG_PWM 693 select COMMON_CLK_SAMSUNG 694 select CPU_V6K 695 select GENERIC_CLOCKEVENTS 696 select GPIO_SAMSUNG 697 select HAVE_S3C2410_I2C if I2C 698 select HAVE_S3C2410_WATCHDOG if WATCHDOG 699 select HAVE_TCM 700 select NO_IOPORT_MAP 701 select PLAT_SAMSUNG 702 select PM_GENERIC_DOMAINS if PM 703 select S3C_DEV_NAND 704 select S3C_GPIO_TRACK 705 select SAMSUNG_ATAGS 706 select SAMSUNG_WAKEMASK 707 select SAMSUNG_WDT_RESET 708 help 709 Samsung S3C64XX series based systems 710 711config ARCH_DAVINCI 712 bool "TI DaVinci" 713 select ARCH_HAS_HOLES_MEMORYMODEL 714 select ARCH_REQUIRE_GPIOLIB 715 select CLKDEV_LOOKUP 716 select GENERIC_ALLOCATOR 717 select GENERIC_CLOCKEVENTS 718 select GENERIC_IRQ_CHIP 719 select HAVE_IDE 720 select USE_OF 721 select ZONE_DMA 722 help 723 Support for TI's DaVinci platform. 724 725config ARCH_OMAP1 726 bool "TI OMAP1" 727 depends on MMU 728 select ARCH_HAS_HOLES_MEMORYMODEL 729 select ARCH_OMAP 730 select ARCH_REQUIRE_GPIOLIB 731 select CLKDEV_LOOKUP 732 select CLKSRC_MMIO 733 select GENERIC_CLOCKEVENTS 734 select GENERIC_IRQ_CHIP 735 select HAVE_IDE 736 select IRQ_DOMAIN 737 select MULTI_IRQ_HANDLER 738 select NEED_MACH_IO_H if PCCARD 739 select NEED_MACH_MEMORY_H 740 select SPARSE_IRQ 741 help 742 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 743 744endchoice 745 746menu "Multiple platform selection" 747 depends on ARCH_MULTIPLATFORM 748 749comment "CPU Core family selection" 750 751config ARCH_MULTI_V4 752 bool "ARMv4 based platforms (FA526)" 753 depends on !ARCH_MULTI_V6_V7 754 select ARCH_MULTI_V4_V5 755 select CPU_FA526 756 757config ARCH_MULTI_V4T 758 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 759 depends on !ARCH_MULTI_V6_V7 760 select ARCH_MULTI_V4_V5 761 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 762 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 763 CPU_ARM925T || CPU_ARM940T) 764 765config ARCH_MULTI_V5 766 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 767 depends on !ARCH_MULTI_V6_V7 768 select ARCH_MULTI_V4_V5 769 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 770 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 771 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 772 773config ARCH_MULTI_V4_V5 774 bool 775 776config ARCH_MULTI_V6 777 bool "ARMv6 based platforms (ARM11)" 778 select ARCH_MULTI_V6_V7 779 select CPU_V6K 780 781config ARCH_MULTI_V7 782 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 783 default y 784 select ARCH_MULTI_V6_V7 785 select CPU_V7 786 select HAVE_SMP 787 788config ARCH_MULTI_V6_V7 789 bool 790 select MIGHT_HAVE_CACHE_L2X0 791 792config ARCH_MULTI_CPU_AUTO 793 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 794 select ARCH_MULTI_V5 795 796endmenu 797 798config ARCH_VIRT 799 bool "Dummy Virtual Machine" if ARCH_MULTI_V7 800 select ARM_AMBA 801 select ARM_GIC 802 select ARM_GIC_V3 803 select ARM_PSCI 804 select HAVE_ARM_ARCH_TIMER 805 806# 807# This is sorted alphabetically by mach-* pathname. However, plat-* 808# Kconfigs may be included either alphabetically (according to the 809# plat- suffix) or along side the corresponding mach-* source. 810# 811source "arch/arm/mach-mvebu/Kconfig" 812 813source "arch/arm/mach-alpine/Kconfig" 814 815source "arch/arm/mach-asm9260/Kconfig" 816 817source "arch/arm/mach-at91/Kconfig" 818 819source "arch/arm/mach-axxia/Kconfig" 820 821source "arch/arm/mach-bcm/Kconfig" 822 823source "arch/arm/mach-berlin/Kconfig" 824 825source "arch/arm/mach-clps711x/Kconfig" 826 827source "arch/arm/mach-cns3xxx/Kconfig" 828 829source "arch/arm/mach-davinci/Kconfig" 830 831source "arch/arm/mach-digicolor/Kconfig" 832 833source "arch/arm/mach-dove/Kconfig" 834 835source "arch/arm/mach-ep93xx/Kconfig" 836 837source "arch/arm/mach-footbridge/Kconfig" 838 839source "arch/arm/mach-gemini/Kconfig" 840 841source "arch/arm/mach-highbank/Kconfig" 842 843source "arch/arm/mach-hisi/Kconfig" 844 845source "arch/arm/mach-integrator/Kconfig" 846 847source "arch/arm/mach-iop32x/Kconfig" 848 849source "arch/arm/mach-iop33x/Kconfig" 850 851source "arch/arm/mach-iop13xx/Kconfig" 852 853source "arch/arm/mach-ixp4xx/Kconfig" 854 855source "arch/arm/mach-keystone/Kconfig" 856 857source "arch/arm/mach-ks8695/Kconfig" 858 859source "arch/arm/mach-meson/Kconfig" 860 861source "arch/arm/mach-moxart/Kconfig" 862 863source "arch/arm/mach-mv78xx0/Kconfig" 864 865source "arch/arm/mach-imx/Kconfig" 866 867source "arch/arm/mach-mediatek/Kconfig" 868 869source "arch/arm/mach-mxs/Kconfig" 870 871source "arch/arm/mach-netx/Kconfig" 872 873source "arch/arm/mach-nomadik/Kconfig" 874 875source "arch/arm/mach-nspire/Kconfig" 876 877source "arch/arm/plat-omap/Kconfig" 878 879source "arch/arm/mach-omap1/Kconfig" 880 881source "arch/arm/mach-omap2/Kconfig" 882 883source "arch/arm/mach-orion5x/Kconfig" 884 885source "arch/arm/mach-picoxcell/Kconfig" 886 887source "arch/arm/mach-pxa/Kconfig" 888source "arch/arm/plat-pxa/Kconfig" 889 890source "arch/arm/mach-mmp/Kconfig" 891 892source "arch/arm/mach-qcom/Kconfig" 893 894source "arch/arm/mach-realview/Kconfig" 895 896source "arch/arm/mach-rockchip/Kconfig" 897 898source "arch/arm/mach-sa1100/Kconfig" 899 900source "arch/arm/mach-socfpga/Kconfig" 901 902source "arch/arm/mach-spear/Kconfig" 903 904source "arch/arm/mach-sti/Kconfig" 905 906source "arch/arm/mach-s3c24xx/Kconfig" 907 908source "arch/arm/mach-s3c64xx/Kconfig" 909 910source "arch/arm/mach-s5pv210/Kconfig" 911 912source "arch/arm/mach-exynos/Kconfig" 913source "arch/arm/plat-samsung/Kconfig" 914 915source "arch/arm/mach-shmobile/Kconfig" 916 917source "arch/arm/mach-sunxi/Kconfig" 918 919source "arch/arm/mach-prima2/Kconfig" 920 921source "arch/arm/mach-tegra/Kconfig" 922 923source "arch/arm/mach-u300/Kconfig" 924 925source "arch/arm/mach-uniphier/Kconfig" 926 927source "arch/arm/mach-ux500/Kconfig" 928 929source "arch/arm/mach-versatile/Kconfig" 930 931source "arch/arm/mach-vexpress/Kconfig" 932source "arch/arm/plat-versatile/Kconfig" 933 934source "arch/arm/mach-vt8500/Kconfig" 935 936source "arch/arm/mach-w90x900/Kconfig" 937 938source "arch/arm/mach-zx/Kconfig" 939 940source "arch/arm/mach-zynq/Kconfig" 941 942# ARMv7-M architecture 943config ARCH_EFM32 944 bool "Energy Micro efm32" 945 depends on ARM_SINGLE_ARMV7M 946 select ARCH_REQUIRE_GPIOLIB 947 help 948 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 949 processors. 950 951config ARCH_LPC18XX 952 bool "NXP LPC18xx/LPC43xx" 953 depends on ARM_SINGLE_ARMV7M 954 select ARCH_HAS_RESET_CONTROLLER 955 select ARM_AMBA 956 select CLKSRC_LPC32XX 957 select PINCTRL 958 help 959 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 960 high performance microcontrollers. 961 962config ARCH_STM32 963 bool "STMicrolectronics STM32" 964 depends on ARM_SINGLE_ARMV7M 965 select ARCH_HAS_RESET_CONTROLLER 966 select ARMV7M_SYSTICK 967 select CLKSRC_STM32 968 select RESET_CONTROLLER 969 help 970 Support for STMicroelectronics STM32 processors. 971 972# Definitions to make life easier 973config ARCH_ACORN 974 bool 975 976config PLAT_IOP 977 bool 978 select GENERIC_CLOCKEVENTS 979 980config PLAT_ORION 981 bool 982 select CLKSRC_MMIO 983 select COMMON_CLK 984 select GENERIC_IRQ_CHIP 985 select IRQ_DOMAIN 986 987config PLAT_ORION_LEGACY 988 bool 989 select PLAT_ORION 990 991config PLAT_PXA 992 bool 993 994config PLAT_VERSATILE 995 bool 996 997source "arch/arm/firmware/Kconfig" 998 999source arch/arm/mm/Kconfig 1000 1001config IWMMXT 1002 bool "Enable iWMMXt support" 1003 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 1004 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 1005 help 1006 Enable support for iWMMXt context switching at run time if 1007 running on a CPU that supports it. 1008 1009config MULTI_IRQ_HANDLER 1010 bool 1011 help 1012 Allow each machine to specify it's own IRQ handler at run time. 1013 1014if !MMU 1015source "arch/arm/Kconfig-nommu" 1016endif 1017 1018config PJ4B_ERRATA_4742 1019 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 1020 depends on CPU_PJ4B && MACH_ARMADA_370 1021 default y 1022 help 1023 When coming out of either a Wait for Interrupt (WFI) or a Wait for 1024 Event (WFE) IDLE states, a specific timing sensitivity exists between 1025 the retiring WFI/WFE instructions and the newly issued subsequent 1026 instructions. This sensitivity can result in a CPU hang scenario. 1027 Workaround: 1028 The software must insert either a Data Synchronization Barrier (DSB) 1029 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 1030 instruction 1031 1032config ARM_ERRATA_326103 1033 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 1034 depends on CPU_V6 1035 help 1036 Executing a SWP instruction to read-only memory does not set bit 11 1037 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 1038 treat the access as a read, preventing a COW from occurring and 1039 causing the faulting task to livelock. 1040 1041config ARM_ERRATA_411920 1042 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1043 depends on CPU_V6 || CPU_V6K 1044 help 1045 Invalidation of the Instruction Cache operation can 1046 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1047 It does not affect the MPCore. This option enables the ARM Ltd. 1048 recommended workaround. 1049 1050config ARM_ERRATA_430973 1051 bool "ARM errata: Stale prediction on replaced interworking branch" 1052 depends on CPU_V7 1053 help 1054 This option enables the workaround for the 430973 Cortex-A8 1055 r1p* erratum. If a code sequence containing an ARM/Thumb 1056 interworking branch is replaced with another code sequence at the 1057 same virtual address, whether due to self-modifying code or virtual 1058 to physical address re-mapping, Cortex-A8 does not recover from the 1059 stale interworking branch prediction. This results in Cortex-A8 1060 executing the new code sequence in the incorrect ARM or Thumb state. 1061 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 1062 and also flushes the branch target cache at every context switch. 1063 Note that setting specific bits in the ACTLR register may not be 1064 available in non-secure mode. 1065 1066config ARM_ERRATA_458693 1067 bool "ARM errata: Processor deadlock when a false hazard is created" 1068 depends on CPU_V7 1069 depends on !ARCH_MULTIPLATFORM 1070 help 1071 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 1072 erratum. For very specific sequences of memory operations, it is 1073 possible for a hazard condition intended for a cache line to instead 1074 be incorrectly associated with a different cache line. This false 1075 hazard might then cause a processor deadlock. The workaround enables 1076 the L1 caching of the NEON accesses and disables the PLD instruction 1077 in the ACTLR register. Note that setting specific bits in the ACTLR 1078 register may not be available in non-secure mode. 1079 1080config ARM_ERRATA_460075 1081 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1082 depends on CPU_V7 1083 depends on !ARCH_MULTIPLATFORM 1084 help 1085 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1086 erratum. Any asynchronous access to the L2 cache may encounter a 1087 situation in which recent store transactions to the L2 cache are lost 1088 and overwritten with stale memory contents from external memory. The 1089 workaround disables the write-allocate mode for the L2 cache via the 1090 ACTLR register. Note that setting specific bits in the ACTLR register 1091 may not be available in non-secure mode. 1092 1093config ARM_ERRATA_742230 1094 bool "ARM errata: DMB operation may be faulty" 1095 depends on CPU_V7 && SMP 1096 depends on !ARCH_MULTIPLATFORM 1097 help 1098 This option enables the workaround for the 742230 Cortex-A9 1099 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1100 between two write operations may not ensure the correct visibility 1101 ordering of the two writes. This workaround sets a specific bit in 1102 the diagnostic register of the Cortex-A9 which causes the DMB 1103 instruction to behave as a DSB, ensuring the correct behaviour of 1104 the two writes. 1105 1106config ARM_ERRATA_742231 1107 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1108 depends on CPU_V7 && SMP 1109 depends on !ARCH_MULTIPLATFORM 1110 help 1111 This option enables the workaround for the 742231 Cortex-A9 1112 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1113 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1114 accessing some data located in the same cache line, may get corrupted 1115 data due to bad handling of the address hazard when the line gets 1116 replaced from one of the CPUs at the same time as another CPU is 1117 accessing it. This workaround sets specific bits in the diagnostic 1118 register of the Cortex-A9 which reduces the linefill issuing 1119 capabilities of the processor. 1120 1121config ARM_ERRATA_643719 1122 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1123 depends on CPU_V7 && SMP 1124 default y 1125 help 1126 This option enables the workaround for the 643719 Cortex-A9 (prior to 1127 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1128 register returns zero when it should return one. The workaround 1129 corrects this value, ensuring cache maintenance operations which use 1130 it behave as intended and avoiding data corruption. 1131 1132config ARM_ERRATA_720789 1133 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1134 depends on CPU_V7 1135 help 1136 This option enables the workaround for the 720789 Cortex-A9 (prior to 1137 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1138 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1139 As a consequence of this erratum, some TLB entries which should be 1140 invalidated are not, resulting in an incoherency in the system page 1141 tables. The workaround changes the TLB flushing routines to invalidate 1142 entries regardless of the ASID. 1143 1144config ARM_ERRATA_743622 1145 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1146 depends on CPU_V7 1147 depends on !ARCH_MULTIPLATFORM 1148 help 1149 This option enables the workaround for the 743622 Cortex-A9 1150 (r2p*) erratum. Under very rare conditions, a faulty 1151 optimisation in the Cortex-A9 Store Buffer may lead to data 1152 corruption. This workaround sets a specific bit in the diagnostic 1153 register of the Cortex-A9 which disables the Store Buffer 1154 optimisation, preventing the defect from occurring. This has no 1155 visible impact on the overall performance or power consumption of the 1156 processor. 1157 1158config ARM_ERRATA_751472 1159 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1160 depends on CPU_V7 1161 depends on !ARCH_MULTIPLATFORM 1162 help 1163 This option enables the workaround for the 751472 Cortex-A9 (prior 1164 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1165 completion of a following broadcasted operation if the second 1166 operation is received by a CPU before the ICIALLUIS has completed, 1167 potentially leading to corrupted entries in the cache or TLB. 1168 1169config ARM_ERRATA_754322 1170 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1171 depends on CPU_V7 1172 help 1173 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1174 r3p*) erratum. A speculative memory access may cause a page table walk 1175 which starts prior to an ASID switch but completes afterwards. This 1176 can populate the micro-TLB with a stale entry which may be hit with 1177 the new ASID. This workaround places two dsb instructions in the mm 1178 switching code so that no page table walks can cross the ASID switch. 1179 1180config ARM_ERRATA_754327 1181 bool "ARM errata: no automatic Store Buffer drain" 1182 depends on CPU_V7 && SMP 1183 help 1184 This option enables the workaround for the 754327 Cortex-A9 (prior to 1185 r2p0) erratum. The Store Buffer does not have any automatic draining 1186 mechanism and therefore a livelock may occur if an external agent 1187 continuously polls a memory location waiting to observe an update. 1188 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1189 written polling loops from denying visibility of updates to memory. 1190 1191config ARM_ERRATA_364296 1192 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1193 depends on CPU_V6 1194 help 1195 This options enables the workaround for the 364296 ARM1136 1196 r0p2 erratum (possible cache data corruption with 1197 hit-under-miss enabled). It sets the undocumented bit 31 in 1198 the auxiliary control register and the FI bit in the control 1199 register, thus disabling hit-under-miss without putting the 1200 processor into full low interrupt latency mode. ARM11MPCore 1201 is not affected. 1202 1203config ARM_ERRATA_764369 1204 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1205 depends on CPU_V7 && SMP 1206 help 1207 This option enables the workaround for erratum 764369 1208 affecting Cortex-A9 MPCore with two or more processors (all 1209 current revisions). Under certain timing circumstances, a data 1210 cache line maintenance operation by MVA targeting an Inner 1211 Shareable memory region may fail to proceed up to either the 1212 Point of Coherency or to the Point of Unification of the 1213 system. This workaround adds a DSB instruction before the 1214 relevant cache maintenance functions and sets a specific bit 1215 in the diagnostic control register of the SCU. 1216 1217config ARM_ERRATA_775420 1218 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1219 depends on CPU_V7 1220 help 1221 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1222 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1223 operation aborts with MMU exception, it might cause the processor 1224 to deadlock. This workaround puts DSB before executing ISB if 1225 an abort may occur on cache maintenance. 1226 1227config ARM_ERRATA_798181 1228 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1229 depends on CPU_V7 && SMP 1230 help 1231 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1232 adequately shooting down all use of the old entries. This 1233 option enables the Linux kernel workaround for this erratum 1234 which sends an IPI to the CPUs that are running the same ASID 1235 as the one being invalidated. 1236 1237config ARM_ERRATA_773022 1238 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1239 depends on CPU_V7 1240 help 1241 This option enables the workaround for the 773022 Cortex-A15 1242 (up to r0p4) erratum. In certain rare sequences of code, the 1243 loop buffer may deliver incorrect instructions. This 1244 workaround disables the loop buffer to avoid the erratum. 1245 1246endmenu 1247 1248source "arch/arm/common/Kconfig" 1249 1250menu "Bus support" 1251 1252config ISA 1253 bool 1254 help 1255 Find out whether you have ISA slots on your motherboard. ISA is the 1256 name of a bus system, i.e. the way the CPU talks to the other stuff 1257 inside your box. Other bus systems are PCI, EISA, MicroChannel 1258 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1259 newer boards don't support it. If you have ISA, say Y, otherwise N. 1260 1261# Select ISA DMA controller support 1262config ISA_DMA 1263 bool 1264 select ISA_DMA_API 1265 1266# Select ISA DMA interface 1267config ISA_DMA_API 1268 bool 1269 1270config PCI 1271 bool "PCI support" if MIGHT_HAVE_PCI 1272 help 1273 Find out whether you have a PCI motherboard. PCI is the name of a 1274 bus system, i.e. the way the CPU talks to the other stuff inside 1275 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1276 VESA. If you have PCI, say Y, otherwise N. 1277 1278config PCI_DOMAINS 1279 bool 1280 depends on PCI 1281 1282config PCI_DOMAINS_GENERIC 1283 def_bool PCI_DOMAINS 1284 1285config PCI_NANOENGINE 1286 bool "BSE nanoEngine PCI support" 1287 depends on SA1100_NANOENGINE 1288 help 1289 Enable PCI on the BSE nanoEngine board. 1290 1291config PCI_SYSCALL 1292 def_bool PCI 1293 1294config PCI_HOST_ITE8152 1295 bool 1296 depends on PCI && MACH_ARMCORE 1297 default y 1298 select DMABOUNCE 1299 1300source "drivers/pci/Kconfig" 1301source "drivers/pci/pcie/Kconfig" 1302 1303source "drivers/pcmcia/Kconfig" 1304 1305endmenu 1306 1307menu "Kernel Features" 1308 1309config HAVE_SMP 1310 bool 1311 help 1312 This option should be selected by machines which have an SMP- 1313 capable CPU. 1314 1315 The only effect of this option is to make the SMP-related 1316 options available to the user for configuration. 1317 1318config SMP 1319 bool "Symmetric Multi-Processing" 1320 depends on CPU_V6K || CPU_V7 1321 depends on GENERIC_CLOCKEVENTS 1322 depends on HAVE_SMP 1323 depends on MMU || ARM_MPU 1324 select IRQ_WORK 1325 help 1326 This enables support for systems with more than one CPU. If you have 1327 a system with only one CPU, say N. If you have a system with more 1328 than one CPU, say Y. 1329 1330 If you say N here, the kernel will run on uni- and multiprocessor 1331 machines, but will use only one CPU of a multiprocessor machine. If 1332 you say Y here, the kernel will run on many, but not all, 1333 uniprocessor machines. On a uniprocessor machine, the kernel 1334 will run faster if you say N here. 1335 1336 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1337 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1338 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1339 1340 If you don't know what to do here, say N. 1341 1342config SMP_ON_UP 1343 bool "Allow booting SMP kernel on uniprocessor systems" 1344 depends on SMP && !XIP_KERNEL && MMU 1345 default y 1346 help 1347 SMP kernels contain instructions which fail on non-SMP processors. 1348 Enabling this option allows the kernel to modify itself to make 1349 these instructions safe. Disabling it allows about 1K of space 1350 savings. 1351 1352 If you don't know what to do here, say Y. 1353 1354config ARM_CPU_TOPOLOGY 1355 bool "Support cpu topology definition" 1356 depends on SMP && CPU_V7 1357 default y 1358 help 1359 Support ARM cpu topology definition. The MPIDR register defines 1360 affinity between processors which is then used to describe the cpu 1361 topology of an ARM System. 1362 1363config SCHED_MC 1364 bool "Multi-core scheduler support" 1365 depends on ARM_CPU_TOPOLOGY 1366 help 1367 Multi-core scheduler support improves the CPU scheduler's decision 1368 making when dealing with multi-core CPU chips at a cost of slightly 1369 increased overhead in some places. If unsure say N here. 1370 1371config SCHED_SMT 1372 bool "SMT scheduler support" 1373 depends on ARM_CPU_TOPOLOGY 1374 help 1375 Improves the CPU scheduler's decision making when dealing with 1376 MultiThreading at a cost of slightly increased overhead in some 1377 places. If unsure say N here. 1378 1379config HAVE_ARM_SCU 1380 bool 1381 help 1382 This option enables support for the ARM system coherency unit 1383 1384config HAVE_ARM_ARCH_TIMER 1385 bool "Architected timer support" 1386 depends on CPU_V7 1387 select ARM_ARCH_TIMER 1388 select GENERIC_CLOCKEVENTS 1389 help 1390 This option enables support for the ARM architected timer 1391 1392config HAVE_ARM_TWD 1393 bool 1394 select CLKSRC_OF if OF 1395 help 1396 This options enables support for the ARM timer and watchdog unit 1397 1398config MCPM 1399 bool "Multi-Cluster Power Management" 1400 depends on CPU_V7 && SMP 1401 help 1402 This option provides the common power management infrastructure 1403 for (multi-)cluster based systems, such as big.LITTLE based 1404 systems. 1405 1406config MCPM_QUAD_CLUSTER 1407 bool 1408 depends on MCPM 1409 help 1410 To avoid wasting resources unnecessarily, MCPM only supports up 1411 to 2 clusters by default. 1412 Platforms with 3 or 4 clusters that use MCPM must select this 1413 option to allow the additional clusters to be managed. 1414 1415config BIG_LITTLE 1416 bool "big.LITTLE support (Experimental)" 1417 depends on CPU_V7 && SMP 1418 select MCPM 1419 help 1420 This option enables support selections for the big.LITTLE 1421 system architecture. 1422 1423config BL_SWITCHER 1424 bool "big.LITTLE switcher support" 1425 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU 1426 select ARM_CPU_SUSPEND 1427 select CPU_PM 1428 help 1429 The big.LITTLE "switcher" provides the core functionality to 1430 transparently handle transition between a cluster of A15's 1431 and a cluster of A7's in a big.LITTLE system. 1432 1433config BL_SWITCHER_DUMMY_IF 1434 tristate "Simple big.LITTLE switcher user interface" 1435 depends on BL_SWITCHER && DEBUG_KERNEL 1436 help 1437 This is a simple and dummy char dev interface to control 1438 the big.LITTLE switcher core code. It is meant for 1439 debugging purposes only. 1440 1441choice 1442 prompt "Memory split" 1443 depends on MMU 1444 default VMSPLIT_3G 1445 help 1446 Select the desired split between kernel and user memory. 1447 1448 If you are not absolutely sure what you are doing, leave this 1449 option alone! 1450 1451 config VMSPLIT_3G 1452 bool "3G/1G user/kernel split" 1453 config VMSPLIT_3G_OPT 1454 bool "3G/1G user/kernel split (for full 1G low memory)" 1455 config VMSPLIT_2G 1456 bool "2G/2G user/kernel split" 1457 config VMSPLIT_1G 1458 bool "1G/3G user/kernel split" 1459endchoice 1460 1461config PAGE_OFFSET 1462 hex 1463 default PHYS_OFFSET if !MMU 1464 default 0x40000000 if VMSPLIT_1G 1465 default 0x80000000 if VMSPLIT_2G 1466 default 0xB0000000 if VMSPLIT_3G_OPT 1467 default 0xC0000000 1468 1469config NR_CPUS 1470 int "Maximum number of CPUs (2-32)" 1471 range 2 32 1472 depends on SMP 1473 default "4" 1474 1475config HOTPLUG_CPU 1476 bool "Support for hot-pluggable CPUs" 1477 depends on SMP 1478 help 1479 Say Y here to experiment with turning CPUs off and on. CPUs 1480 can be controlled through /sys/devices/system/cpu. 1481 1482config ARM_PSCI 1483 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1484 depends on CPU_V7 1485 select ARM_PSCI_FW 1486 help 1487 Say Y here if you want Linux to communicate with system firmware 1488 implementing the PSCI specification for CPU-centric power 1489 management operations described in ARM document number ARM DEN 1490 0022A ("Power State Coordination Interface System Software on 1491 ARM processors"). 1492 1493# The GPIO number here must be sorted by descending number. In case of 1494# a multiplatform kernel, we just want the highest value required by the 1495# selected platforms. 1496config ARCH_NR_GPIO 1497 int 1498 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \ 1499 ARCH_ZYNQ 1500 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1501 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1502 default 416 if ARCH_SUNXI 1503 default 392 if ARCH_U8500 1504 default 352 if ARCH_VT8500 1505 default 288 if ARCH_ROCKCHIP 1506 default 264 if MACH_H4700 1507 default 0 1508 help 1509 Maximum number of GPIOs in the system. 1510 1511 If unsure, leave the default value. 1512 1513source kernel/Kconfig.preempt 1514 1515config HZ_FIXED 1516 int 1517 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ 1518 ARCH_S5PV210 || ARCH_EXYNOS4 1519 default 128 if SOC_AT91RM9200 1520 default 0 1521 1522choice 1523 depends on HZ_FIXED = 0 1524 prompt "Timer frequency" 1525 1526config HZ_100 1527 bool "100 Hz" 1528 1529config HZ_200 1530 bool "200 Hz" 1531 1532config HZ_250 1533 bool "250 Hz" 1534 1535config HZ_300 1536 bool "300 Hz" 1537 1538config HZ_500 1539 bool "500 Hz" 1540 1541config HZ_1000 1542 bool "1000 Hz" 1543 1544endchoice 1545 1546config HZ 1547 int 1548 default HZ_FIXED if HZ_FIXED != 0 1549 default 100 if HZ_100 1550 default 200 if HZ_200 1551 default 250 if HZ_250 1552 default 300 if HZ_300 1553 default 500 if HZ_500 1554 default 1000 1555 1556config SCHED_HRTICK 1557 def_bool HIGH_RES_TIMERS 1558 1559config THUMB2_KERNEL 1560 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1561 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1562 default y if CPU_THUMBONLY 1563 select AEABI 1564 select ARM_ASM_UNIFIED 1565 select ARM_UNWIND 1566 help 1567 By enabling this option, the kernel will be compiled in 1568 Thumb-2 mode. A compiler/assembler that understand the unified 1569 ARM-Thumb syntax is needed. 1570 1571 If unsure, say N. 1572 1573config THUMB2_AVOID_R_ARM_THM_JUMP11 1574 bool "Work around buggy Thumb-2 short branch relocations in gas" 1575 depends on THUMB2_KERNEL && MODULES 1576 default y 1577 help 1578 Various binutils versions can resolve Thumb-2 branches to 1579 locally-defined, preemptible global symbols as short-range "b.n" 1580 branch instructions. 1581 1582 This is a problem, because there's no guarantee the final 1583 destination of the symbol, or any candidate locations for a 1584 trampoline, are within range of the branch. For this reason, the 1585 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1586 relocation in modules at all, and it makes little sense to add 1587 support. 1588 1589 The symptom is that the kernel fails with an "unsupported 1590 relocation" error when loading some modules. 1591 1592 Until fixed tools are available, passing 1593 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1594 code which hits this problem, at the cost of a bit of extra runtime 1595 stack usage in some cases. 1596 1597 The problem is described in more detail at: 1598 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1599 1600 Only Thumb-2 kernels are affected. 1601 1602 Unless you are sure your tools don't have this problem, say Y. 1603 1604config ARM_ASM_UNIFIED 1605 bool 1606 1607config AEABI 1608 bool "Use the ARM EABI to compile the kernel" 1609 help 1610 This option allows for the kernel to be compiled using the latest 1611 ARM ABI (aka EABI). This is only useful if you are using a user 1612 space environment that is also compiled with EABI. 1613 1614 Since there are major incompatibilities between the legacy ABI and 1615 EABI, especially with regard to structure member alignment, this 1616 option also changes the kernel syscall calling convention to 1617 disambiguate both ABIs and allow for backward compatibility support 1618 (selected with CONFIG_OABI_COMPAT). 1619 1620 To use this you need GCC version 4.0.0 or later. 1621 1622config OABI_COMPAT 1623 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1624 depends on AEABI && !THUMB2_KERNEL 1625 help 1626 This option preserves the old syscall interface along with the 1627 new (ARM EABI) one. It also provides a compatibility layer to 1628 intercept syscalls that have structure arguments which layout 1629 in memory differs between the legacy ABI and the new ARM EABI 1630 (only for non "thumb" binaries). This option adds a tiny 1631 overhead to all syscalls and produces a slightly larger kernel. 1632 1633 The seccomp filter system will not be available when this is 1634 selected, since there is no way yet to sensibly distinguish 1635 between calling conventions during filtering. 1636 1637 If you know you'll be using only pure EABI user space then you 1638 can say N here. If this option is not selected and you attempt 1639 to execute a legacy ABI binary then the result will be 1640 UNPREDICTABLE (in fact it can be predicted that it won't work 1641 at all). If in doubt say N. 1642 1643config ARCH_HAS_HOLES_MEMORYMODEL 1644 bool 1645 1646config ARCH_SPARSEMEM_ENABLE 1647 bool 1648 1649config ARCH_SPARSEMEM_DEFAULT 1650 def_bool ARCH_SPARSEMEM_ENABLE 1651 1652config ARCH_SELECT_MEMORY_MODEL 1653 def_bool ARCH_SPARSEMEM_ENABLE 1654 1655config HAVE_ARCH_PFN_VALID 1656 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1657 1658config HAVE_GENERIC_RCU_GUP 1659 def_bool y 1660 depends on ARM_LPAE 1661 1662config HIGHMEM 1663 bool "High Memory Support" 1664 depends on MMU 1665 help 1666 The address space of ARM processors is only 4 Gigabytes large 1667 and it has to accommodate user address space, kernel address 1668 space as well as some memory mapped IO. That means that, if you 1669 have a large amount of physical memory and/or IO, not all of the 1670 memory can be "permanently mapped" by the kernel. The physical 1671 memory that is not permanently mapped is called "high memory". 1672 1673 Depending on the selected kernel/user memory split, minimum 1674 vmalloc space and actual amount of RAM, you may not need this 1675 option which should result in a slightly faster kernel. 1676 1677 If unsure, say n. 1678 1679config HIGHPTE 1680 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1681 depends on HIGHMEM 1682 default y 1683 help 1684 The VM uses one page of physical memory for each page table. 1685 For systems with a lot of processes, this can use a lot of 1686 precious low memory, eventually leading to low memory being 1687 consumed by page tables. Setting this option will allow 1688 user-space 2nd level page tables to reside in high memory. 1689 1690config CPU_SW_DOMAIN_PAN 1691 bool "Enable use of CPU domains to implement privileged no-access" 1692 depends on MMU && !ARM_LPAE 1693 default y 1694 help 1695 Increase kernel security by ensuring that normal kernel accesses 1696 are unable to access userspace addresses. This can help prevent 1697 use-after-free bugs becoming an exploitable privilege escalation 1698 by ensuring that magic values (such as LIST_POISON) will always 1699 fault when dereferenced. 1700 1701 CPUs with low-vector mappings use a best-efforts implementation. 1702 Their lower 1MB needs to remain accessible for the vectors, but 1703 the remainder of userspace will become appropriately inaccessible. 1704 1705config HW_PERF_EVENTS 1706 def_bool y 1707 depends on ARM_PMU 1708 1709config SYS_SUPPORTS_HUGETLBFS 1710 def_bool y 1711 depends on ARM_LPAE 1712 1713config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1714 def_bool y 1715 depends on ARM_LPAE 1716 1717config ARCH_WANT_GENERAL_HUGETLB 1718 def_bool y 1719 1720config ARM_MODULE_PLTS 1721 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1722 depends on MODULES 1723 help 1724 Allocate PLTs when loading modules so that jumps and calls whose 1725 targets are too far away for their relative offsets to be encoded 1726 in the instructions themselves can be bounced via veneers in the 1727 module's PLT. This allows modules to be allocated in the generic 1728 vmalloc area after the dedicated module memory area has been 1729 exhausted. The modules will use slightly more memory, but after 1730 rounding up to page size, the actual memory footprint is usually 1731 the same. 1732 1733 Say y if you are getting out of memory errors while loading modules 1734 1735source "mm/Kconfig" 1736 1737config FORCE_MAX_ZONEORDER 1738 int "Maximum zone order" 1739 default "12" if SOC_AM33XX 1740 default "9" if SA1111 || ARCH_EFM32 1741 default "11" 1742 help 1743 The kernel memory allocator divides physically contiguous memory 1744 blocks into "zones", where each zone is a power of two number of 1745 pages. This option selects the largest power of two that the kernel 1746 keeps in the memory allocator. If you need to allocate very large 1747 blocks of physically contiguous memory, then you may need to 1748 increase this value. 1749 1750 This config option is actually maximum order plus one. For example, 1751 a value of 11 means that the largest free memory block is 2^10 pages. 1752 1753config ALIGNMENT_TRAP 1754 bool 1755 depends on CPU_CP15_MMU 1756 default y if !ARCH_EBSA110 1757 select HAVE_PROC_CPU if PROC_FS 1758 help 1759 ARM processors cannot fetch/store information which is not 1760 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1761 address divisible by 4. On 32-bit ARM processors, these non-aligned 1762 fetch/store instructions will be emulated in software if you say 1763 here, which has a severe performance impact. This is necessary for 1764 correct operation of some network protocols. With an IP-only 1765 configuration it is safe to say N, otherwise say Y. 1766 1767config UACCESS_WITH_MEMCPY 1768 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1769 depends on MMU 1770 default y if CPU_FEROCEON 1771 help 1772 Implement faster copy_to_user and clear_user methods for CPU 1773 cores where a 8-word STM instruction give significantly higher 1774 memory write throughput than a sequence of individual 32bit stores. 1775 1776 A possible side effect is a slight increase in scheduling latency 1777 between threads sharing the same address space if they invoke 1778 such copy operations with large buffers. 1779 1780 However, if the CPU data cache is using a write-allocate mode, 1781 this option is unlikely to provide any performance gain. 1782 1783config SECCOMP 1784 bool 1785 prompt "Enable seccomp to safely compute untrusted bytecode" 1786 ---help--- 1787 This kernel feature is useful for number crunching applications 1788 that may need to compute untrusted bytecode during their 1789 execution. By using pipes or other transports made available to 1790 the process as file descriptors supporting the read/write 1791 syscalls, it's possible to isolate those applications in 1792 their own address space using seccomp. Once seccomp is 1793 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1794 and the task is only allowed to execute a few safe syscalls 1795 defined by each seccomp mode. 1796 1797config SWIOTLB 1798 def_bool y 1799 1800config IOMMU_HELPER 1801 def_bool SWIOTLB 1802 1803config XEN_DOM0 1804 def_bool y 1805 depends on XEN 1806 1807config XEN 1808 bool "Xen guest support on ARM" 1809 depends on ARM && AEABI && OF 1810 depends on CPU_V7 && !CPU_V6 1811 depends on !GENERIC_ATOMIC64 1812 depends on MMU 1813 select ARCH_DMA_ADDR_T_64BIT 1814 select ARM_PSCI 1815 select SWIOTLB_XEN 1816 help 1817 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1818 1819endmenu 1820 1821menu "Boot options" 1822 1823config USE_OF 1824 bool "Flattened Device Tree support" 1825 select IRQ_DOMAIN 1826 select OF 1827 help 1828 Include support for flattened device tree machine descriptions. 1829 1830config ATAGS 1831 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1832 default y 1833 help 1834 This is the traditional way of passing data to the kernel at boot 1835 time. If you are solely relying on the flattened device tree (or 1836 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1837 to remove ATAGS support from your kernel binary. If unsure, 1838 leave this to y. 1839 1840config DEPRECATED_PARAM_STRUCT 1841 bool "Provide old way to pass kernel parameters" 1842 depends on ATAGS 1843 help 1844 This was deprecated in 2001 and announced to live on for 5 years. 1845 Some old boot loaders still use this way. 1846 1847# Compressed boot loader in ROM. Yes, we really want to ask about 1848# TEXT and BSS so we preserve their values in the config files. 1849config ZBOOT_ROM_TEXT 1850 hex "Compressed ROM boot loader base address" 1851 default "0" 1852 help 1853 The physical address at which the ROM-able zImage is to be 1854 placed in the target. Platforms which normally make use of 1855 ROM-able zImage formats normally set this to a suitable 1856 value in their defconfig file. 1857 1858 If ZBOOT_ROM is not enabled, this has no effect. 1859 1860config ZBOOT_ROM_BSS 1861 hex "Compressed ROM boot loader BSS address" 1862 default "0" 1863 help 1864 The base address of an area of read/write memory in the target 1865 for the ROM-able zImage which must be available while the 1866 decompressor is running. It must be large enough to hold the 1867 entire decompressed kernel plus an additional 128 KiB. 1868 Platforms which normally make use of ROM-able zImage formats 1869 normally set this to a suitable value in their defconfig file. 1870 1871 If ZBOOT_ROM is not enabled, this has no effect. 1872 1873config ZBOOT_ROM 1874 bool "Compressed boot loader in ROM/flash" 1875 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1876 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1877 help 1878 Say Y here if you intend to execute your compressed kernel image 1879 (zImage) directly from ROM or flash. If unsure, say N. 1880 1881config ARM_APPENDED_DTB 1882 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1883 depends on OF 1884 help 1885 With this option, the boot code will look for a device tree binary 1886 (DTB) appended to zImage 1887 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1888 1889 This is meant as a backward compatibility convenience for those 1890 systems with a bootloader that can't be upgraded to accommodate 1891 the documented boot protocol using a device tree. 1892 1893 Beware that there is very little in terms of protection against 1894 this option being confused by leftover garbage in memory that might 1895 look like a DTB header after a reboot if no actual DTB is appended 1896 to zImage. Do not leave this option active in a production kernel 1897 if you don't intend to always append a DTB. Proper passing of the 1898 location into r2 of a bootloader provided DTB is always preferable 1899 to this option. 1900 1901config ARM_ATAG_DTB_COMPAT 1902 bool "Supplement the appended DTB with traditional ATAG information" 1903 depends on ARM_APPENDED_DTB 1904 help 1905 Some old bootloaders can't be updated to a DTB capable one, yet 1906 they provide ATAGs with memory configuration, the ramdisk address, 1907 the kernel cmdline string, etc. Such information is dynamically 1908 provided by the bootloader and can't always be stored in a static 1909 DTB. To allow a device tree enabled kernel to be used with such 1910 bootloaders, this option allows zImage to extract the information 1911 from the ATAG list and store it at run time into the appended DTB. 1912 1913choice 1914 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1915 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1916 1917config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1918 bool "Use bootloader kernel arguments if available" 1919 help 1920 Uses the command-line options passed by the boot loader instead of 1921 the device tree bootargs property. If the boot loader doesn't provide 1922 any, the device tree bootargs property will be used. 1923 1924config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1925 bool "Extend with bootloader kernel arguments" 1926 help 1927 The command-line arguments provided by the boot loader will be 1928 appended to the the device tree bootargs property. 1929 1930endchoice 1931 1932config CMDLINE 1933 string "Default kernel command string" 1934 default "" 1935 help 1936 On some architectures (EBSA110 and CATS), there is currently no way 1937 for the boot loader to pass arguments to the kernel. For these 1938 architectures, you should supply some command-line options at build 1939 time by entering them here. As a minimum, you should specify the 1940 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1941 1942choice 1943 prompt "Kernel command line type" if CMDLINE != "" 1944 default CMDLINE_FROM_BOOTLOADER 1945 depends on ATAGS 1946 1947config CMDLINE_FROM_BOOTLOADER 1948 bool "Use bootloader kernel arguments if available" 1949 help 1950 Uses the command-line options passed by the boot loader. If 1951 the boot loader doesn't provide any, the default kernel command 1952 string provided in CMDLINE will be used. 1953 1954config CMDLINE_EXTEND 1955 bool "Extend bootloader kernel arguments" 1956 help 1957 The command-line arguments provided by the boot loader will be 1958 appended to the default kernel command string. 1959 1960config CMDLINE_FORCE 1961 bool "Always use the default kernel command string" 1962 help 1963 Always use the default kernel command string, even if the boot 1964 loader passes other arguments to the kernel. 1965 This is useful if you cannot or don't want to change the 1966 command-line options your boot loader passes to the kernel. 1967endchoice 1968 1969config XIP_KERNEL 1970 bool "Kernel Execute-In-Place from ROM" 1971 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1972 help 1973 Execute-In-Place allows the kernel to run from non-volatile storage 1974 directly addressable by the CPU, such as NOR flash. This saves RAM 1975 space since the text section of the kernel is not loaded from flash 1976 to RAM. Read-write sections, such as the data section and stack, 1977 are still copied to RAM. The XIP kernel is not compressed since 1978 it has to run directly from flash, so it will take more space to 1979 store it. The flash address used to link the kernel object files, 1980 and for storing it, is configuration dependent. Therefore, if you 1981 say Y here, you must know the proper physical address where to 1982 store the kernel image depending on your own flash memory usage. 1983 1984 Also note that the make target becomes "make xipImage" rather than 1985 "make zImage" or "make Image". The final kernel binary to put in 1986 ROM memory will be arch/arm/boot/xipImage. 1987 1988 If unsure, say N. 1989 1990config XIP_PHYS_ADDR 1991 hex "XIP Kernel Physical Location" 1992 depends on XIP_KERNEL 1993 default "0x00080000" 1994 help 1995 This is the physical address in your flash memory the kernel will 1996 be linked for and stored to. This address is dependent on your 1997 own flash usage. 1998 1999config KEXEC 2000 bool "Kexec system call (EXPERIMENTAL)" 2001 depends on (!SMP || PM_SLEEP_SMP) 2002 depends on !CPU_V7M 2003 select KEXEC_CORE 2004 help 2005 kexec is a system call that implements the ability to shutdown your 2006 current kernel, and to start another kernel. It is like a reboot 2007 but it is independent of the system firmware. And like a reboot 2008 you can start any kernel with it, not just Linux. 2009 2010 It is an ongoing process to be certain the hardware in a machine 2011 is properly shutdown, so do not be surprised if this code does not 2012 initially work for you. 2013 2014config ATAGS_PROC 2015 bool "Export atags in procfs" 2016 depends on ATAGS && KEXEC 2017 default y 2018 help 2019 Should the atags used to boot the kernel be exported in an "atags" 2020 file in procfs. Useful with kexec. 2021 2022config CRASH_DUMP 2023 bool "Build kdump crash kernel (EXPERIMENTAL)" 2024 help 2025 Generate crash dump after being started by kexec. This should 2026 be normally only set in special crash dump kernels which are 2027 loaded in the main kernel with kexec-tools into a specially 2028 reserved region and then later executed after a crash by 2029 kdump/kexec. The crash dump kernel must be compiled to a 2030 memory address not used by the main kernel 2031 2032 For more details see Documentation/kdump/kdump.txt 2033 2034config AUTO_ZRELADDR 2035 bool "Auto calculation of the decompressed kernel image address" 2036 help 2037 ZRELADDR is the physical address where the decompressed kernel 2038 image will be placed. If AUTO_ZRELADDR is selected, the address 2039 will be determined at run-time by masking the current IP with 2040 0xf8000000. This assumes the zImage being placed in the first 128MB 2041 from start of memory. 2042 2043endmenu 2044 2045menu "CPU Power Management" 2046 2047source "drivers/cpufreq/Kconfig" 2048 2049source "drivers/cpuidle/Kconfig" 2050 2051endmenu 2052 2053menu "Floating point emulation" 2054 2055comment "At least one emulation must be selected" 2056 2057config FPE_NWFPE 2058 bool "NWFPE math emulation" 2059 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2060 ---help--- 2061 Say Y to include the NWFPE floating point emulator in the kernel. 2062 This is necessary to run most binaries. Linux does not currently 2063 support floating point hardware so you need to say Y here even if 2064 your machine has an FPA or floating point co-processor podule. 2065 2066 You may say N here if you are going to load the Acorn FPEmulator 2067 early in the bootup. 2068 2069config FPE_NWFPE_XP 2070 bool "Support extended precision" 2071 depends on FPE_NWFPE 2072 help 2073 Say Y to include 80-bit support in the kernel floating-point 2074 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2075 Note that gcc does not generate 80-bit operations by default, 2076 so in most cases this option only enlarges the size of the 2077 floating point emulator without any good reason. 2078 2079 You almost surely want to say N here. 2080 2081config FPE_FASTFPE 2082 bool "FastFPE math emulation (EXPERIMENTAL)" 2083 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2084 ---help--- 2085 Say Y here to include the FAST floating point emulator in the kernel. 2086 This is an experimental much faster emulator which now also has full 2087 precision for the mantissa. It does not support any exceptions. 2088 It is very simple, and approximately 3-6 times faster than NWFPE. 2089 2090 It should be sufficient for most programs. It may be not suitable 2091 for scientific calculations, but you have to check this for yourself. 2092 If you do not feel you need a faster FP emulation you should better 2093 choose NWFPE. 2094 2095config VFP 2096 bool "VFP-format floating point maths" 2097 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2098 help 2099 Say Y to include VFP support code in the kernel. This is needed 2100 if your hardware includes a VFP unit. 2101 2102 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2103 release notes and additional status information. 2104 2105 Say N if your target does not have VFP hardware. 2106 2107config VFPv3 2108 bool 2109 depends on VFP 2110 default y if CPU_V7 2111 2112config NEON 2113 bool "Advanced SIMD (NEON) Extension support" 2114 depends on VFPv3 && CPU_V7 2115 help 2116 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2117 Extension. 2118 2119config KERNEL_MODE_NEON 2120 bool "Support for NEON in kernel mode" 2121 depends on NEON && AEABI 2122 help 2123 Say Y to include support for NEON in kernel mode. 2124 2125endmenu 2126 2127menu "Userspace binary formats" 2128 2129source "fs/Kconfig.binfmt" 2130 2131endmenu 2132 2133menu "Power management options" 2134 2135source "kernel/power/Kconfig" 2136 2137config ARCH_SUSPEND_POSSIBLE 2138 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2139 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2140 def_bool y 2141 2142config ARM_CPU_SUSPEND 2143 def_bool PM_SLEEP 2144 2145config ARCH_HIBERNATION_POSSIBLE 2146 bool 2147 depends on MMU 2148 default y if ARCH_SUSPEND_POSSIBLE 2149 2150endmenu 2151 2152source "net/Kconfig" 2153 2154source "drivers/Kconfig" 2155 2156source "drivers/firmware/Kconfig" 2157 2158source "fs/Kconfig" 2159 2160source "arch/arm/Kconfig.debug" 2161 2162source "security/Kconfig" 2163 2164source "crypto/Kconfig" 2165if CRYPTO 2166source "arch/arm/crypto/Kconfig" 2167endif 2168 2169source "lib/Kconfig" 2170 2171source "arch/arm/kvm/Kconfig" 2172